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CICC 2019: Austin, TX, USA
- IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. IEEE 2019, ISBN 978-1-5386-9395-7
- Sung-Gun Cho, Edith Beigné, Zhengya Zhang
:
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. 1-4 - Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. 1-4 - Jae-Won Nam
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. 1-4 - Yukun Zhu
A Low Power Sub-harmonic Self-Oscillating Mixer with 16.8dB conversion loss at 310GHz in 65nm CMOS. 1-4 - Xiaolong Liu, Zhiqiang Huang, Jun Yin
Magnetic-Tuning Millimeter-Wave CMOS Oscillators (Invited Paper). 1-8 - Huan Wang, Hossein Mohammadnezhad, Damla Dimlioglu, Payam Heydari:
A 100-120GHz 20Gbps Bits-to-RF 16QAM Transmitter Using 1-bit Digital-to-Analog Interface. 1-4 - Nikolaos Papadopoulos, Soeren Steudel, Auke Jisk Kronemeijer, Marc Ameys, Kris Myny
Flexible 16nJ/c.s. 134S/s 6b MIM C-2C ADC using Dual Gate Self-aligned Unipolar Metal-Oxide TFTs. 1-4 - Massimo Alioto, Sachin Taneja:
Enabling Ubiquitous Hardware Security via Energy-Efficient Primitives and Systems : (Invited Paper). 1-8 - Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez:
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. 1-4 - Somok Mondal
A107 µW MedRadio Injection-Locked Clock Multiplier with a CTAT-biased 126 ppm/°C Ring Oscillator. 1-4 - Ayman Shabra, Padraig Cooney, Adalberto Cantoni, Joshua Bamford, Stacy Ho, Michael Ashburn:
A 20 kHz Bandwidth Resistive DAC with 135 dBA Dynamic Range and 125 dB THD. 1-4 - Nicolas Butzen, Michiel Steyaert
Advanced Multiphasing: Pushing the Envelope of Fully Integrated Power Conversion. 1-8 - Beomsoo Park, Mark M. Tehranipoor, Domenic Forte
A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability. 1-4 - Shih-Hung Chen:
Esd Challenges in Advanced Finfet and Gaa Nanowire cmos Technologies: Designing Diode Based ESD Protection in Advanced State of the Art Technologies. 1-100 - Xiaoliang Li
A High Dynamic Range CMOS-MEMS Accelerometer Array with Drift Compensation and Fine-Grain Offset Compensation. 1-4 - Dmytro Cherniak, Carlo Samori
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper). 1-8 - Aritra Banerjee
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). 1-11 - Peiyu Chen, Dai Li, Zhanghao Yu, Qing Jin
A 0.84pJ/cycle Wheatstone Bridge Based CMOS RC Oscillator with Reconfigurable Frequencies. 1-4 - Aili Wang, Chixiao Chen, Chuanjin Richard Shi:
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. 1-4 - Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. 1-4 - Luya Zhang
A Microwave-Optical Biosensor with 5.4ppm Label/Reference-free Long-term Stability and Single Photon Sensitivity in 28nm Bulk CMOS. 1-4 - Hoi-Jun Yoo:
Mobile Deep Learning Processors on the Edge. 1-91 - Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan
BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design. 1-8 - Hassan Saif, Muhammad Bilawal Khan
A 17V-to-45V Input 25 μW-to-10mW Output Power, 90.2%-Peak-Efficiency SC DC-DC Converter with Recursive Output Connection for High-Voltage Energy Harvesting. 1-4 - Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim:
Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors. 1-4 - Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET. 1-4 - Bai Nguyen, Nghia Tang, Zhiyuan Zhou, Wookpyo Hong, Deukhyoun Heo, Yangyang Tang, Philipp Zhang:
A Sub-1V Analog-Assisted Inverter-Based Digital Low-Dropout Regulator with a Fast Response Time at 25mA/100ps and 99.4% Current Efficiency. 1-4 - Chung-Ming Yang, Tai-Haur Kuo:
A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators. 1-4 - Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. 1-3 - Swarup Bhunia
New Frontiers in Hardware Security in the IoT Regime. 1-55 - Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. 1-4 - Jun-Chau Chien:
A 20.1-μW 1.8 -GHz Near-Field Dielectric Plethysmography (NF-DPG) Heart-Rate Sensor with Time-based Edge Sampling. 1-4 - Mohsen Hassanpourghadi, Mike Shuo-Wei Chen:
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. 1-4 - Baibhab Chatterjee
A Wearable Real-time CMOS Dosimeter with Integrated Zero-bias Floating-Gate Sensor and an 861nW 18-bit Energy-Resolution Scalable Time-based Radiation to Digital Converter. 1-4 - Farrokh Ayazi, Haoran Wen, Yaesuk Jeong, Pranav Gupta
High-Q Timing and Inertial Measurement Unit Chip (TIMU) with 3D Wafer-Level Packaging. 1-8 - Mohammed Affan Zidan, Wei D. Lu
RRAM fabric for neuromorphic and reconfigurable compute-in-memory systems. 1-8 - Miguel E. Perez, Michael A. Sperling, Timothy E. Diemoz, John F. Bulzacchelli, Zeynep Toprak Deniz:
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS. 1-4 - Dengquan Li, Jiaxin Liu
A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. 1-4 - Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. 1-4 - Haowei Jiang, Chih-Cheng Huang, Matthew R. Chan, Drew A. Hall
A 2-in-1 Temperature and Humidity Sensor Achieving 62 fJ·K2 and 0.83 pJ·(%RH)2. 1-4 - Abdullah Abdulslam, Bao Huu Lam, Patrick P. Mercier
A Battery-Connected Symmetric Modified Multilevel Ladder Converter Achieving 0.45W/mm2 Power Density and 90% Peak Efficiency. 1-4 - Marc Pons
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. 1-4 - Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. 1-4 - Arianna Coccia, Danilo Manstretta, Rinaldo Castello
A Wideband Saw-Less Transmitter Operating in Closed-Loop With Embedded N-Path Filtering. 1-4 - Dongyi Liao, Yucai Zhang, Zhenqi Chen, Yanjie Wang, Fa Foster Dai:
An mm-Wave Synthesizer with Low In-Band Noise and Robust Locking Reference-Sampling PLL. 1-4 - Yihan Zhang, Kenneth L. Shepard:
A 0.6-mm2 Powering and Data Telemetry System Compatible with Ultrasound B-Mode Imaging for Freely Moving Biomedical Sensor Systems. 1-4 - Yanlong Zhang
A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. 1-4 - Zhan Su, Hechen Wang
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS. 1-4 - Yogesh Ramadass:
High Voltage Devices, Topologies and Gate Drivers. 1-73 - Xiaoyang Wang, Patrick P. Mercier
A Charge-Pump-based Digital LDO Employing an AC-Coupled High-Z Feedback Loop Towards a sub-4fs FoM and a 105, 000x Stable Dynamic Current Range. 1-4 - Patrick P. Mercier
Power Management for the Internet of Things. 1-105 - Mark B. Ritter:
Quantum Technology Overview. 1-69 - Wen-Chuen Liu, Robert C. N. Pilawa-Podgurski, Pei Han Ng:
An 83mA 96.8% Peak Efficiency 3-Level Boost Converter with Full-Range Auto-Capacitor-Calibrating Pulse Frequency Modulation. 1-4 - Marc Erett, Declan Carey, Ronan Casey, James Hudner, Kevin Geary, Ted Lee, Mayank Raj, Hongtao Zhang, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Nakul Narang, Pedro Neto, Bruce Xu, Winson Lin, Kee Hian Tan, Yohan Frans, Ken Chang:
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET. 1-8 - Mingqiang Guo
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. 1-4 - Ganesh Balamurugan, Ajay Balankutty, Chun-Ming Hsu:
56G/112G Link Foundations Standards, Link Budgets & Models. 1-95 - Jaeeun Jang, Joonsung Bae, Hoi-Jun Yoo:
Understanding Body Channel Communication : A review: from history to the future applications. 1-8 - Bo Xiong, Yida Li
A 7×7×2mm3 8.6-μ 500-kb/s Transmitter with Robust Injection-Locking Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications. 1-4 - Xuyang Lu, Xue Wu, Hooman Saeidi, Kaushik Sengupta
A Multi-Port Dual Polarized Antenna Coupled mm-Wave CMOS Receiver with Element-level Pattern and Notch Programmability and Passive Interferer Rejection Capability. 1-4 - Taewoong Kim, Youngcheol Chae:
A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR. 1-4 - Berkay Çiftci
Low-Cost Fully Autonomous Piezoelectric Energy Harvesting Interface Circuit with up to 6.14x Power Capacity Gain. 1-4 - Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
An Sram-Based Accelerator for Solving Partial Differential Equations. 1-4 - Alessio Santiccioli, Mario Mercandelli
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power. 1-4 - Tiago L. Costa
A CMOS 2D Transmit Beamformer With Integrated PZT Ultrasound Transducers For Neuromodulation. 1-4 - Yusang Chun, Tejasvi Anand:
A 13.6-16Gb/s Wireline Transceiver with Dicode Encoding and Sequence Detection Decoding for Equalizing 24.2dB with 2.56pJ/bit in 65nm CMOS. 1-4 - Liang Fang, Ping Gui:
A 14nV/√Hz 14μW Chopper Instrumentation Amplifier with Dynamic Offset Zeroing (DOZ) Technique for Ripple Reduction. 1-4 - Reza Erfani, Fatemeh Marefat, Pedram Mohseni:
A 1-10MHz Frequency-Aware CMOS Active Rectifier with Dual-Loop Adaptive Delay Compensation and >230 mW Output Power for Capacitively Powered Biomedical Implants. 1-4 - James T. Doyle, Jonathon C. Stiff, Santosh Kulkarni, Aysel Yildiz:
A Low Cost 100 MHz 2-Stage PSiP and Evolution to a Co-Packaged/Fully-Integrated Voltage Regulator for SoC Power Delivery. 1-8 - Azita Emami
High-Speed Optical Links. 1-103 - Avi Miller, Yizhak Shifman
A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10. 1-4 - Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin:
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. 1-4 - Yang-Hang Fan
A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS. 1-4 - Danny Yoo, Mohammad Bagherbeik
A 30Gb/s 2x Half-Baud-Rate CDR. 1-4 - Fei Wang, Hua Wang
A Noise Circulating Cross-Coupled VCO with a 195.6dBc/Hz FoM and 50kHz 1/f3 Noise Corner. 1-4 - Laura Fick, Dave Fick:
Introduction to Compute-in-Memory. 1-65 - Ali Mostajeran, Hamidreza Aghasi
Fully Integrated Solutions for High Resolution Terahertz Imaging (Invited). 1-8 - Saurabh Chaubey, Ramesh Harjani:
A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS. 1-4 - Alvin Leng Sun Loke, C. K. Lee, Burton Mike Leary:
Nanoscale CMOS Implications on Analog/Mixed-Signal Design. 1-57 - Hon-Piu Lam
Spatial Temperature Sensor with Distributed MASH Modulators. 1-4 - Tao Tang, Jeong Hoan Park, Lian Zhang, Kian Ann Ng, Jerald Yoo
An 8-channel 2.1 μ W0.017 mm2 0.04% Gain Mismatch Bio-potential Recording AFE using Group-Chopping Technique. 1-4 - Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. 1-4 - Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. 1-4 - Insik Yoon, Ningyuan Cao, Anvesha Amaravati, Arijit Raychowdhury:
A 55nm 50nJ/encode 13nJ/decode Homomorphic Encryption Crypto-Engine for IoT Nodes to Enable Secure Computation on Encrypted Data. 1-4 - Gyusung Park, Minsu Kim, Nakul Pande, Po-Wei Chiu, Jeehwan Song, Chris H. Kim:
A Counter based ADC Non-linearity Measurement Circuit and Its Application to Reliability Testing. 1-4 - Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. 1-4 - Vincent W. Leung
Distributed Microscale Brain Implants with Wireless Power Transfer and Mbps Bi-directional Networked Communications. 1-4 - Doohwan Jung, Jong Seok Park, Sensen Li, Tzu-Yuan Huang, Huan Zhao, Hua Wang
A 1.2 V Single Supply Hybrid Current-/Voltage-Mode Three-Way Digital Doherty PA with Built-In Large-Signal Phase Compensation Achieving Less-Than 5° AM-PM. 1-4 - Yung C. Liang, Ruize Sun, Yee-Chia Yeo, Cezhou Zhao:
Development of GaN Monolithic Integrated Circuits for Power Conversion. 1-4 - Jianglin Du
A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. 1-4 - Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto:
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. 1-8 - Elad Alon:
Mixed-Signal Electrical Interfaces. 1-57 - Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew:
A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. 1-4 - Ahmed Hamza, Hussam AlShammary, Cameron Hill
A 52-dB Self-Interference Rejection Receiver using RF Code-Domain Signal Processing. 1-4 - Yohan Frans:
ADC-based Wireline Transceiver. 1-89 - Mo Huang
An Analog-Proportional Digital-Integral Multi-Loop Digital LDO with Fast Response, Improved PSR and Zero Minimum Load Current. 1-4 - Xi Chen, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen G. Tell, C. Thomas Gray:
Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET. 1-4 - Shi Bu, Sameed Hameed
An LPTV Noise Cancellation Technique for a 0.9-V Filtering-by-Aliasing Receiver Front-End with >67-dB Stopband Rejection. 1-4 - Sri Navaneeth Easwaran
Portable and Scalable High Voltage Circuits for Automotive Applications in BiCMOS Processes. 1-87 - Pieter Harpe:
A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-Rejection Passive FIR Filter. 1-4 - Sreenil Saha, Samuel Burri, Claudio Bruschini
Time Domain NIRS Optode based on Null/Small Source-Detector Distance for Wearable Applications. 1-8 - Yong Qu
A Monolithic I2V2-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting. 1-4 - Viveka Konandur Rajanna
Low-Swing Links with Dynamic Energy-Quality Trade-off for Error-Resilient Applications. 1-4 - Muya Chang, Li-Hsiang Lin
Optimo: A 65Nm 270Mhz 143.2Mw Programmable Spatial-Array-Processor With A Hierarchical Multi-Cast On-Chip Network For Solving Distributed Optimizations. 1-4 - Jinbo Li, Ran Shu, Qun Jane Gu:
An 8.5-11 GHz CMOS Transmitter with >19 dBm OP1dB and 24 % Efficiency. 1-4 - Wing-Hung Ki
Analysis and IC Techniques of Wireless Power Transfer Circuits. 1-88 - Alessandra Nardi, Samir Camdzic, Antonino Armato, Francesco Lertora:
Design-For-Safety For Automotive IC Design: Challenges And Opportunities. 1-8 - Peigen Zhou, Jixin Chen, Pinpin Yan, Zhe Chen, Debin Hou, Wei Hong:
A 280-325 GHz Frequency Multiplier Chain With 2.5 dBm Peak Output Power. 1-4 - Hossein Mohammadnezhad, Huan Wang, Andreia Cathelin, Payam Heydari:
A Single-Channel RF-to-Bits 36Gbps 8PSK RX with Direct Demodulation in RF Domain. 1-4 - Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany:
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. 1-4 - Mohamed Megahed, Y. Ramadass, Tejasvi Anand:
A Sub 1μW Switched Source + Capacitor Architecture Free of Top/Bottom Plate Parasitic Switching Loss Achieving Peak Efficiency of 80.66% at a Regulated 1.8V Output in 180nm. 1-4 - Greg Yeric:
IC Design After Moore's Law. 1-150 - Alvin Leng Sun Loke, Da Yang, Tin Tin Wee, Jonathan L. Holland, Patrick Isakanian, Kern Rim, Sam Yang, Jacob S. Schneider, Giri Nallapati, Sreeker Dundigal, Hasnain Lakdawala, Behnam Amelifard, Chulkyu Lee, Betty McGovern, Paul S. Holdaway, Xiaohua Kong, Burton M. Leary:
Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond. 1-8 - Hossein Jalili
A 219-to-238-GHz Coupled Standing-Wave VCO with 3.4-dBm Peak Output Power in 65nm CMOS. 1-4 - Eric Chang, Nathan Narevsky, Krishna Settaluri, Elad Alon:
BAG: A Process-Portable Framework for Generator-based AMS Circuit Design. 1-20 - Soumya Bose, Tejasvi Anand, Matthew L. Johnston:
A 3.5mV Input, 82% Peak Efficiency Boost Converter with Loss-Optimized MPPT and 50mV Integrated Cold-Start for Thermoelectric Energy Harvesting. 1-4 - Xiaohua Huang
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. 1-4 - Hao Tang, Suresh Venkatesh
2D Magnetic Sensor Array for Real-time Cell Tracking and Multi-site Detection with Increased Robustness and Flow-rate. 1-4 - Tsung-Chih Hung, Tai-Haur Kuo:
A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth. 1-4 - Bangan Liu, Yuncheng Zhang
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. 1-4 - Héctor Gómez, Julian Arenas, Camilo Rojas, David Reyes, Alex Mantilla, Elkim Roa
A 68/36ppm/○C Tc 32.768Khz-To-1Mhz Rc-Based Oscillator With 72/6Pj Start-Up Energy. 1-4 - Somayeh Khiyabani, Hamid Khatibi, Ehsan Afshari:
A Compact 275 GHz Harmonic VCO with -2.6 dBm Output Power in a 130 nm SiGe Process. 1-4 - Yongjun Li
An AC-Coupled Stacked Dual Active Bridge Hybrid DC-DC Converter for Battery-to-Processor Power Delivery with 87.2% Peak Efficiency and High Accuracy Loadline Regulation. 1-4 - Daniel S. Truesdell
A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution. 1-4 - Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer. 1-4 - Koji Sakui, Takayuki Ohba:
Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform. 1-6 - Makoto Nagata
On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. 1-6
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