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Robert C. N. Pilawa-Podgurski
Person information
- affiliation: University of California, Berkeley, USA
- affiliation (former): University of Illinois, Urbana-Champaign, USA
- affiliation (PhD 2012): MIT, Cambridge, MA, USA
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2020 – today
- 2021
- [j7]Nilanjan Pal
, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications. IEEE J. Solid State Circuits 56(11): 3499-3510 (2021) - [c9]Pourya Assem, Robert C. N. Pilawa-Podgurski:
Quad Gate-Driver Controller with Start-Up and Shutdown for Cascaded Resonant Switched-Capacitor Converter. CICC 2021: 1-2 - 2020
- [j6]Wen-Chuen Liu
A Three-Level Boost Converter With Full-Range Auto-Capacitor-Compensation Pulse Frequency Modulation. IEEE J. Solid State Circuits 55(3): 744-755 (2020) - [j5]Pourya Assem
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS. IEEE J. Solid State Circuits 55(9): 2513-2528 (2020) - [c8]Nilanjan Pal, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS. CICC 2020: 1-4
2010 – 2019
- 2019
- [j4]James J. Sluss
2018 IEEE Education Society Awards, 2018 Frontiers in Education Conference Awards, and Selected IEEE Awards. IEEE Trans. Educ. 62(1): 57-63 (2019) - [c7]Wen-Chuen Liu, Robert C. N. Pilawa-Podgurski, Pei Han Ng:
An 83mA 96.8% Peak Efficiency 3-Level Boost Converter with Full-Range Auto-Capacitor-Calibrating Pulse Frequency Modulation. CICC 2019: 1-4 - [d1]Yue Cao
One Year Submillisecond Fast Solar Database. IEEE DataPort, 2019 - 2018
- [j3]Seong Joong Kim
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits 53(3): 814-824 (2018) - 2017
- [c6]Pamela J. Tannous, Satya R. T. Peddada, James T. Allison, Thomas Foulkes, Robert C. N. Pilawa-Podgurski, Andrew G. Alleyne
Dynamic temperature estimation of power electronics systems. ACC 2017: 3463-3469 - [c5]Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC 2017: 1-4 - [c4]Wen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski:
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS. ISSCC 2017: 182-183 - 2016
- [c3]Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO 2016: 54:1-54:12 - 2015
- [j2]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits 50(12): 2814-2824 (2015) - [c2]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. ISSCC 2015: 1-3 - 2012
- [b1]Robert C. N. Pilawa-Podgurski:
Architectures and circuits for low-voltage energy conversion and applications in renewable energy and power management. Massachusetts Institute of Technology, Cambridge, MA, USA, 2012 - [j1]Robert C. N. Pilawa-Podgurski, David J. Perreault:
Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS. IEEE J. Solid State Circuits 47(7): 1557-1567 (2012) - 2011
- [c1]Robert C. N. Pilawa-Podgurski, David J. Perreault:
Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS. ESSCIRC 2011: 479-482
Coauthor Index
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