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Jean-Luc Nagel
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2010 – 2019
- 2019
- [c17]Marc Pons
, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS. CICC 2019: 1-4 - [c16]Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW. ISLPED 2019: 1-4 - [c15]Christoph Thomas Müller, Marc Pons
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC. PRIME 2019: 285-288 - 2017
- [c14]Pierre-François Rüedi, A. Bishof, Marcin K. Augustyniak, Pascal Persechini, Jean-Luc Nagel, Marc Pons
Ultra low power microelectronics for wearable and medical devices. DATE 2017: 1426-1431 - 2016
- [c13]Marc Pons
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation. ESSCIRC 2016: 41-44 - 2013
- [c12]Marc Pons
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation. PATMOS 2013: 9-15 - 2012
- [c11]Marc Pons
Maximum delay variation temperature-aware standard cell design. ICECS 2012: 296-299 - 2011
- [c10]Lingamneni Avinash, Christian C. Enz, Jean-Luc Nagel, Krishna V. Palem, Christian Piguet:
Energy parsimonious circuit design through probabilistic pruning. DATE 2011: 764-769 - 2010
- [j4]Luca Benini
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits. J. Low Power Electron. 6(1): 44-55 (2010)
2000 – 2009
- 2009
- [j3]Claude Arm, Steve Gyger, Jean-Marc Masgonty, Marc-Nicolas Morgan, Jean-Luc Nagel, Christian Piguet, Flavio Rampogna, Patrick Volet:
Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core. IEEE J. Solid State Circuits 44(7): 2055-2064 (2009) - [c9]Pierre-François Rüedi, Pascal Heim, Steve Gyger, François Kaess, Claude Arm, Ricardo Caseiro, Jean-Luc Nagel, Silvio Todeschini:
An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications. ISSCC 2009: 46-47 - 2008
- [j2]Christian Piguet, Jean-Luc Nagel, Vincent Peiris, Steve Gyger, Daniel Séverac, Marc-Nicolas Morgan, Jean-Marc Masgonty:
Low-Power Heterogeneous Systems-on-Chips. J. Low Power Electron. 4(2): 111-126 (2008) - [c8]Claude Arm, Steve Gyger, Jean-Marc Masgonty, Marc Morgan, Jean-Luc Nagel, Christian Piguet, Flavio Rampogna, Patrick Volet:
Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core. ESSCIRC 2008: 190-193 - 2006
- [c7]Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine:
Architectural and technology influence on the optimal total power consumption. DATE 2006: 989-994 - [c6]Christian Piguet, Christian Schuster, Jean-Luc Nagel:
Static and Dynamic Power Reduction by Architecture Selection. PATMOS 2006: 659-668 - 2005
- [j1]Christian Schuster, Christian Piguet, Jean-Luc Nagel, Pierre-André Farine:
An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth. J. Low Power Electron. 1(1): 3-10 (2005) - 2004
- [c5]Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine:
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures. PATMOS 2004: 169-178 - 2003
- [c4]Erian Bezhani, Dequn Sun, Jean-Luc Nagel, Sergio Carrato:
Optimized filterbank fingerprint recognition. Image Processing: Algorithms and Systems 2003: 399-406 - 2002
- [c3]Jean-Luc Nagel, Patrick Stadelmann, Michael Ansorge, Fausto Pellandini:
A low-power VLSI architecture for face verification using elastic graph matching. EUSIPCO 2002: 1-4 - [c2]Patrick Stadelmann, Jean-Luc Nagel, Michael Ansorge, Fausto Pellandini:
A multiscale morphological coprocessor for low-power face authentication. EUSIPCO 2002: 1-4 - 2000
- [c1]Roberto Costantini, Javier Bracamonte, G. Ramponi, Jean-Luc Nagel, Michael Ansorge, Fausto Pellandini:
A low-complexity video coder based on the Discrete Walsh Hadamard Transform. EUSIPCO 2000: 1-4
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