UC3844B, UC3845B,

UC2844B, UC2845B

High Performance
Current Mode Controllers
The UC3844B, UC3845B series are high performance fixed
frequency current mode controllers. They are specifically designed for http://onsemi.com
Off−Line and dc−dc converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated PDIP−8
reference, high gain error amplifier, current sensing comparator, and a N SUFFIX
high current totem pole output ideally suited for driving a power CASE 626
8
MOSFET.
1
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, a latch for single pulse metering, and a flip−flop SOIC−8
which blanks the output off every other oscillator cycle, allowing 8 D1 SUFFIX
CASE 751
output deadtimes to be programmed from 50% to 70%. 1
These devices are available in an 8−pin dual−in−line and surface
mount (SOIC−8) plastic package as well as the 14−pin plastic surface
mount (SOIC−14). The SOIC−14 package has separate power and SOIC−14
ground pins for the totem pole output stage. 14 D SUFFIX
The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off), CASE 751A
1
ideally suited for off−line converters. The UCX845B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off). PIN CONNECTIONS
Features Compensation 1 8 Vref
• Pb−Free Packages are Available Voltage Feedback 2 7 VCC

• Trimmed Oscillator for Precise Frequency Control Current Sense 3 6 Output

RT/CT 4 5 GN
• Oscillator Frequency Guaranteed at 250 kHz D
(Top View)
• Current Mode Operation to 500 kHz Output Switching Frequency
• Output Deadtime Adjustable from 50% to 70% Compensation 1 14 Vref
• Automatic Feed Forward Compensation NC 2 13 NC
Voltage Feedback VCC
•
3 12
Latching PWM for Cycle−By−Cycle Current Limiting NC 4 11 VC
• Internally Trimmed Reference with Undervoltage Lockout Current Sense 5 10 Output
• High Current Totem Pole Output NC 6 9 GND

• RT/CT Power Ground

7 8
Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current (Top View)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 16 of this data sheet.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

September, 2004 − Rev. 3 UC3844B/D
 UC3844B, UC3845B, UC2844B, UC2845B
VCC 7(12)

VCC
Vref 5.0V Undervoltage
Reference Lockout
8(14) R
Vref
R Undervoltage VC
Lockout
7(11)

RT/CT Oscillator Output

4(7) Latching 6(10)
PWM
Power
Voltage
Ground
Feedback
Input 5(8)
2(3) Error
Output/ Amplifier Current
Compensation Sense Input
1(1) 3(5)

GND 5(9)

Pin numbers in parenthesis are for the D suffix SOIC−14 package.

Figure 1. Simplified Block Diagram

ORDERING INFORMATION
Operating
Device Temperature Range Package Shipping†
UC384xBD SOIC−14 55 Units/Rail
UC384xBDR2 SOIC−14 2500 Tape & Reel
UC3844BDR2G SOIC−14 2500 Tape & Reel
(Pb−Free)

UC384xBD1 SOIC−8 98 Units/Rail

UC3844BD1G SOIC−8 98 Units/Rail
TA = 0° to +70°C (Pb−Free)

UC384xBD1R2 SOIC−8 2500 Tape & Reel

UC384xBD1R2G SOIC−8
2500 Tape & Reel
(Pb−Free)

UC384xBN PDIP−8 50 Units/Rail

UC384xBNG PDIP−8 50 Units/Rail
(Pb−Free)

UC2845BD SOIC−14 55 Units/Rail

UC284xBDR2 SOIC−14 2500 Tape & Reel
UC2845BDR2G SOIC−14 2500 Tape & Reel
(Pb−Free)

UC2845BD1 TA = −25° to +85°C SOIC−8 98 Units/Rail

UC284xBD1R2 SOIC−8 2500 Tape & Reel
UC284xBD1R2G SOIC−8 2500 Tape & Reel
(Pb−Free)

UC2844BN PDIP−8 50 Units/Rail

UC384xBVD SOIC−14 55 Units/Rail
UC3844BVDR2 SOIC−14 2500 Tape & Reel
UC384xBVD1 TA = −40° to +105°C SOIC−8 98 Units/Rail
UC384xBVD1R2 SOIC−8 2500 Tape & Reel
UC384xBVN PDIP−8 50 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
x indicates either a 4 or 5 to define specific device part numbers.

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 UC3844B, UC3845B, UC2844B, UC2845B

MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink (Note 1) IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 J
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C PD 862 mW
Thermal Resistance, Junction−to−Air RJA 145 °C/W
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C PD 702 mW
Thermal Resistance, Junction−to−Air RJA 178 °C/W
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C PD 1.25 W
Thermal Resistance, Junction−to−Air RJA 100 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature TA °C
UC3844B, UC3845B 0 to + 70
UC2844B, UC2845B − 25 to + 85
Storage Temperature Range Tstg − 65 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum package power dissipation limits must be observed.

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV
Temperature Stability TS − 0.2 − − 0.2 − mV/°C
Total Output Variation over Line, Load, and Temperature Vref 4.9 − 5.1 4.82 − 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − V
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA
OSCILLATOR SECTION
Frequency fOSC kHz
TJ = 25°C 49 52 55 49 52 55
TA = Tlow to Thigh 48 − 56 48 − 56
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) 225 250 275 225 250 275
Frequency Change with Voltage (VCC = 12 V to 25 V)
fOSC/
V − 0.2 1.0 − 0.2 1.0 %
Frequency Change with Temperature (TA = Tlow to Thigh)
fOSC/
T − 1.0 − − 0.5 − %
Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V
Discharge Current (VOSC = 2.0 V) Idischg mA
TJ = 25°C 7.8 8.3 8.8 7.8 8.3 8.8
TA = Tlow to Thigh (UC284XB, UC384XB) 7.5 − 8.8 7.6 − 8.8
TA = Tlow to Thigh (UC384XBV) − − − 7.2 − 8.8
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV

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 UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 4], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 5], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V
Input Bias Current (VFB = 5.0 V) IIB − − 0.1 −1.0 − − 0.1 − 2.0 A
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 − 65 90 − dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 − 0.7 1.0 − MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 − 60 70 − dB
Output Current mA
Sink (VO = 1.1 V, VFB = 2.7 V) ISink 2.0 12 − 2.0 12 −
Source (VO = 5.0 V, VFB = 2.3 V) ISource − 0.5 −1.0 − − 0.5 −1.0 −
Output Voltage Swing V
High State (RL = 15 k to ground, VFB = 2.3 V) VOH 5.0 6.2 − 5.0 6.2 −
Low State (RL = 15 k to Vref, VFB = 2.7 V) VOL
(UC284XB, UC384XB) − 0.8 1.1 − 0.8 1.1
(UC384XBV) − − − − 0.8 1.2

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 6 & 7) AV V/V
(UC284XB, UC384XB) 2.85 3.0 3.15 2.85 3.0 3.15
(UC384XBV) − − − 2.85 3.0 3.25
Maximum Current Sense Input Threshold (Note 6) Vth V
(UC284XB, UC384XB) 0.9 1.0 1.1 0.9 1.0 1.1
(UC384XBV) − − − 0.85 1.0 1.1
Power Supply Rejection Ratio PSRR − 70 − − 70 − dB
(VCC = 12 V to 25 V) (Note 6)
Input Bias Current IIB − − 2.0 −10 − − 2.0 −10 A
Propagation Delay (Current Sense Input to Output) tPLH(In/Out) − 150 300 − 150 300 ns
OUTPUT SECTION
Output Voltage V
Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4
(ISink = 200 mA, UC284XB, UC384XB) − 1.6 2.2 − 1.6 2.2
(ISink = 200 mA, UC384XBV) − − − − 1.6 2.3
High State (ISource = 20 mA, UC284XB, UC384XB) VOH 13 13.5 − 13 13.5 −
(ISource = 20 mA, UC384XBV) − − − 12.9 − −
(ISource = 200 mA) 12 13.4 − 12 13.4 −
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold Vth V
UCX844B, BV 15 16 17 14.5 16 17.5
UCX845B, BV 7.8 8.4 9.0 7.8 8.4 9.0
Minimum Operating Voltage After Turn−On VCC(min) V
UCX844B, BV 9.0 10 11 8.5 10 11.5
UCX845B, BV 7.0 7.6 8.2 7.0 7.6 8.2
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV
6. This parameter is measured at the latch trip point with VFB = 0 V.
7. Comparator gain is defined as: AV =
V Output/Compensation

V Current Sense Input

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 UC3844B, UC3845B, UC2844B, UC2845B

ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 8], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 9], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristic Symbol Min Typ Max Min Typ Max Unit
PWM SECTION
Duty Cycle %
Maximum (UC284XB, UC384XB) DC(max) 47 48 50 47 48 50
Maximum (UC384XBV) − − − 46 48 50
Minimum DC(min) − − 0 − − 0

TOTAL DEVICE
Power Supply Current ICC mA
Startup (VCC = 6.5 V for UCX845B, − 0.3 0.5 − 0.3 0.5
Startup (VCC = 14 V for UCX844B, BV)
Operating (Note 8) − 12 17 − 12 17
Power Supply Zener Voltage (ICC = 25 mA) VZ 30 36 − 30 36 − V
8. Adjust VCC above the Startup threshold before setting to 15 V.
9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B = + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV = +105°C for UC3844BV, UC3845BV

ÄÄÄÄÄ
ÄÄÄÄÄ
80 75
VCC = 15 V 1.CT = 10 nF 3

ÄÄÄÄÄ
% DT, PERCENT OUTPUT DEADTIME
50 TA = 25°C 2.CT = 5.0 nF
R T, TIMING RESISTOR (k Ω)

70

ÄÄÄÄÄ
3.CT = 2.0 nF
4.CT = 1.0 nF 2
20 4

ÄÄÄÄÄ
5.CT = 500 pF
65 6.CT = 200 pF 1
7.CT = 100 pF
8.0
5.0 60
7

2.0 55 5
NOTE: Output switches at
1/2 the oscillator frequency 6
0.8 50
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz)

Figure 2. Timing Resistor Figure 3. Output Deadtime

versus Oscillator Frequency versus Oscillator Frequency

VCC = 15 V VCC = 15 V
2.55 V AV = −1.0 AV = −1.0
3.0 V
TA = 25°C TA = 25°C
20 mV/DIV

200 mV/DIV

2.5 V 2.5 V

2.45 V 2.0 V

0.5 s/DIV 1.0 s/DIV

Figure 4. Error Amp Small Signal Figure 5. Error Amp Large Signal
Transient Response Transient Response

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 UC3844B, UC3845B, UC2844B, UC2845B

Vth , CURRENT SENSE INPUT THRESHOLD (V)

100 0 1.2
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
VCC = 15 V VCC = 15 V
VO = 2.0 V to 4.0 V 30 1.0

φ, EXCESS PHASE (DEGREES)

80
RL = 100 k
Gain TA = 25°C
60 60 0.8
TA = 25°C
40 90 0.6
Phase TA = 125°C
20 120 0.4
TA = −55°C
0 150 0.2

−20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 2.0 4.0 6.0 8.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (VO)

Figure 6. Error Amp Open Loop Gain and Figure 7. Current Sense Input Threshold
Phase versus Frequency versus Error Amp Output Voltage

ÄÄÄÄ
ISC , REFERENCE SHORT CIRCUIT CURRENT (mA)
∆ Vref , REFERENCE VOLTAGE CHANGE (mV)

0 110

ÄÄÄÄ
VCC = 15 V
VCC = 15 V
RL ≤ 0.1 
−4.0

−8.0 90

−12 TA = −
55°C
TA = 125°C
−16 70

−20
TA = 25°C
−24 50
0 20 40 60 80 100 120 −55 −25 0 25 50 75 100 125
Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)

Figure 8. Reference Voltage Change Figure 9. Reference Short Circuit Current

versus Source Current versus Temperature
∆V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

∆V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

VCC = 15 V VCC = 12 V to 25 V
IO = 1.0 mA to 20 mA TA = 25°C
TA = 25°C
O

2.0 ms/DIV 2.0 ms/DIV

Figure 10. Reference Load Regulation Figure 11. Reference Line Regulation

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 UC3844B, UC3845B, UC2844B, UC2845B

ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
0
Vsat , OUTPUT SATURATION VOLTAGE (V) Source Saturation

ÄÄÄÄÄ
ÄÄÄ ÄÄÄÄÄ
VCC VCC = 15 V
VCC = 15 V
−1.0 (Load to Ground) 80 s Pulsed Load
TA = 25°C CL = 1.0 nF

ÄÄÄÄ
120 Hz Rate 90
TA = 25°C
−2.0 %

ÄÄÄÄ
TA = −55°C

3.0
ÄÄÄÄ
ÄÄÄÄ ÄÄÄÄ
TA = −55°C

ÄÄÄÄÄÄÄÄÄ
2.0
TA = 25°C

ÄÄÄ
ÄÄÄÄÄ
10
1.0 Sink Saturation %
(Load to VCC) GND
0
0 200 400 600 800 50 ns/DIV
IO, OUTPUT LOAD CURRENT (mA)

Figure 12. Output Saturation Voltage Figure 13. Output Waveform

versus Load Current
V O , OUTPUT VOLTAGE

25
VCC = 30 V

ICC, SUPPLY CURRENT (mA)

CL = 15 pF

20 V/DIV
TA = 25°C 20

15

ÄÄÄÄ
ÄÄÄÄ
ICC, SUPPLY CURRENT

10
RT = 10 k

UCX845B

UCX844B
ÄÄÄÄ
CT = 3.3 nF
100 mA/DIV

5 VFB = 0 V

ÄÄÄÄ
ISense = 0 V
TA = 25°C
0
0 10 20 30 40
100 ns/DIV VCC, SUPPLY VOLTAGE (V)

Figure 14. Output Cross Conduction Figure 15. Supply Current versus Supply Voltage

PIN FUNCTION DESCRIPTION

Pin
8−Pin 14−Pin Function Description
1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation.
2 3 Voltage This is the inverting input of the Error Amplifier. It is normally connected to the switching power
Feedback supply output through a resistor divider.
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.
5 GND This pin is the combined control circuitry and power ground.
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin. The output switches at one−half the oscillator frequency.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor C T through resistor RT.
8 Power This pin is a separate power ground return that is connected back to the power source. It is used
Ground to reduce the effects of switching transient noise on the control circuitry.
11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source
connection, it can reduce the effects of switching transient noise on the control circuitry.
9 GND This pin is the control circuitry ground return and is connected back to the powersource ground.
2,4,6,13 NC No connection. These pins are not internally connected.

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 UC3844B, UC3845B, UC2844B, UC2845B

OPERATING DESCRIPTION

The UC3844B, UC3845B series are high performance, Comparator. This guarantees that no drive pulses appear at
fixed frequency, current mode controllers. They are the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
specifically designed for Off−Line and dc−dc converter This occurs when the power supply is operating and the load
applications offering the designer a cost−effective solution is removed, or at the beginning of a soft−start interval
with minimal external components. A representative block (Figures 21, 22). The Error Amp minimum feedback
diagram is shown in Figure 16. resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
Oscillator comparator’s 1.0 V clamp level:
The oscillator frequency is programmed by the values
3.0 (1.0 V) + 1.4 V
selected for the timing components RT and CT. Capacitor CT Rf(min) ≈ = 8800 
0.5 mA
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal Current Sense Comparator and PWM Latch
current sink. During the discharge of CT, the oscillator The UC3844B, UC3845B operate as a current mode
generates an internal blanking pulse that holds the center controller, whereby output switch conduction is initiated by
input of the NOR gate high. This causes the Output to be in the oscillator and terminated when the peak inductor current
a low state, thus producing a controlled amount of output reaches the threshold level established by the Error
deadtime. An internal flip−flop has been incorporated in the Amplifier Output/Compensation (Pin 1). Thus the error
UCX844/5B which blanks the output off every other clock signal controls the peak inductor current on a
cycle by holding one of the inputs of the NOR gate high. This cycle−by−cycle basis. The Current Sense Comparator PWM
in combination with the CT discharge period yields output Latch configuration used ensures that only a single pulse
deadtimes programmable from 50% to 70%. Figure 2 shows appears at the Output during any given oscillator cycle. The
RT versus Oscillator Frequency and Figure 3, Output inductor current is converted to a voltage by inserting the
Deadtime versus Frequency, both for given values of CT. ground−referenced sense resistor RS in series with the
Note that many values of RT and CT will give the same source of output switch Q1. This voltage is monitored by the
oscillator frequency but only one combination will yield a Current Sense Input (Pin 3) and compared to a level derived
specific output deadtime at a given frequency. The oscillator from the Error Amp Output. The peak inductor current under
thresholds are temperature compensated to within ±6% at normal operating conditions is controlled by the voltage at
50 kHz. Also, because of industry trends moving the Pin 1 where:
UC384X into higher and higher frequency applications, the
V(Pin 1) − 1.4 V
UC384XB is guaranteed to within ±10% at 250 kHz. Ipk =
In many noise−sensitive applications it may be desirable 3 RS
to frequency−lock the converter to an external system clock. Abnormal operating conditions occur when the power
This can be accomplished by applying a clock signal to the supply output is overloaded or if output voltage sensing is
circuit shown in Figure 18. For reliable locking, the lost. Under these conditions, the Current Sense Comparator
free−running oscillator frequency should be set about 10% threshold will be internally clamped to 1.0 V. Therefore the
less than the clock frequency. A method for multi−unit maximum peak switch current is:
synchronization is shown in Figure 19. By tailoring the 1.0 V
clock waveform, accurate Output duty cycle clamping can Ipk(max) =
RS
be achieved to realize output deadtimes of greater than 70%.
When designing a high power switching regulator it
Error Amplifier becomes desirable to reduce the internal clamp voltage in order
A fully compensated Error Amplifier with access to the to keep the power dissipation of RS to a reasonable level. A
inverting input and output is provided. It features a typical simple method to adjust this voltage is shown in Figure 20. The
dc voltage gain of 90 dB, and a unity gain bandwidth of two external diodes are used to compensate the internal diodes,
1.0 MHz with 57 degrees of phase margin (Figure 6). The yielding a constant clamp voltage over temperature. Erratic
non−inverting input is internally biased at 2.5 V and is not operation due to noise pickup can result if there is an excessive
pinned out. The converter output voltage is typically divided reduction of the Ipk(max) clamp voltage.
down and monitored by the inverting input. The maximum A narrow spike on the leading edge of the current
input bias current is −2.0 A which can cause an output waveform can usually be observed and may cause the power
voltage error that is equal to the product of the input bias supply to exhibit an instability when the output is lightly
current and the equivalent input divider source resistance. loaded. This spike is due to the power transformer
The Error Amp Output (Pin 1) is provided for external interwinding capacitance and output rectifier recovery time.
loop compensation (Figure 29). The output voltage is offset The addition of an RC filter on the Current Sense Input with
by two diode drops (≈1.4 V) and divided by three before it a time constant that approximates the spike duration will
connects to the inverting input of the Current Sense usually eliminate the instability (refer to Figure 24).

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 UC3844B, UC3845B, UC2844B, UC2845B

VCC Vin

VCC 7(12)

36V
Vref Reference
Regulator
8(14) VCC + (See
R Text)
Internal UVLO − VC
RT 2.5V Bias
R 7(11)
+
3.6V Vref
−
UVLO Output Q1
Oscillator
CT 4(7) 6(10)
+ 1.0mA
S
Power Ground
Voltage 2R Q
Feedback R PWM
5(8)
Input 2(3) R Latch
Error 1.0V Current Sense Input
Amplifier
Output/
Compensation 1(1) Current Sense 3(5)
Comparator RS

GND 5(9)

Pin numbers adjacent to terminals are for the 8−pin dual−in−line package. = Sink Only Positive True Logic
Pin numbers in parenthesis are for the D suffix SOIC−14 package.

Figure 16. Representative Block Diagram

Capacitor CT

Latch Set"
Input

Output/
Compensation

Current Sense
Input

Latch Reset"
Input

Output

Large RT/Small CT Small RT/Large CT

Figure 17. Timing Diagram

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 UC3844B, UC3845B, UC2844B, UC2845B

Undervoltage Lockout designer added flexibility in tailoring the drive voltage

Two undervoltage lockout comparators have been independent of VCC. A Zener clamp is typically connected
incorporated to guarantee that the IC is fully functional to this input when driving power MOSFETs in systems
before the output stage is enabled. The positive power where VCC is greater than 20 V. Figure 23 shows proper
supply terminal (VCC) and the reference output (Vref) are power and control ground connections in a current−sensing
each monitored by separate comparators. Each has built−in power MOSFET application.
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator Reference
upper and lower thresholds are 16 V/10 V for the UCX844B, The 5.0 V bandgap reference is trimmed to ±1.0%
and 8.4 V/7.6 V for the UCX845B. The Vref comparator tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
upper and lower thresholds are 3.6 V/3.4 V. The large UC384XB. Its primary purpose is to supply charging current
hysteresis and low startup current of the UCX844B makes to the oscillator timing capacitor. The reference has
it ideally suited in off−line converter applications where short−circuit protection and is capable of providing in
efficient bootstrap startup techniques are required excess of 20 mA for powering additional control system
(Figure 30). The UCX845B is intended for lower voltage circuitry.
dc−dc converter applications. A 36 V Zener is connected as
Design Considerations
a shunt regulator from VCC to ground. Its purpose is to Do not attempt to construct the converter on
protect the IC from excessive voltage that can occur during wire−wrap or plug−in prototype boards. High frequency
system startup. The minimum operating voltage for the circuit layout techniques are imperative to prevent
UCX844B is 11 V and 8.2 V for the UCX845B. pulse−width jitter. This is usually caused by excessive noise
Output pick−up imposed on the Current Sense or Voltage Feedback
These devices contain a single totem pole output stage that inputs. Noise immunity can be improved by lowering circuit
was specifically designed for direct drive of power impedances at these points. The printed circuit layout should
MOSFETs. It is capable of up to ±1.0 A peak drive current contain a ground plane with low−current signal and
and has a typical rise and fall time of 50 ns with a 1.0 nF load. high−current switch and output grounds returning on
Additional internal circuitry has been added to keep the separate paths back to the input filter capacitor. Ceramic
Output in a sinking mode whenever an undervoltage lockout bypass capacitors (0.1 F) connected directly to VCC, VC,
is active. This characteristic eliminates the need for an and Vref may be required depending upon circuit layout.
external pulldown resistor. This provides a low impedance path for filtering the high
The SOIC−14 surface mount package provides separate frequency noise. All high current loops should be kept as
pins for VC (output supply) and Power Ground. Proper short as possible using heavy copper runs to minimize
implementation will significantly reduce the level of radiated EMI. The Error Amp compensation circuitry and
switching transient noise imposed on the control circuitry. the converter output voltage divider should be located close
This becomes particularly useful when reducing the Ipk(max) to the IC and as far as possible from the power switch and
clamp level. The separate VC supply input allows the other noise−generating components.

Vref

8(14) R 8(14) R
Bias RA Bias
RT
R 8 4 R
RB
5.0k
6 3
Osc Osc
CT 4(7) R 4(7)
+ 5 +
5.0k Q
0.01 7
2R 2 S 2R

External 2(3) EA R 5.0k 2(3) EA R

47 C
Sync MC1455
Input
1
1(1) 1(1)

5(9) 5(9)
To Additional
UCX84XBs
The diode clamp is required if the Sync amplitude is large enough to cause 1.44 RA
f  D(max) 
the bottom side of CT to go more than 300 mV below ground. (RA
 2RB)C RA
 2RB

Figure 18. External Clock Synchronization Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization

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 UC3844B, UC3845B, UC2844B, UC2845B

VCC Vin

7(12)

5.0V Ref
8(14) R
5.0V Ref
8(14) Bias
R +
Bias − R
+
R 7(11) −
+
− Osc
Q1 4(7)
Osc + T
4(7) T 6(10) S
+ VClamp 1.0mA
R2 S 2(3) Q
1.0 mA R
Q 2R
EA R
2R R 5(8) 1.0M
2(3) EA R
Comp/Latch 1.0V
1.0V
1(1)
3(5) RS C
1(1)
R1 5(9)
5(9) tSoft−Start ≈ 3600C in F

VClamp ≈
1.67 R1R
1R2R2 Where: 0 ≤ VClamp ≤ 1.0 V
RR21
1 + 0.33x10
−3
V
Ipk(max)  Clamp
RS

Figure 20. Adjustable Reduction of Clamp Level Figure 21. Soft−Start Circuit

VCC Vin VCC Vin

RSIpkrDS(on)
(12) VPin5 
7(12) rDM(on)
 RS
If: SENSEFET = MTP10N10M
RS = 200
5.0V Ref 5.0V Ref
Then : VPin5  0.075Ipk
8(14) R + +
− −
Bias D SENSEFET
R 7(11) (11)
+ +
− − S
Q1 G
Osc K
4(7) T T (10)
+ 6(10) M
VClamp
S S
1.0 mA
Q Q
R R (8)
EA 2R 5(8)
2(3) R Comp/Latch
1.0V Comp/Latch
R2 Power Ground:
3(5) (5) RS To Input Source
1(1) RS 1/4 W Return
R1 MPSA63 5(9) Control Circuitry Ground:
To Pin (9)
1.67
VClamp ≈ Where: 0 ≤ VClamp ≤ 1.0 V
RR21
1 Virtually lossless current sensing can be achieved with the implementation
of a SENSEFET power switch. For proper operation during over−current
conditions, a reduction of the Ipk(max) clamp level must be implemented.
tSoft-Start   In 1  VC
3VClamp

C R1R2
R1
R2
 V
Ipk(max)  Clamp
RS
Refer to Figures 20 and 22.

Figure 22. Adjustable Buffered Reduction of Figure 23. Current Sensing Power MOSFET
Clamp Level with Soft−Start

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 UC3844B, UC3845B, UC2844B, UC2845B
VCC Vin

7(12)

5.0V Ref
+
−

7(11)
+ The addition of the RC filter will eliminate
−
Q1
instability caused by the leading edge spike
on the current waveform.
T 6(10)
S
5(8)
Q
R

Comp/Latch 3(5) R

C RS

Figure 24. Current Waveform Spike Suppression

VCC Vin
IB

7(12) + Vin

0
Base Charge
5.0V Ref
− Removal
+
−
C1
+ 7(11)
−
Rg Q1 Q1
6(10)
T 6(10)
S
Q 5(8)
R 5(8)
Comp/Latch
3(5) RS
3(5) RS

Series gate resistor Rg will damp any high frequency The totem pole output can furnish negative base current
parasitic oscillations caused by the MOSFET input for enhanced transistor turn−off, with the addition of
capacitance and any series wiring inductance in the capacitor C1.
gate−source circuit.

Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive

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 UC3844B, UC3845B, UC2844B, UC2845B

VCC Vin

7(12)
Isolation
Boundary

5.0V Ref
+
− VGS Waveforms

+ 7(11) + +
Q1
− 0
0
− −
T 6(10) 50% DC 25% DC

NNSp
5(8)
Q V(Pin1) − 1.4
R Ipk =
3(5) R
3 RS
Comp/Latch

C RS NS
NP

Figure 27. Isolated MOSFET Drive

8(14) R
Bias
R

Osc
4(7)
+
1.0 mA
2R

2(3) R
EA

1(1)
MCR 2N
101 3905 5(9)

2N
3903

The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The
simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.

Figure 28. Latched Shutdown

From VO 2.5V From VO 2.5V

+ +
1.0mA 1.0mA 2R
Ri 2R Rp
2(3) Ri 2(3)
R R
Rd Cf Rf EA Cp Rd Cf Rf EA

1(1) 1(1)
Rf ≥ 8.8k 5(9) 5(9)

Error Amp compensation circuit for stabilizing any current mode topology except Error Amp compensation circuit for stabilizing current mode boost
for boost and flyback converters operating with continuous inductor current. and flyback topologies operating with continuous inductor current.

Figure 29. Error Amplifier Compensation

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 UC3844B, UC3845B, UC2844B, UC2845B

L1
MBR1635
4.7 + T1 5.0V/4.0A
MDA 250 4.7k 3300 + +
2200 1000
202 pF
56k
115 Vac 5.0V RTN
MUR110
1N4935 1N4935 12V/0.3A
+ L2 +
7(12) + 68 +
1000 10

100 47 ±12V RTN

5.0V Ref 1000 10

0.01 8(14) + 1N4937 + +
R − −12V/0.3A
Bias MUR110
33k L3
R 7(11)
+ 680pF 2.7k
− 1N4937
22
Osc
1.0nF 4(7) T 6(10) MTP
+ 1N5819 4N50
18k S
2(3) Q
R 5(8)
100 EA
150k Comp/Latch 1.0k
4.7k pF
3(5)
1(1) 0.5
470pF
5(9)

T1 − Primary: 45 Turns #26 AWG L1 − 15 H at 5.0 A, Coilcraft Z7156

Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound L2, L3 − 25 H at 5.0 A, Coilcraft Z7157
Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound
Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35−3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance of 1.0 mH

Figure 30. 7 W Off−Line Flyback Regulator

Test Conditions Results

Line Regulation: 5.0 V Vin = 95 Vac to 130 Vac
= 50 mV or ±0.5%
±12 V
= 24 mV or ±0.1%

Load Regulation: 5.0 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A
= 300 mV or ±3.0%
±12 V Vin = 115 Vac, Iout = 100 mA to 300 mA
= 60 mV or ±0.25%

Output Ripple: 5.0 V Vin = 115 Vac 40 mVpp

±12 V 80 mVpp

Efficiency Vin = 115 Vac 70%

All outputs are at nominal load currents unless otherwise noted.

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 UC3844B, UC3845B, UC2844B, UC2845B

Output Load Regulation

Vin = 15V
(Open Loop Configuration)
UC3845B 7(12) IO (mA) VO (V)
+
47
34V 0 29.9
Reference 2 28.8
Regulator 9 28.3
8(14) R VCC +
2.5V 7(11) 1N5819 18 27.4
10k Internal UVLO −
Bias 36 24.4
R
3.6V + Vref
− 15 10
UVLO 6(10) 1N5819
Osc VO ≈ 2 (Vin)
1.0nF 4(7) + T +
Connect to
+
0.5mA S 47
2R 5(8) Pin 2 for R2
2(3) Q
R closed loop
PWM operation.
Error R 1.0V Latch 3(5)
Amplifier

1(1) Current Sense

R1
Comparator
5(9) VO = 2.5 R2
R1

1

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent line
and load regulation by connecting the R2/R1 resistor divider as shown.

Figure 31. Step−Up Charge Pump Converter

Vin = 15V Output Load Regulation

UC3845B 7(12)
+ IO (mA) VO (V)
47
34V 0 −14.4
Reference 2 −13.2
Regulator
8(14) R VCC + 9 −12.5
2.5V − 7(11) 18 −11.7
10k Internal UVLO
Bias 32 −10.6
R
3.6V + Vref
− 15 10
UVLO 6(10) 1N5819
Osc VO ≈ −Vin
1.0nF 4(7) + T
1N5819 +
S 47
0.5mA 5(8)
2R
2(3) Q
R PWM
Error R 1.0V Latch 3(5)
Amplifier

1(1) Current Sense

Comparator
5(9)

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.

Figure 32. Voltage−Inverting Charge Pump Converter

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 UC3844B, UC3845B, UC2844B, UC2845B

MARKING DIAGRAMS

PDIP−8
N SUFFIX
CASE 626
8 8 8 8

UC384xBN UC3844BVN UC3845BVN UC2844BN

AWL AWL FAWL FAWL
YYWW YYWW YYWW YYWW

1 1 1 1

SOIC−8
D1 SUFFIX
CASE 751

8 8 8

384xB 384xB 284xB

ALYW ALYWV ALYW

1 1 1

SOIC−14
D SUFFIX
CASE 751A
14 14 14

UC384xBD UC384xBVD UC284xBD

AWLYWW AWLYWW AWLYWW

1 1 1

x = 4 or 5
F = Wafer Fab
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week

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 UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

PDIP−8
N SUFFIX
CASE 626−05
ISSUE L

NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8 5 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
−B− Y14.5M, 1982.

1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
F C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
NOTE 2 −A− F 1.02 1.78 0.040 0.070
L G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
C L 7.62 BSC 0.300 BSC
M −−− 10
−−− 10

J N 0.76 1.01 0.030 0.040
−T−
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M

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 UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AC

−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0
8
0
8

0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 inches

mm 

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 UC3844B, UC3845B, UC2844B, UC2845B

PACKAGE DIMENSIONS

SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G

−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
14 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−B− 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
P 7 PL PER SIDE.
0.25 (0.010) M B M 5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
1 7 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
G R X 45
F CONDITION.
C
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
−T− B 3.80 4.00 0.150 0.157
K M J C 1.35 1.75 0.054 0.068
SEATING D 14 PL D 0.35 0.49 0.014 0.019
PLANE
0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0
7
0
7

P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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 UC3844B, UC3845B, UC2844B, UC2845B

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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20