Pulse Width Modulator Control Circuits: Semiconductor Technical Data
Pulse Width Modulator Control Circuits: Semiconductor Technical Data
Pulse Width Modulator Control Circuits: Semiconductor Technical Data
PULSE WIDTH MODULATOR
The SG3525A, SG3527A pulse width modulator control circuits offer
improved performance and lower external parts count when implemented for CONTROL CIRCUITS
controlling all types of switching power supplies. The on–chip +5.1 V
reference is trimmed to ±1% and the error amplifier has an input
SEMICONDUCTOR
common–mode voltage range that includes the reference voltage, thus
eliminating the need for external divider resistors. A sync input to the TECHNICAL DATA
oscillator enables multiple units to be slaved or a single unit to be
synchronized to an external system clock. A wide range of deadtime can be
programmed by a single resistor connected between the CT and Discharge
pins. These devices also feature built–in soft–start circuitry, requiring only an
external timing capacitor. A shutdown pin controls both the soft–start circuitry
and the output stages, providing instantaneous turn off through the PWM N SUFFIX
latch with pulsed shutdown, as well as soft–start recycle with longer PLASTIC PACKAGE
shutdown commands. The under voltage lockout inhibits the outputs and the
16 CASE648
1
changing of the soft–start capacitor when VCC is below nominal. The output
stages are totem–pole design capable of sinking and sourcing in excess of
200 mA. The output stage of the SG3525A features NOR logic resulting in a
low output for an off–state while the SG3527A utilized OR logic which gives a
high output when off. DW SUFFIX
• 8.0 V to 35 V Operation PLASTIC PACKAGE
CASE 751B
•
16
5.1 V ± 1.0% Trimmed Reference 1 (SO–16L)
• 100 Hz to 400 kHz Oscillator Range
• Separate Oscillator Sync Pin
• Adjustable Deadtime Control
PIN CONNECTIONS
• Input Undervoltage Lockout
• Latching PWM to Prevent Multiple Pulses Inv. Input 1 16 Vref
• Pulse–by–Pulse Shutdown Noninv. Input 2 15 VCC
• Dual Source/Sink Outputs: ±400 mA Peak
Sync 3 14 Output B
16 VC CT 5 12 Ground
Vref To Internal 13
15 Circuitry
VCC
Reference Under– RT 6 11 Output A
Regulator Voltage Output A
12 Lockout
Ground 11 Discharge 7 10 Shutdown
NOR
4
OSC Output
Soft–Start 8 9 Compensation
3 Q
Sync
6 Oscillator F/F
RT Q NOR 14
5 (Top View)
Output B
CT
7
Discharge R
+ SG3525A Output Stage
9 S
Compensation – PWM Latch 13
1 – VC
INV. Input –
Error 50µA S Output A
2 Amp ORDERING INFORMATION
Noninv. Input + VREF OR 11
8
CSoft–Start Operating
10 5.0k
Output B Device Temperature Range Package
Shutdown 5.0k
OR 14 SG3525AN Plastic DIP
SG3527A SG3525ADW TA = 0° to +70°C SO–16L
Output Stage
SG3527AN Plastic DIP
APPLICATION INFORMATION
Shutdown Options (See Block diagram, front page) latch is immediately set providing the fastest turn–off signal to
Since both the compensation and soft–start terminals the outputs; and a 150 µA current sink begins to discharge
(Pins 9 and 8) have current source pull–ups, either can the external soft–start capacitor. If the shutdown command is
readily accept a pull–down signal which only has to sink a short, the PWM signal is terminated without significant
maximum of 100 µA to turn off the outputs. This is subject to discharge of the soft–start capacitor, thus, allowing, for
the added requirement of discharging whatever external example, a convenient implementation of pulse–by–pulse
capacitance may be attached to these pins. current limiting. Holding Pin 10 high for a longer duration,
An alternate approach is the use of the shutdown circuitry however, will ultimately discharge this external capacitor,
of Pin 10 which has been improved to enhance the available recycling slow turn–on upon release.
shutdown options. Activating this circuit by applying a Pin 10 should not be left floating as noise pickup could
positive signal on Pin 10 performs two functions: the PWM conceivably interrupt normal operation.
ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc
Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline – 10 20 mV
Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload – 20 50 mV
Temperature Stability ∆Vref/∆T – 20 – mV
Total Output Variation ∆Vref 4.95 – 5.25 Vdc
Includes Line and Load Regulation over Temperature
Vref
16 15 VCC
Reference Regulator
Clock 0.1 0.1
4 Flip/ 13 VC
Flop
3.0k 0.1
Sync
3 O Out A
PWM
ADJ. s 11
RT c A
1.0k
6 i
l
Deadtime l
1.5k 1.0k, 1.0W
a
0.009 Ramp 7 (2)
t
100Ω 5 o
r
14
0.1 0.001 B
Out B
Comp
10k 9 12
PWM Gnd
1 = VIO
2 = 1(+) 0.01
3 = 1(–) 50µA 8 Softstart
1 1
+
2 2 1 5.0µF
– –
3 3 E/A 5.0k 10
2 5.0k Vref
V/I Meter +
1 1 2.0k
+ 2 2
3 3 DUT
Shutdown
Figure 1. Oscillator Charge Time versus RT Figure 2. Oscillator Discharge Time versus RD
200 500
50
300
* RD = 0 Ω
20
200
10
6 5 7
RD * 100
5.0
RT CT
2.0 0
2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200
CHARGE TIME (µs) DISCHARGE TIME (µs)
1 – 9
100 RZ 3.5
80 3.0
60 2.5
RZ = 20 k 2.0
40
1.5 Source Sat, (VC–VOH)
20
1.0
0 Sink Sat, (VOL)
0.5
–20 0
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0
f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A)
Vref 15
16 VCC
Q1 Q5 Q8
7.4k
Q3
RT Q3
6
CT Q6 Q9
5 Ramp Q4
Inverting
2.0k 14k To PWM Q1 Q2
Input
3 2.0k Q10 Q11 25k 1
Sync Blanking To PWM
5.0pF Noninverting
7 Q14 To Output Input Comparator
Discharge 400µA 2
Q4 5.8V 30
Q2 23k 200µA 100µA
Q7 1.0k Q12 Q13 250
12 1.0k 3.0k 9 Compensation
Gnd 4
OSC Output
11, 14
Vref Q8
Q11 Output
Q6
2.0k
Q1 Q2 Q3 Q6 Omitted
in SG3527A
For single–ended supplies, the driver outputs are grounded. In conventional push–pull bipolar designs, forward base drive is
The VC terminal is switched to ground by the totem–pole controlled by R1–R3. Rapid turn–of f times for the power
source transistors on alternate oscillator cycles. devices are achieved with speed–up capacitors C1 and C2.
+Vsupply +Vsupply
R1
Q1
T1 C1
13 Q1 T1
11 13 R1 T2
VC A 11
VC A
SG3525A SG3525A Q2
Q2 14
14
Gnd B Gnd B C2
12 R2
12
The low source impedance of the output drivers provides Low power transformers can be driven directly by the SG3525A.
rapid charging of power FET input capacitance while Automatic reset occurs during deadtime, when both ends of the
minimizing external components. primary winding are switched to ground.
DW SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SO–16L)
–A– ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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*SG3525A/D*
8 ◊ SG3525A/D
MOTOROLA ANALOG IC DEVICE DATA