UC3842B, UC3843B, UC2842B, UC2843B High Performance Current Mode Controllers
UC3842B, UC3843B, UC2842B, UC2843B High Performance Current Mode Controllers
UC3842B, UC3843B, UC2842B, UC2843B High Performance Current Mode Controllers
UC2842B, UC2843B
High Performance
Current Mode Controllers
The UC3842B, UC3843B series are high performance fixed
frequency current mode controllers. They are specifically designed for
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Off−Line and DC−DC converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error PDIP−8
N SUFFIX
amplifier, current sensing comparator, and a high current totem pole CASE 626
output ideally suited for driving a power MOSFET. 8
Also included are protective features consisting of input and 1
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering. SOIC−14
14 D SUFFIX
These devices are available in an 8−pin dual−in−line and surface CASE 751A
mount (SOIC−8) plastic package as well as the 14−pin plastic surface 1
mount (SOIC−14). The SOIC−14 package has separate power and
ground pins for the totem pole output stage.
The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), SOIC−8
8 D1 SUFFIX
ideally suited for off−line converters. The UCX843B is tailored for
CASE 751
lower voltage applications having UVLO thresholds of 8.5 V (on) and 1
7.6 V (off).
Features
• Trimmed Oscillator for Precise Frequency Control PIN CONNECTIONS
• Oscillator Frequency Guaranteed at 250 kHz
• Compensation Vref
1 8
Current Mode Operation to 500 kHz
Voltage Feedback 2 7 VCC
• Automatic Feed Forward Compensation Current Sense 3 6 Output
• Latching PWM for Cycle−By−Cycle Current Limiting RT/CT 4 5 GND
• Internally Trimmed Reference with Undervoltage Lockout (Top View)
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis Compensation 1 14 Vref
• Low Startup and Operating Current NC 2 13 NC
MAXIMUM RATINGS
Rating Symbol Value Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec) VCC, VC 30 V
Total Power Supply and Zener Current (ICC + IZ) 30 mA
Output Current, Source or Sink IO 1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 mJ
Current Sense and Voltage Feedback Inputs Vin − 0.3 to + 5.5 V
Error Amp Output Sink Current IO 10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C PD 862 mW
Thermal Resistance, Junction−to−Air RqJA 145 °C/W
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C PD 702 mW
Thermal Resistance, Junction−to−Air RqJA 178 °C/W
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C PD 1.25 W
Thermal Resistance, Junction−to−Air RqJA 100 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature TA °C
UC3842B, UC3843B 0 to 70
UC2842B, UC2843B − 25 to + 85
UC3842BV, UC3843BV −40 to +105
Storage Temperature Range Tstg − 65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 4000 V per JEDEC Standard JESD22-A114B
Machine Model Method 200 V per JEDEC Standard JESD22-A115-A
2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78
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UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 3], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 4], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline − 2.0 20 − 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload − 3.0 25 − 3.0 25 mV
Temperature Stability TS − 0.2 − − 0.2 − mV/°C
Total Output Variation over Line, Load, and Temperature Vref 4.9 − 5.1 4.82 − 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn − 50 − − 50 − mV
Long Term Stability (TA = 125°C for 1000 Hours) S − 5.0 − − 5.0 − mV
Output Short Circuit Current ISC − 30 − 85 −180 − 30 − 85 −180 mA
OSCILLATOR SECTION
Frequency fOSC kHz
TJ = 25°C 49 52 55 49 52 55
TA = Tlow to Thigh 48 − 56 48 − 56
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) 225 250 275 225 250 275
Frequency Change with Voltage (VCC = 12 V to 25 V) DfOSC/DV − 0.2 1.0 − 0.2 1.0 %
Frequency Change with Temperature, TA = Tlow to Thigh DfOSC/DT − 1.0 − − 0.5 − %
Oscillator Voltage Swing (Peak−to−Peak) VOSC − 1.6 − − 1.6 − V
Discharge Current (VOSC = 2.0 V) Idischg mA
TJ = 25°C, TA = Tlow to Thigh 7.8 8.3 8.8 7.8 8.3 8.8
UC284XB, UC384XB 7.5 − 8.8 7.6 − 8.8
TA = Tlow to Thigh UC384XBV − − − 7.2 − 8.8
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UC3842B, UC3843B, UC2842B, UC2843B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 7], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 8], unless otherwise noted.)
UC284XB UC384XB, XBV
Characteristics Symbol Min Typ Max Min Typ Max Unit
OUTPUT SECTION
Output Voltage V
Low State (ISink = 20 mA) VOL − 0.1 0.4 − 0.1 0.4
(ISink = 200 mA) UC284XB, UC384XB − 1.6 2.2 − 1.6 2.2
UC384XBV − − − − 1.6 2.3
High State (ISource = 20 mA) UC284XB, UC384XB VOH 13 13.5 − 13 13.5 −
UC384XBV − − − 12.9 13.5 −
12 13.4 − 12 13.4 −
(ISource = 200 mA)
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) VOL(UVLO) − 0.1 1.1 − 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr − 50 150 − 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf − 50 150 − 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC) Vth V
UCX842B, BV 15 16 17 14.5 16 17.5
UCX843B, BV 7.8 8.4 9.0 7.8 8.4 9.0
PWM SECTION
Duty Cycle %
Maximum UC284XB, UC384XB DC(max) 94 96 − 94 96 −
Maximum UC384XBV − − − 93 96 −
Minimum DC(min) − − 0 − − 0
TOTAL DEVICE
Power Supply Current ICC + IC mA
Startup (VCC = 6.5 V for UCX843B, − 0.3 0.5 − 0.3 0.5
Startup VCC 14 V for UCX842B, BV)
(Note 7) − 12 17 − 12 17
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UC3842B, UC3843B, UC2842B, UC2843B
80 100
50 1. CT = 10 nF 4
3. CT = 2.0 nF 3
4. CT = 1.0 nF 2
20
20 5. CT = 500 pF
6. CT = 200 pF 1
8.0 10 7. CT = 100 pF 7
6
5.0 5
5.0
2.0 VCC = 15 V
TA = 25°C 2.0 VCC = 15 V
TA = 25°C
0.8 1.0
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M 10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz)
VOSC = 2.0 V 90
8.5
80
Idischg = 8.54 mA
8.0 70
60
VCC = 15 V
7.5 CT = 3.3 nF
50 TA = 25°C
7.0 40
-55 -25 0 25 50 75 100 125 0.8 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
TA, AMBIENT TEMPERATURE (°C) RT, TIMING RESISTOR (kW)
Figure 4. Oscillator Discharge Current Figure 5. Maximum Output Duty Cycle
versus Temperature versus Timing Resistor
20 mV/DIV
2.50 V
2.5 V
2.45 V
2.0 V
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UC3842B, UC3843B, UC2842B, UC2843B
40 90 0.6
Phase TA = 125°C
20 120 0.4 TA = -55°C
0 150 0.2
-20 180 0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 0 2.0 4.0 6.0 8.0
f, FREQUENCY (Hz) VO, ERROR AMP OUTPUT VOLTAGE (V)
Figure 8. Error Amp Open Loop Gain and Figure 9. Current Sense Input Threshold
Phase versus Frequency versus Error Amp Output Voltage
ÄÄÄ
I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)
ÄÄÄÄ ÄÄÄ
Δ Vref , REFERENCE VOLTAGE CHANGE (mV)
0 110
VCC = 15 V
VCC = 15 V
RL ≤ 0.1 W
-4.0
ÄÄÄ
-8.0 90
-12
ÄÄÄÄ
TA = 125°C ÄÄÄ
TA = -55°C
ÄÄÄÄ
-16 70
ÄÄÄÄ
-20 TA = 25°C
-24 50
0 20 40 60 80 100 120 -55 -25 0 25 50 75 100 125
Iref, REFERENCE SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change Figure 11. Reference Short Circuit Current
versus Source Current versus Temperature
Δ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
VCC = 15 V VCC = 12 V to 25
IO = 1.0 mA to 20 mA TA = 25°C
TA = 25°C
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UC3842B, UC3843B, UC2842B, UC2843B
ÄÄÄÄÄÄÄÄÄÄ
ÄÄÄÄÄÄÄÄÄÄÄÄÄÄ
ÄÄÄ
0
Vsat, OUTPUT SATURATION VOLTAGE (V) Source Saturation VCC = 15 V
ÄÄÄÄ ÄÄÄÄÄ
VCC (Load to Ground) 80 ms Pulsed Load
-1.0 TA = 25°C 120 Hz Rate VCC = 15 V
ÄÄÄÄ
90% CL = 1.0 nF
-2.0
ÄÄÄÄ
TA = 25°C
TA = -55°C
ÄÄÄ
ÄÄÄ ÄÄÄ
3.0
TA = -55°C
ÄÄÄÄ ÄÄÄ
2.0
TA = 25°C
1.0
0
0
ÄÄÄÄ ÄÄ200
Sink Saturation
(Load to VCC)
400
GND
600 800
10%
25
VCC = 30 V
ÄÄÄÄ
ÄÄÄÄ
10
I CC , SUPPLY CURRENT
RT = 10 k
UCX843B
ÄÄÄÄ
UCX842B
CT = 3.3 nF
100 mA/DIV
ÄÄÄÄ
5 VFB = 0 V
ISense = 0 V
TA = 25°C
0
0 10 20 30 40
100 ns/DIV VCC, SUPPLY VOLTAGE (V)
Figure 16. Output Cross Conduction Figure 17. Supply Current versus Supply Voltage
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UC3842B, UC3843B, UC2842B, UC2843B
OPERATING DESCRIPTION
RTńCT(valley)
*V
ref
ref
Ǔ
solution with minimal external components. A
(eq. 4)
representative block diagram is shown in Figure 19.
Clearly, the maximum duty ratio is determined by the
Oscillator timing resistor RT. Therefore, RT is chosen such as to
The oscillator frequency is programmed by the values achieve a desired maximum duty ratio. Once RT has been
chosen for the timing components RT and CT. It must also be selected, CT can now be chosen to obtain the desired
noted that the value of RT uniquely determines the switching frequency as per Equation 5.
maximum duty ratio of UC384xx. The oscillator
f+ 1
configuration depicting the connection of the timing
components to the RT/CT pin of the controller is shown in R TC T ln ǒ V
V
RTńCT(valley)
RTńCT(peak)
*V
*V
ref
ref
@R
R I
T dischg
I
T dischg
)V
)V
RTńCT(peak)
*V
RTńCT(valley)
*V
ref
ref
Ǔ
Figure 18. Capacitor CT gets charged from the Vref source,
through resistor RT to its peak threshold VRT/CT(peak), (eq. 5)
typically 2.8 V. Upon reaching this peak threshold volage, an Figure 2 shows the frequency and maximum duty ratio
internal 8.3 mA current source, Idischg, is enabled and the variation versus RT for given values of CT. Care should be
voltage across CT begins to decrease. Once the voltage taken to ensure that the absolute minimum value of RT
across CT reaches its valley threshold, VRT/CT(valley), should not be less than 542 W. However, considering a 10%
typically 1.2 V, Idischg turns off. This allows capacitor CT to tolerance for the timing resistor, the nearest available
charge up again from Vref. This entire cycle repeats, and the standard resistor of 680 W is the absolute minimum that can
resulting waveform on the RT/CT pin has a sawtooth shape. be used to guarantee normal oscillator operation. If a timing
Typical waveforms are shown in Figure 20. resistor smaller than this value is used, then the charging
The oscillator thresholds are temperature compensated to current through the RT, CT path will exceed the pulldown
within ±6% at 50 kHz. Considering the general industry (discharge) current and the oscillator will get permanently
trend of operating switching controllers at higher locked/latched to an undefined state.
frequencies, the UC384xx is guaranteed to operate within In many noise-sensitive applications it may be desirable
±10% at 250 kHz. These internal circuit refinements to frequency-lock the converter to an external system clock.
minimize variations of oscillator frequency and maximum This can be accomplished by applying a clock signal to the
duty ratio. circuit shown in Figure 22. For reliable synchronization, the
The charging and discharging times of the timing free-running oscillator frequency should be set about 10%
capacitor CT are calculated using Equations 1 and 2. These less than the clock frequency. A method for multi-unit
equations do not take into account the propagation delays of synchronization is shown in Figure 23. By tailoring the
the internal comparator. Hence, at higher frequencies, the clock waveform, accurate Output duty ratio clamping can be
calculated value of the oscillator frequency differs from the achieved.
actual value.
Vref
ǒ Ǔ
RT/CT
R TI dischg ) V RTńCT(peak) * V ref
t RTńCT(dischg) + R TC T ln 1.2 V
R TI dischg ) V RTńCT(valley) * V ref
Idischg
(eq. 2) Enable CT
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UC3842B, UC3843B, UC2842B, UC2843B
Error Amplifier appears at the Output during any given oscillator cycle. The
A fully compensated Error Amplifier with access to the inductor current is converted to a voltage by inserting the
inverting input and output is provided. It features a typical ground−referenced sense resistor RS in series with the
DC voltage gain of 90 dB, and a unity gain bandwidth of source of output switch Q1. This voltage is monitored by the
1.0 MHz with 57 degrees of phase margin (Figure 8). The Current Sense Input (Pin 3) and compared to a level derived
non−inverting input is internally biased at 2.5 V and is not from the Error Amp Output. The peak inductor current under
pinned out. The converter output voltage is typically divided normal operating conditions is controlled by the voltage at
down and monitored by the inverting input. The maximum pin 1 where:
input bias current is −2.0 mA which can cause an output V(Pin 1) − 1.4 V
voltage error that is equal to the product of the input bias Ipk =
3 RS
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external Abnormal operating conditions occur when the power
loop compensation (Figure 33). The output voltage is offset supply output is overloaded or if output voltage sensing is
by two diode drops (≈1.4 V) and divided by three before it lost. Under these conditions, the Current Sense Comparator
connects to the non−inverting input of the Current Sense threshold will be internally clamped to 1.0 V. Therefore the
Comparator. This guarantees that no drive pulses appear at maximum peak switch current is:
the Output (Pin 6) when pin 1 is at its lowest state (VOL). 1.0 V
Ipk(max) =
This occurs when the power supply is operating and the load RS
is removed, or at the beginning of a soft−start interval When designing a high power switching regulator it
(Figures 25, 26). The Error Amp minimum feedback becomes desirable to reduce the internal clamp voltage in
resistance is limited by the amplifier’s source current order to keep the power dissipation of RS to a reasonable
(0.5 mA) and the required output voltage (VOH) to reach the level. A simple method to adjust this voltage is shown in
comparator’s 1.0 V clamp level: Figure 24. The two external diodes are used to compensate
3.0 (1.0 V) + 1.4 V the internal diodes, yielding a constant clamp voltage over
Rf(min) ≈ = 8800 W temperature. Erratic operation due to noise pickup can result
0.5 mA
if there is an excessive reduction of the Ipk(max) clamp
Current Sense Comparator and PWM Latch voltage.
The UC3842B, UC3843B operate as a current mode A narrow spike on the leading edge of the current
controller, whereby output switch conduction is initiated by waveform can usually be observed and may cause the power
the oscillator and terminated when the peak inductor current supply to exhibit an instability when the output is lightly
reaches the threshold level established by the Error loaded. This spike is due to the power transformer
Amplifier Output/Compensation (Pin 1). Thus the error interwinding capacitance and output rectifier recovery time.
signal controls the peak inductor current on a The addition of an RC filter on the Current Sense Input with
cycle−by−cycle basis. The Current Sense Comparator PWM a time constant that approximates the spike duration will
Latch configuration used ensures that only a single pulse usually eliminate the instability (refer to Figure 28).
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UC3842B, UC3843B, UC2842B, UC2843B
VCC Vin
VCC 7(12)
36V
Vref Reference
Regulator
8(14) VCC + (See
R Text) VC
Internal UVLO -
RT 2.5V Bias
R 7(11)
+
3.6V Vref
-
UVLO Output Q1
Oscillator
CT 4(7) 6(10)
+ 1.0mA
S
Power Ground
Voltage 2R Q
Feedback R PWM
5(8)
Input 2(3) R Latch
Error 1.0V Current Sense Input
Amplifier
Output/
Compensation 1(1) Current Sense 3(5)
Comparator RS
GND 5(9)
Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. = Sink Only Positive True Logic
Pin numbers in parenthesis are for the D suffix SOIC-14 package.
Capacitor CT
Latch
“Set" Input
Output/
Compensation
Current Sense
Input
Latch
“Reset" Input
Output
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UC3842B, UC3843B, UC2842B, UC2843B
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UC3842B, UC3843B, UC2842B, UC2843B
(A)
DI
Control Voltage
m1 m2
Inductor
Current Dl ) Dl m2
m1
Dl ) Dl m2 m2
Vref
m1 m1
8(14)
Oscillator Period R
Bias
RT
t0 t1 t2 t3 R
DI R
m1 47 2(3) EA
m2
Inductor
1(1)
Current
5(9)
Oscillator Period
The diode clamp is required if the Sync amplitude is large enough to cause the bottom
t4 t5 t6 side of CT to go more than 300 mV below ground.
Figure 21. Continuous Current Waveforms Figure 22. External Clock Synchronization
VCC Vin
7(12)
5.0V Ref
8(14) R +
8(14) Bias -
R
RA Bias R 7(11)
+
8 4 R -
Q1
RB
5.0k Osc
6 3 4(7) 6(10)
Osc + VClamp
R 4(7) R2 S
1.0 mA
5 + Q
5.0k Q
7 R
2 2R EA 2R 5(8)
S 2(3) R
1.0V Comp/Latch
5.0k 2(3) R
C MC1455 EA 3(5)
1(1) RS
1 R1 5(9)
1(1)
1.44 RB
UCX84XBs ǒ R2
R1
)1 Ǔ VClamp
f + D(max) + Ipk(max) [
(RA ) 2RB)C RA ) 2RB RS
Figure 23. External Duty Cycle Clamp and Figure 24. Adjustable Reduction of Clamp Level
Multi−Unit Synchronization
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UC3842B, UC3843B, UC2842B, UC2843B
VCC Vin
7(12)
5.0V Ref
8(14) R +
-
Bias
5.0V Ref R 7(11)
8(14) +
R -
Bias Q1
Osc
R 4(7) 6(10)
+ + VClamp
- 1.0 mA S
Q
Osc R
4(7) EA 2R 5(8)
2(3) R
+ Comp/Latch
R2 1.0V
1.0mA S
2(3) Q 3(5)
1(1) RS
2R R R1 5(9)
C MPSA63
EA R 1.0V
1.0M
1.67
VClamp [ Where: 0 ≤ VClamp ≤ 1.0 V
1(1) ǒRR21 ) 1Ǔ
C
tSoft-Start ≈ 3600C in mF
5(9) ƪ
tSoftStart + * In 1 *
VC
3VClamp
ƫC
R1R2
R1 ) R2
Ipk(max) [
VClamp
RS
VCC Vin
RS Ipk rDS(on)
(12) VPin 5 [ VCC Vin
rDM(on) ) RS
If: SENSEFET = MTP10N10M 7(12)
RS = 200
5.0V Ref
+ Then : VPin5 [ 0.075Ipk
- 5.0V Ref
D +
SENSEFET -
(11)
+
- S 7(11)
+
G
-
K Q1
(10)
M
S 6(10)
Q S
R 5(8)
(8) Q
Comp/Latch R
Power Ground: 3(5) R
Comp/Latch
(5) RS To Input Source
1/4 W Return
C RS
Control Circuitry Ground:
To Pin (9)
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over-current conditions, a The addition of the RC filter will eliminate instability caused by the leading
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 24 and 26. edge spike on the current waveform.
Figure 27. Current Sensing Power MOSFET Figure 28. Current Waveform Spike Suppression
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UC3842B, UC3843B, UC2842B, UC2843B
VCC Vin
IB
7(12) Vin
+
0
5.0V Ref
+ Base Charge
- - Removal
7(11)
+
- C1
Rg Q1
6(10) Q1
6(10)
S
Q
R 5(8)
5(8)
Comp/Latch
3(5) RS
3(5) RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in The totem pole output can furnish negative base current for enhanced
the gate-source circuit. transistor turn-off, with the addition of capacitor C1.
Figure 29. MOSFET Parasitic Oscillations Figure 30. Bipolar Transistor Drive
R
Q
5(8)
Ipk +
3RS
ǒ Ǔ
V(Pin1) * 1.4 NS
Np
MCR
101
2N
3905 5(9)
2N
Comp/Latch 3(5) R 3903
C RS NS
NP
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two
transistor circuit can be used in place of the SCR as shown. All resistors are 10 k.
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UC3842B, UC3843B, UC2842B, UC2843B
From VO 2.5V
+
Ri 1.0mA 2R
2(3)
EA R
Rd Cf Rf
1(1)
Rf ≥ 8.8 k
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback
converters operating with continuous inductor current.
From VO 2.5V
+
Rp 1.0mA 2R
Ri 2(3)
EA R
Cp Rd Cf Rf
1(1)
5(9)
Error Amp compensation circuit for stabilizing current mode boost and flyback
topologies operating with continuous inductor current.
VCC Vin
7(12)
36V
5.0V Ref
8(14) R +
-
RT Bias
MPS3904 R
+ 7(11)
-
RSlope Osc
From VO CT 4(7) + -m 6(10)
1.0mA S
Ri 2R
2(3) Q
R 5(8)
Cf EA R 1.0V
Rf Comp/Latch
Rd
1(1) m 3(5) RS
- 3.0m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage
feedback or current sense inputs to provide slope compensation.
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UC3842B, UC3843B, UC2842B, UC2843B
L1
MBR1635
4.7W + T1 5.0V/4.0A
MDA 250 4.7k 3300 + +
2200 1000
202 pF
115 Vac 56k
5.0V RTN
MUR110
1N4935 1N4935 12V/0.3A
+ L2 +
7(12) + 68 + 1000 10
100 47 ±12V RTN
1000 10
5.0V Ref 1N4937 + +
0.01 8(14) -12V/0.3A
R + MUR110
Bias
- 680pF L3
10k
R 7(11)
+
- 2.7k 1N4937
22
Osc
4700pF 4(7) + 6(10) MTP
1N5819 4N50
18k S L1 - 15 mH at 5.0 A, Coilcraft Z7156
2(3) Q L2, L3 - 25 mH at 5.0 A, Coilcraft Z7157
R 5(8)
100 EA
150k 1.0k
4.7k pF Comp/Latch
T1 - Primary: 45 Turns #26 AWG
1(1) 3(5) 0.5 Secondary ±12 V: 9 Turns #30 AWG
470pF (2 Strands) Bifiliar Wound
5(9) Secondary 5.0 V: 4 Turns (six strands)
#26 Hexfiliar Wound
Secondary Feedback: 10 Turns
Figure 35. 27 W Off−Line Flyback Regulator #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35-3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance
of 1.0 mH
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16
UC3842B, UC3843B, UC2842B, UC2843B
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
UC2842BDG SOIC−14 55 Units/Rail
(Pb−Free)
UC2842BD1G SOIC−8 98 Units/Rail
(Pb−Free)
TA = −25° to +85°C
UC2842BD1R2G SOIC−8 2500 Tape & Reel
(Pb−Free)
UC2842BNG PDIP−8
1000 Units/Rail
(Pb−Free)
UC3842BNG PDIP−8
1000 Units/Rail
(Pb−Free)
UC3842BDG SOIC−14 55 Units/Rail
(Pb−Free)
UC3842BDR2G SOIC−14 2500 Tape & Reel
TA = 0° to +70°C
(Pb−Free)
UC3842BD1G SOIC−8 98 Units/Rail
(Pb−Free)
UC3842BD1R2G SOIC−8
2500 Tape & Reel
(Pb−Free)
UC3842BVDR2G SOIC−14
2500 Tape & Reel
(Pb−Free)
UC3842BVD1G SOIC−8 98 Units/Rail
TA = −40° to +105°C
(Pb−Free)
UC3842BVD1R2G SOIC−8 2500 Tape & Reel
(Pb−Free)
UC2843BDG SOIC−14 55 Units/Rail
(Pb−Free)
UC2843BDR2G SOIC−14 2500 Tape & Reel
TA = −25° to +85°C
(Pb−Free)
UC2843BD1G SOIC−8 98 Units/Rail
(Pb−Free)
UC2843BD1R2G SOIC−8 2500 Tape & Reel
(Pb−Free)
TA = −25° to +85°C
UC2843BNG PDIP−8 1000 Units/Rail
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
UC3842B, UC3843B, UC2842B, UC2843B
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
UC3843BDG SOIC−14 55 Units/Rail
(Pb−Free)
UC3843BDR2G SOIC−14
2500 Tape & Reel
(Pb−Free)
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18
UC3842B, UC3843B, UC2842B, UC2843B
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8 8 8
1 1 1
SOIC−14
D SUFFIX
CASE 751A
14 14 14
UC384xBDG UC384xBVDG UC284xBDG
AWLYWW AWLYWW AWLYWW
1 1 1
SOIC−8
D1 SUFFIX
CASE 751
8 8 8
384xB 384xB 284xB
ALYW ALYWV ALYW
G G G
1 1 1
x = 2 or 3
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
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19
UC3842B, UC3843B, UC2842B, UC2843B
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
NOTES:
ISSUE L 1. DIMENSION L TO CENTER OF LEAD WHEN
8 5 FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
−B− 3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1 4
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
F B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
NOTE 2 −A− D 0.38 0.51 0.015 0.020
L F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
C K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M --- 10_ --- 10_
−T− J N 0.76 1.01 0.030 0.040
SEATING N
PLANE
M
D K
H G
0.13 (0.005) M T A M B M
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20
UC3842B, UC3843B, UC2842B, UC2843B
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AJ
−X− NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
8 5
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B S 0.25 (0.010) M Y M 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 PROTRUSION SHALL BE 0.127 (0.005) TOTAL
4 IN EXCESS OF THE D DIMENSION AT
−Y− K MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
G
MILLIMETERS INCHES
C N X 45 _ DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
SEATING
PLANE B 3.80 4.00 0.150 0.157
−Z− C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
0.10 (0.004) G 1.27 BSC 0.050 BSC
H M J H 0.10 0.25 0.004 0.010
D J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0 _ 8 _
0.25 (0.010) M Z Y S X S
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
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21
UC3842B, UC3843B, UC2842B, UC2843B
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE J
NOTES:
−A− 1. DIMENSIONING AND TOLERANCING PER
14 8 ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
−B− P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.25 (0.010) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
1 7 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
G R X 45 _ F CONDITION.
C
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
−T− B 3.80 4.00 0.150 0.157
K M J C 1.35 1.75 0.054 0.068
SEATING D 14 PL D 0.35 0.49 0.014 0.019
PLANE
0.25 (0.010) M T B S A S F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT
7X
7.04 14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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22 UC3842B/D