MC34023, MC33023

High Speed Single-Ended

PWM Controller
The MC34023 series are high speed, fixed frequency, single−ended
pulse width modulator controllers optimized for high frequency
operation. They are specifically designed for Off−Line and
DC−to−DC converter applications offering the designer a
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cost−effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, a wide bandwidth error amplifier, a high speed current
sensing comparator, and a high current totem pole output ideally PDIP−16
suited for driving a power MOSFET. P SUFFIX
Also included are protective features consisting of input and 16 CASE 648
reference undervoltage lockouts each with hysteresis, cycle−by−cycle 1
current limiting, and a latch for single pulse metering.
The flexibility of this series allows it to be easily configured for
either current mode or voltage mode control. SOIC−16W
16 DW SUFFIX
Features CASE 751G
• 50 ns Propagation Delay to Output 1

• High Current Totem Pole Output

• Wide Bandwidth Error Amplifier MARKING DIAGRAMS
• Fully−Latched Logic with Double Pulse Suppression 16
• Latching PWM for Cycle−By−Cycle Current Limiting 16
• Soft−Start Control with Latched Overcurrent Reset MC34023P MC33023DW
• Input Undervoltage Lockout with Hysteresis AWLYYWWG AWLYYWWG
1
• Low Startup Current (500 mA Typ)
1
• Internally Trimmed Reference with Undervoltage Lockout
A = Assembly Location
• 90% Maximum Duty Cycle (Externally Adjustable) WL = Wafer Lot
• Precision Trimmed Oscillator YY = Year
• Voltage or Current Mode Operation to 1.0 MHz WW = Work Week
G = Pb−Free Package
• Functionally Similar to the UC3823
• These are Pb−Free Devices PIN CONNECTIONS

Error Amp
16 5.1V 15 Inverting Input 1 16 Vref
Vref
Reference Error Amp 2
4 VCC 15 VCC
Clock Noninverting Input
Error Amp Output 3 14 Output
5 UVLO
RT Clock 4 13 VC
6 Oscillator
CT RT 5 12 Power Ground
13
7 VC CT 6 11 Current Limit
Reference
Ramp 14
Output Ramp 7 10 Ground
Error Amp 3 Latching 12
Output PWM Power Soft-Start 8 9 Current Limit/
Noninverting Error Shutdown
Ground
Input 2 Amp
(Top View)
Inverting 11
Input 1 Current ORDERING INFORMATION
8 9 Limit Ref See detailed ordering and shipping information in the package
Soft-Start Soft-Start Current
Limit/ dimensions section on page 2 of this data sheet.
Shutdown
10 Ground *For additional information on our Pb−Free strategy
This device contains 176 active transistors. and soldering details, please download the
ON Semiconductor Soldering and Mounting
Figure 1. Simplified Application
Techniques Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

July, 2009 − Rev. 7 MC34023/D
 MC34023, MC33023

ORDERING INFORMATION
Device Package Shipping†
MC33023DWG SOIC−16W 47 Units / Rail
(Pb−Free)

MC33023DWR2G SOIC−16W 1000 Units / Reel

(Pb−Free)

MC34023PG PDIP−16 25 Units / Rail

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 30 V
Output Driver Supply Voltage VC 20 V
Output Current, Source or Sink (Note 1) IO A
DC 0.5
Pulsed (0.5 ms) 2.0
Current Sense, Soft−Start, Ramp, and Error Amp Inputs Vin −0.3 to +7.0 V
Error Amp Output and Soft−Start Sink Current IO 10 mA
Clock and RT Output Current ICO 5.0 mA
Power Dissipation and Thermal Characteristics
SO−16L Package (Case 751G)
Maximum Power Dissipation @ TA = + 25°C PD 862 mW
Thermal Resistance, Junction−to−Air RqJA 145 °C/W
DIP Package (Case 648)
Maximum Power Dissipation @ TA = + 25°C PD 1.25 W
Thermal Resistance, Junction−to−Air RqJA 100 °C/W

Operating Junction Temperature TJ +150 °C

Operating Ambient Temperature (Note 2) °C
MC34023 TA 0 to +70
MC33023 −40 to +105
Storage Temperature Range Tstg −55 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.

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 MC34023, MC33023

ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA
is the operating ambient temperature range that applies [Note 2], unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = + 25°C) Vref 5.05 5.1 5.15 V
Line Regulation (VCC = 10 V to 30 V) Regline − 2.0 15 mV
Load Regulation (IO = 1.0 mA to 10 mA) Regload − 2.0 15 mV
Temperature Stability TS − 0.2 − mV/°C
Total Output Variation over Line, Load, and Temperature Vref 4.95 − 5.25 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = + 25°C) Vn − 50 − mV
Long Term Stability (TA = +125°C for 1000 Hours) S − 5.0 − mV
Output Short Circuit Current ISC − 30 − 65 −100 mA
OSCILLATOR SECTION
Frequency kHz
TJ = + 25°C fosc 380 400 420
Line (VCC = 10 V to 30 V) and Temperature (TA = Tlow to Thigh) 370 400 430
Frequency Change with Voltage (VCC = 10 V to 30 V) Dfosc/DV − 0.2 1.0 %
Frequency Change with Temperature (TA = Tlow to Thigh) Dfosc/DT − 2.0 − %
Sawtooth Peak Voltage VOSC(P) 2.6 2.8 3.0 V
Sawtooth Valley Voltage VOSC(V) 0.7 1.0 1.25 V
Clock Output Voltage V
High State VOH 3.9 4.5 −
Low State VOL − 2.3 2.9
ERROR AMPLIFIER SECTION
Input Offset Voltage VIO − − 15 mV
Input Bias Current IIB − 0.6 3.0 mA
Input Offset Current IIO − 0.1 1.0 mA
Open−Loop Voltage Gain (VO = 1.0 V to 4.0 V) AVOL 60 95 − dB
Gain Bandwidth Product (TJ = + 25°C) GBW 4.0 8.3 − MHz
Common Mode Rejection Ratio (VCM = 1.5 V to 5.5 V) CMRR 75 95 − dB
Power Supply Rejection Ratio (VCC = 10 V to 30 V) PSRR 85 110 − dB
Output Current, Source (VO = 4.0 V) ISource 0.5 3.0 − mA
Output Current, Sink (VO = 1.0 V) ISink 1.0 3.6 −
Output Voltage Swing, High State (IO = − 0.5 mA) VOH 4.5 4.75 5.0 V
Output Voltage Swing, Low State (IO = 1 mA) VOL 0 0.4 1.0
Slew Rate SR 6.0 12 − V/ms
PWM COMPARATOR SECTION
Ramp Input Bias Current IIB − −0.5 −5.0 mA
Duty Cycle, Maximum DC(max) 80 90 − %
Duty Cycle, Minimum DC(min) − − 0
Zero Duty Cycle Threshold Voltage Pin 3(4) (Pin 7(9) = 0 V) Vth 1.1 1.25 1.4 V
Propagation Delay (Ramp Input to Output, TJ = + 25°C) tPLH(in/out) − 60 100 ns
SOFT−START SECTION
Charge Current (VSoft−Start = 0.5 V) Ichg 3.0 9.0 20 mA
Discharge Current (VSoft−Start = 1.5 V) Idischg 1.0 4.0 − mA
1. Maximum package power dissipation limits must be observed.
2. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34023 Thigh = +70°C for MC34023
= −40°C for MC33023 = +105°C for MC33023

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 MC34023, MC33023

ELECTRICAL CHARACTERISTICS (VCC = 15 V, RT = 3.65 kW, CT = 1.0 nF, for typical values TA = + 25°C, for min/max values TA
is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
CURRENT SENSE SECTION
Input Bias Current (Pin 9(12) = 0 V to 4.0 V) IIB − − 15 mA
Current Limit Comparator Input Offset Voltage (Pin 11(14) = 1.1 V) VIO − − 45 mV
Current Limit Reference Input Common Mode Range (Pin 11(14)) TJ = + 25°C VCMR 1.0 − 3.0 V
Shutdown Comparator Threshold Vth 1.25 1.40 1.55 V
Propagation Delay (Current Limit/Shutdown to Output, TJ = + 25°C) tPLH(in/out) − 50 80 ns
OUTPUT SECTION
Output Voltage V
Low State (ISink = 20 mA) VOL − 0.25 0.4
(ISink = 200 mA) − 1.2 2.2
High State (ISource = 20 mA) VOH 13 13.5 −
(ISource = 200 mA) 12 13 −
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 0.5 mA) VOL(UVLO) − 0.25 1.0 V
Output Leakage Current (VC = 20 V) IL − 100 500 mA
Output Voltage Rise Time (CL = 1.0 nF, TJ = + 25°C) tr − 30 60 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = + 25°C) tf − 30 60 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold (VCC Increasing) Vth(on) 8.8 9.2 9.6 V
UVLO Hysteresis Voltage (VCC Decreasing After Turn−On) VH 0.4 0.8 1.2 V
TOTAL DEVICE
Power Supply Current ICC mA
Startup (VCC = 8.0 V) − 0.5 1.2
Operating − 20 30
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34023 Thigh = +70°C for MC34023
= −40°C for MC33023 = +105°C for MC33023

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 MC34023, MC33023

100 k 1200
VCC = 15 V RT = 1.2 k

f osc, OSCILLATOR FREQUENCY (kHz)

1 3 5 7 9 CT = 1.0 nF
TA = + 25°C 1.0 MHz
1000
R T , TIMING RESISTOR ( Ω )

2 4 6 8
CT = 800
10 k 1. 100 nF VCC = 15 V
2. 47 nF 600
3. 22 nF RT = 3.6 k
4. 10 nF 400 kHz CT = 1.0 nF
5. 4.7 nF 400
6. 2.2 nF
1.0 k 7. 1.0 nF 200 RT = 36 k
8. 470 pF 50 kHz CT = 1.0 nF
9. 220 pF
470 0
100 1000 104 105 106 107 -55 -25 0 25 50 75 100 125
fosc, OSCILLATOR FREQUENCY (Hz) TA, AMBIENT TEMPERATURE (°C)

Figure 2. Timing Resistor versus Figure 3. Oscillator Frequency

Oscillator Frequency versus Temperature

120 0 1.30
A VOL, OPEN LOOP VOLTAGE GAIN (dB)

100
VTH, ZERO DUTY CYCLE (V) 1.28
, EXCESS PHASE (°C)

80 45 VCC = 15 V
Gain Pin 7(9) = 0 V
60 1.26
Phase
40 90 1.24
20
θ

1.22
0 135

-20 1.20
10 100 1.0 k 10 k 100 k 1.0 M 10 M -55 -25 0 25 50 75 100 125
f, FREQUENCY (Hz) TA, AMBIENT TEMPERATURE (°C)

Figure 4. Error Amp Open Loop Gain and Figure 5. PWM Comparator Zero Duty Cycle
Phase versus Frequency Threshold Voltage versus Temperature

2.55 V 3.0 V

2.5 V 2.5 V

2.45 V 2.0 V

0.1 ms/DIV 0.1 ms/DIV

Figure 6. Error Amp Small Signal Figure 7. Error Amp Large Signal
Transient Response Transient Response

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 MC34023, MC33023

I SC , REFERENCE SHORT CIRCUIT CURRENT (mA)

0 66
Vref , REFERENCE VOLTAGE CHANGE (mV)

-5.0 VCC = 15 V
TA = -55°C 65.6
VCC = 15 V
-10
TA = +125°C TA = + 25°C 65.2
-15
64.8
-20

-25 64.4

-30 64
0 10 20 30 40 50 -55 -25 0 25 50 75 100 125
ISource, SOURCE CURRENT (mA) TA, AMBIENT TEMPERATURE (°C)

Figure 8. Reference Voltage Change Figure 9. Reference Short Circuit Current

versus Source Current versus Temperature
2.0 mV/DIV

2.0 mV/DIV

Vref LINE REGULATION 10 V to 24 V Vref LOAD REGULATION 1.0 mA to 10 mA

(2.0 ms/DIV) (2.0 ms/DIV)

Figure 10. Reference Line Regulation Figure 11. Reference Load Regulation
VIO, CURRENT LIMIT INPUT OFFSET VOLTAGE (mV)

100 1.50

VCC = 15 V
Vth, THRESHOLD VOLTAGE (V)

60 VCC = 15 V 1.46
Pin 11(14) = 1.1 V

20 1.42

-20 1.38

-60 1.34

-100 1.30
-55 -25 0 25 50 75 100 125 -55 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

Figure 12. Current Limit Comparator Input Figure 13. Shutdown Comparator Threshold
Offset Voltage versus Temperature Voltage versus Temperature

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 MC34023, MC33023

I chg , SOFT‐START CHARGE CURRENT ( μ A)

10 0

Vsat , OUTPUT SATURATION VOLTAGE (V)

Source Saturation
VCC = 15 V VCC (Load to Ground)
9.5 -1.0
VCC = 15 V
80 ms Pulsed Load
9.0
-2.0 120 Hz Rate
TA = 25°C
8.5
2.0
8.0

1.0
7.5 Sink Saturation
Ground
(Load to VCC)
7.0 0
-55 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1.0
TA, AMBIENT TEMPERATURE (°C) IO, OUTPUT LOAD CURRENT (A)

Figure 14. Soft−Start Charge Current Figure 15. Output Saturation Voltage
versus Temperature versus Load Current

OUTPUT RISE & FALL TIME 1.0 nF LOAD OUTPUT RISE & FALL TIME 10 nF LOAD
50 ns/DIV 50 ns/DIV

Figure 16. Drive Output Rise and Fall Time Figure 17. Drive Output Rise and Fall Time

30

25 RT = 3.65 kW
I CC , SUPPLY CURRENT (mA)

CT = 1.0 nF
20
VCC Increasing
15
VCC Decreasing
10

5.0

0
0 4.0 8.0 12 16 20
VCC, SUPPLY VOLTAGE (V)

Figure 18. Supply Voltage versus Supply Current

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 MC34023, MC33023

VCC Vin

16 15
Vref Reference
Regulator VCC VCC
4 UVLO
Clock
Vref 9.2 V 13
5 4.2 V
UVLO
Oscillator VC
RT
6 14
CT
Output
PWM R 12
Ramp 7 1.25 V Comparator Q Power Ground
S
Error Amp Output PWM Latch
3 Error Current
2 + 11
Amp Limit
Noninverting Input Current Limit Reference
Inverting Input 9.0 mA
1 9
8 Current Limit/Shutdown
Soft-Start
0.5 V
R
CSS 1.4 V
Q Soft-Start Latch
Shutdown
S

10 Ground

Figure 19. Representative Block Diagram

CT

Clock

Soft-Start
Error Amp
Output Ramp

PWM
Comparator

Output

Figure 20. Current Limit Operating Waveforms

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 MC34023, MC33023

OPERATING DESCRIPTION

The MC33023 and MC34023 series are high speed, fixed output of the error amplifier to less than its normal output
frequency, single−ended pulse width modulator controllers voltage, thus limiting the duty cycle. The time it takes for a
optimized for high frequency operation. They are capacitor to reach full charge is given by:
specifically designed for Off−Line and DC−to−DC
t [ (4.5 • 10 5) C Soft-Start
converter applications offering the designer a cost effective
solution with minimal external components. A A Soft−Start latch is incorporated to prevent erratic
representative block diagram is shown in Figure 19. operation of this circuitry. Two conditions can cause the
Soft−Start circuit to latch so that the Soft−Start capacitor
Oscillator stays discharged. The first condition is activation of an
The oscillator frequency is programmed by the values undervoltage lockout of either VCC or Vref. The second
selected for the timing components RT and CT. The RT pin condition is when current sense input exceeds 1.4 V. Since
is set to a temperature compensated 3.0 V. By selecting the this latch is “set dominant”, it cannot be reset until either of
value of RT, the charge current is set through a current mirror these signals is removed and, the voltage at CSoft−Start is less
for the timing capacitor CT. This charge current runs than 0.5 V.
continuously through CT. The discharge current is ratioed to
be 10 times the charge current, which yields the maximum PWM Comparator and Latch
duty cycle of 90%. CT is charged to 2.8 V and discharged to A PWM circuit typically compares an error voltage with
1.0 V. During the discharge of CT, the oscillator generates an a ramp signal. The outcome of this comparison determines
internal blanking pulse that resets the PWM Latch and, the state of the output. In voltage mode operation the ramp
inhibits the outputs. The threshold voltage on the oscillator signal is the voltage ramp of the timing capacitor. In current
comparator is trimmed to guarantee an oscillator accuracy mode operation the ramp signal is the voltage ramp induced
of 5.0% at 25°C. in a current sensing element. The ramp input of the PWM
Additional dead time can be added by externally comparator is pinned out so that the user can decide which
increasing the charge current to CT as shown in Figure 24. mode of operation best suits the application requirements.
This changes the charge to discharge ratio of CT which is set The ramp input has a 1.25 V offset such that whenever the
internally to Icharge/10 Icharge. The new charge to discharge voltage at this pin exceeds the error amplifier output voltage
ratio will be: minus 1.25 V, the PWM comparator will cause the PWM
latch to set, disabling the outputs. Once the PWM latch is set,
I additional ) I charge
% Deadtime + only a blanking pulse by the oscillator can reset it, thus
10 (I charge) initiating the next cycle.
A bidirectional clock pin is provided for synchronization Current Limiting and Shutdown
or for master/slave operation. As a master, the clock pin A pin is provided to perform current limiting and
provides a positive output pulse during the discharge of CT. shutdown operations. Two comparators are connected to the
As a slave, the clock pin is an input that resets the PWM latch input of this pin. The reference voltage for the current limit
and blanks the drive output, but does not discharge CT. comparator is not set internally. A pin is provided so the user
Therefore, the oscillator is not synchronized by driving the can set the voltage. When the voltage at the current limit
clock pin alone. Figures 28, 29 and 30 provide suggested input pin exceeds the externally set voltage, the PWM latch
synchronization. is set, disabling the output. In this way cycle−by−cycle
Error Amplifier
current limiting is accomplished. If a current limit resistor is
A fully compensated Error Amplifier is provided. It used in series with the power devices, the value of the
features a typical DC voltage gain of 95 dB and a gain resistor is found by:
bandwidth product of 8.3 MHz with 75 degrees of phase I Limit Reference Voltage
margin (Figure 4). Typical application circuits will have the R Sense +
I pk (switch)
noninverting input tied to the reference. The inverting input
will typically be connected to a feedback voltage generated If the voltage at this pin exceeds 1.4 V, the second
from the output of the switching power supply. Both inputs comparator is activated. This comparator sets a latch which,
have a common mode voltage (VCM) input range of 1.5 V to in turn, causes the soft start capacitor to be discharged. In this
5.5 V. The Error Amplifier Output is provided for external way a “hiccup” mode of recovery is possible in the case of
loop compensation. output short circuits. If a current limit resistor is used in
series with the output devices, the peak current at which the
Soft−Start Latch
controller will enter a “hiccup” mode is given by:
Soft−Start is accomplished in conjunction with an
external capacitor. The Soft−Start capacitor is charged by an
internal 9.0 mA current source. This capacitor clamps the

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 MC34023, MC33023

1.4 V and snubbers should be connected as close as possible to the

I shutdown + specific part in question. The PC board lead lengths must be
R Sense
less than 0.5 inches for effective bypassing for snubbing.
In certain applications, it may be desirable to disable the
current limit comparator. This can be accomplished by Instabilities
biasing pin 11 to a level greater than 1.4 V but less than 3.0 V. In current mode control, an instability can be encountered
Under these conditions, the shutdown comparator and at any given duty cycle. The instability is caused by the
soft−start latch are activated during an overcurrent event current feedback loop. It has been shown that the instability
causing the converter to enter an hiccup mode. is caused by a double pole at half the switching frequency.
If an external ramp (Se) is added to the on−time ramp (Sn)
Undervoltage Lockout of the current−sense waveform, stability can be achieved.
There are two undervoltage lockout circuits within the IC. One must be careful not to add too much ramp
The first senses VCC and the second Vref. During power−up, compensation. If too much is added the system will start to
VCC must exceed 9.2 V and Vref must exceed 4.2 V before perform like a voltage mode regulator. All benefits of
the outputs can be enabled and the Soft−Start latch released. current mode control will be lost. Figure 26 is an example of
If VCC falls below 8.4 V or Vref falls below 3.6 V, the outputs one way in which external ramp compensation can be
are disabled and the Soft−Start latch is activated. When the implemented.
UVLO is active, the part is in a low current standby mode
allowing the IC to have an off−line bootstrap startup circuit. Ramp Compensation
Typical startup current is 500 mA.
Ramp Input
1.25 V
Output Ramp
The MC34023 has a high current totem pole output Compensation Se
specifically designed for direct drive of power MOSFETs.
It is capable of up to ± 2.0 A peak drive current with a typical Current
rise and fall time of 30 ns driving a 1.0 nF load. Signal Sn
Separate pins for VC and Power Ground are provided.
With proper implementation, a significant reduction of Figure 21. Ramp Compensation
switching transient noise imposed on the control circuitry is
possible. The separate VC supply input also allows the A simple equation can be used to calculate the amount of
designer added flexibility in tailoring the drive voltage external ramp slope necessary to add that will achieve
independent of VCC. stability in the current loop. For the following equations, the
calculated values for the application circuit in Figure 35 are
Reference also shown.
A 5.1 V bandgap reference is pinned out and is trimmed
to an initial accuracy of ±1.0% at 25°C. This reference has
short circuit protection and can source in excess of 10 mA
Se +
VO
L
ǒ Ǔ
NS
NP
(R S)A i

for powering additional control system circuitry.

Design Considerations where: VO = DC output voltage

Do not attempt to construct the converter on NP, NS = number of power transformer primary
= or secondary turns
wire−wrap or plug−in prototype boards. With high
Ai = gain of the current sense network
frequency, high power, switching power supplies it is
= (see Figures 24 and 25)
imperative to have separate current loops for the signal paths
L= output inductor
and for the power paths. The printed circuit layout should RS = current sense resistance
contain a ground plane with low current signal and high
current switch and output grounds returning on separate
5
paths back to the input filter capacitor. Shown in Figure 36
is a printed circuit layout of the application circuit. Note how For the application circuit: S e +
1.8 μ 8
ǒǓ
2 (0.3)(0.55)

the power and ground traces are run. All bypass capacitors = 0.115 V/ms

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 MC34023, MC33023

PIN FUNCTION DESCRIPTION

Pin

DIP/SOIC Function Description

1 Error Amp This pin is usually used for feedback from the output of the power supply.
Inverting Input

2 Error Amp This pin is used to provide a reference in which an error signal can be produced on the output of the
Noninverting error amp. Usually this is connected to Vref, however an external reference can also be used.
Input
3 Error Amp This pin is provided for compensating the error amp for poles and zeros encountered in the power
Output supply system, mostly the output LC filter.

4 Clock This is a bidirectional pin used for synchronization.

5 RT The value of RT sets the charge current through timing Capacitor, CT.
6 CT In conjunction with RT, the timing Capacitor sets the switching frequency.
7 Ramp Input For voltage mode operation this pin is connected to CT. For current mode operation this pin is
connected through a filter to the current sensing element.

8 Soft−Start A capacitor at this pin sets the Soft−Start time.

9 Current Limit/ This pin has two functions. First, it provides cycle−by−cycle current limiting. Second, if the current is
Shutdown excessive, this pin will reinitiate a Soft−Start cycle.

10 Ground This pin is the ground for the control circuitry.

11 Current Limit This pin voltage sets the threshold for cycle−by−cycle current limiting.
Reference Input

12 Power Ground This is a separate power ground return that is connected back to the power source. It is used to
reduce the effects of switching transient noise on the control circuitry.

13 VC This is a separate power source connection for the outputs that is connected back to the power source
input. With a separate power source connection, it can reduce the effects of switching transient noise
on the control circuitry.
14 Output This is a high current totem pole output.
15 VCC This pin is the positive supply of the control IC.
16 Vref This is a 5.1 V reference. It is usually connected to the noninverting input of the error amplifier.

4 4
5 5
Oscillator Oscillator
CT 6 6
CT

From Current
1.25 V Sense Element 7 1.25 V
7

3 3
1 1

Output Voltage Output Voltage

Feedback Input 2 Feedback Input Vref 2
Vref
In voltage mode operation, the control range on the output of the Error In current mode control, an RC filter should be placed at the ramp input
Amplifier from 0% to 90% duty cycle is from 2.25 V to 4.05 V. to filter the leading edge spike caused by turn−on of a power MOSFET.

Figure 22. Voltage Mode Operation Figure 23. Current Mode Operation

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 MC34023, MC33023

9 Rw
9 ISense
ISense

The addition of an RC filter will eliminate instability caused by the The addition of an RC filter will eliminate instability caused by the
leading edge spike on the current waveform. This sense signal can also leading edge spike on the current waveform. This sense signal can also
be used at the ramp input pin for current mode control. For ramp be used at the ramp input pin for current mode control. For ramp
compensation it is necessary to know the gain of the current feedback compensation it is necessary to know the gain of the current feedback
loop. If a transformer is used, the gain can be calculated by: loop. The gain can be calculated by:

Rw
R Sense
A + A
i
+ turns ratio
i turns ratio

Figure 24. Resistive Current Sensing Figure 25. Primary Side Current Sensing

4
5
6 Oscillator
CT C1

R1 1.25 V
Current Sense 7
Information
R2
3

This method of slope compensation is easy to implement, however, it

is noise sensitive. Capacitor C1 provides AC coupling. The oscillator
signal is added to the current signal by a voltage divider consisting of
resistors R1 and R2.

Figure 26A. Slope Compensation (Noise Sensitive)

Current Sense Output

Figure 26. Ramp
Transformer
Input
Rw RM
Ramp
Input 7 1.25 V

Output Rf 7 1.25 V
CM
RM 3
CM Cf Current Sense Rf Cf
3 Resistor

When only one output is used, this method of slope compensation can be used and it is relatively noise immune. Resistor RM and capacitor CM provide the added
slope necessary. By choosing RM and CM with a larger time constant than the switching frequency, you can assume that its charge is linear. First choose CM, then
RM can be adjusted to achieve the required slope. The diode provides a reset pulse at the ramp input at the end of every cycle. The charge current IM can be calculated
by IM = CMSe. Then RM can be calculated by RM = VCC/IM.

Figure 26B. Slope Compensation (Noise Immune)

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 MC34023, MC33023

5.0 V 4
0V
5
6 Oscillator
RT
CT
Vref
4
RDT
5
6 Oscillator
RT CT

The sync pulse fed into the clock pin must be at least 3.9 V. RT and CT
need to be set 10% slower than the sync frequency. This circuit is also
Additional dead time can be added by the addition of a dead time used in Voltage Mode operation for master/slave operation. The clock
resistor from Vref to CT. See text on Oscillator section for more signal would be coming from the master which is set at the desired
information. operating frequency, while the slave is set 10% slower.

Figure 27. Dead Time Addition Figure 28. External Clock Synchronization

4 4
5 Vref 5
Master Slave
6 6
Oscillator Oscillator
RT
CT

Figure 29. Current Mode Master/Slave Operation Over Short Distances

16 20
Reference
MMBT3906
1.0 k
4
4.7 k NC

4 2200 5
MMBD0914 1.15 RT
Slave
6 Oscillator
5
430
Master
6 MMBT3904
Oscillator CT
RT
CT

Figure 30. Synchronization Over Long Distances

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 MC34023, MC33023

2
+
Vref IB
8
R1 +

CSS 0 VC Vin
R2
Base Charge
-
Removal
15

In voltage mode operation, the maximum duty cycle can be clamped. By 14

the addition of a PNP transistor to buffer the clamp voltage, the Soft−Start 12 To Current RS
current is not affected by R1.
Sense Input
V clamp ) 0.6
The new equation for Soft−Start is t[
9.0 μA
(C SS)
The totem pole output can furnish negative base current for enhanced
In current mode operation, this circuit will limit the maximum voltage transistor turn−off, with the addition of the capacitor in series with the base.
allowed at the ramp input to end a cycle.

Figure 31. Buffered Maximum Clamp Level Figure 32. Bipolar Transistor Drive

VC Vin

VC
15
14
15
14
12 To Current RS
Sense Input
12

A series gate resistor may be needed to dampen high frequency parasitic

oscillation caused by the MOSFET’s input capacitance and any series
wiring inductance in the gate−source circuit. The series resistor will also
decrease the MOSFET switching speed. A Schottky diode can reduce The totem pole output can easily drive pulse transformers. A Schottky
the driver’s power dissipation due to excessive ringing, by preventing the diode is recommended when driving inductive loads at high frequencies.
output pin from being driven below ground. The Schottky diode also The diode can reduce the driver’s power dissipation due to excessive
prevents substrate injection when the output pin is driven below ground. ringing, by preventing the output pin from being driven below ground.

Figure 33. MOSFET Parasitic Oscillations Figure 34. Isolated MOSFET Drive

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14
 V in = 40 V to 56 V

1N5819
4.7 1500 pF 22
Vref 1.8
16 Reference 15 47 k T1 10 μF
Regulator VO = 5.0 V
1.0 4 VCC 10 47 100
L1
22
1.2 k 5 4.2 V UVLO 13 1500 pF 1
Oscillator 9.2 V MBR2535 CTL
10 IRF640
Vref 50
1000 pF 6 UVLO MUR410
14 4.7
0.01 1600 pF
PWM R
22 k 1.25 V Comparator Q 12
7 1N5819 0.3 Ω 2
3 S
2.0 k PWM Latch 100
Current 3.9 k
0.015 μF 1 Limit 11
2

+
Vref
1.0 k
9 100
Error 9.0 μA Shutdown
8 Amp
47 k 0.5 V 47 220 pF

R
0.1 1.4 V
Q
Soft-Start Soft-Start Latch

15
S

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10
MC34023, MC33023

Figure 35. Application Circuit

T1 − Primary: 8 turns #48 AWG (1300 strands litz wire)
Secondary: 2 turns 0.003’’ (2 layers) copper foil Test Condition Result
Bootstrap: 1 turn added to secondary #36 AWG
Core: Philips 3F3, part #4312 020 4124 Line Regulation V in = 40 V to 56 V, I O = 7.5A 14 mV = ± 0.275%
Bobbin: Philips part #4322 021 3525
Coilcraft P3269−A Load Regulation V in = 48 V, IO = 4.0 A to 7.5 A 54 mV = ± 1.0%
L1 − 2 turns #48 AWG (1300 strands litz wire)
Core: Philips 3F3, part #EP10−3F3 Output Ripple V in = 48 V, IO = 7.5 A 10 mVp−p
Bobbin: Philips part #EP10PCB1−8
L = 1.8 μ H Efficiency V in = 48 V, IO = 7.5 A 69.8%
Coilcraft P3270−A
Heatsinks − Power FET: AAVID Heatsink #533902B02552 with clip
Output Rectifiers: AAVID Heatsink #533402B02552 with clip
Insulators − All power devices are insulated with Berquist Sil−Pad 150
1 − 10(1.0 μF) ceramic capacitors in parallel

2 − 5(1.5 Ω ) resistors in parallel

 MC34023, MC33023

1N5819

1N5819
1500 pF

2535CTI
MBR
100 pF
4.0″
100 pF

1N5819
MC34023

+10

1000 pF 0.01
0.01
0.01

100

2535CTI
MBR
2200 pF

1500 pF

6.5″
(Top View)

Figure 36. PC Board With Components

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16
 MC34023, MC33023

(Top View)

4.0″

6.5″
(Bottom View)

Figure 37. PC Board Without Components

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17
 MC34023, MC33023

PACKAGE DIMENSIONS

PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9
3. DIMENSION L TO CENTER OF LEADS
B WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
1 8 MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

F C
INCHES MILLIMETERS
L DIM MIN MAX MIN MAX
A 0.740 0.770 18.80 19.55
S B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
SEATING
−T− PLANE
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
K M G 0.100 BSC 2.54 BSC
H J H 0.050 BSC 1.27 BSC
G J 0.008 0.015 0.21 0.38
D 16 PL K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
0.25 (0.010) M T A M
M 0_ 10 _ 0_ 10 _
S 0.020 0.040 0.51 1.01

SOIC−16W
DW SUFFIX
CASE 751G−03
ISSUE C
NOTES:
D A 1. DIMENSIONS ARE IN MILLIMETERS.
q 2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
16 9 3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
M

5. DIMENSION B DOES NOT INCLUDE DAMBAR

B

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 TOTAL IN
H

h X 45 _
M

EXCESS OF THE B DIMENSION AT MAXIMUM

8X

MATERIAL CONDITION.
0.25

MILLIMETERS
DIM MIN MAX
1 8 A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
16X B B C 0.23 0.32
D 10.15 10.45
0.25 M T A S B S E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q 0_ 7_
A

SEATING
14X e PLANE
A1

T C

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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18