WO2007034740A1 - 表示パネル用の基板とこの基板を備える表示パネル - Google Patents
表示パネル用の基板とこの基板を備える表示パネル Download PDFInfo
- Publication number
- WO2007034740A1 WO2007034740A1 PCT/JP2006/318331 JP2006318331W WO2007034740A1 WO 2007034740 A1 WO2007034740 A1 WO 2007034740A1 JP 2006318331 W JP2006318331 W JP 2006318331W WO 2007034740 A1 WO2007034740 A1 WO 2007034740A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal line
- display panel
- line
- substrate
- pattern
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133354—Arrangements for aligning or assembling substrates
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
Definitions
- the present invention relates to a display panel substrate and a display panel including the substrate.
- the present invention relates to a substrate for a liquid crystal display panel in which a pattern such as a conductive film or an insulating film is formed in a laminated form, and a liquid crystal display panel including this substrate.
- a general liquid crystal display panel includes an array substrate and a color filter substrate, and has a configuration when liquid crystal is filled between them. On the surface of these array substrate and color filter substrate, a pattern such as a conductive film or an insulating film is formed in a laminated form.
- FIG. 3 is a plan view schematically showing an example of a pattern such as wiring formed on the conventional liquid crystal display panel 9.
- the array substrate has a layer in which the pattern of the gate signal line 912 and the auxiliary capacitance line 915 is formed, and a layer in which the pattern of the source signal line 913 and the drain line 914 is formed, and these layers are insulated. They are stacked with a membrane (not shown) in between. With these patterns, a thin film transistor and other predetermined wiring are constructed.
- the pattern of the gate signal line 912 and the auxiliary capacitor line 915 and the pattern of the source signal line 913 and the drain line 914 are positioned with a predetermined accuracy. It is necessary to form together. Therefore, after forming the pattern of the gate signal line 912 and the auxiliary capacitance line 915 and the pattern of the source signal line 913 and the drain line 914, the alignment accuracy of these patterns is measured. When the alignment accuracy deviates from a predetermined allowable range force, the source signal line 913 and the drain line 914 are formed again.
- Measurement of such alignment accuracy is performed, for example, using image recognition. Therefore, measurement marks and patterns for use in image recognition may be formed on the source signal line 913 and the drain line 914 in some cases.
- the drain A straight portion 914a extending in the X-axis direction is formed in a part of the wire 914.
- the edge of the straight line portion 914a and the edge of the gate signal line 912 are detected using image recognition, and the result is used to determine the mutual positional relationship in the Y-axis direction (for example, the center line of the gate signal line 912). Measure the distance D) between the center line B of the straight line 914a of the drain line 914.
- JP-A-2003-302654 is cited as a prior art document related to the present invention.
- the straight line portion 914a needs a certain length so that the edge can be detected with a predetermined accuracy in image recognition.
- the process margin is reduced, which may cause a decrease in yield.
- the problem to be solved by the present invention is a display panel substrate capable of measuring the alignment accuracy while improving the aperture ratio of the picture element, and a display panel using the substrate Or providing a display panel substrate and a display panel using this substrate, which can improve the pixel aperture ratio without reducing the process margin.
- the present invention provides a first conductor pattern and a second conductor pattern.
- a position measurement mark for measuring the alignment accuracy with the screen is formed in a floating island shape.
- floating island means that no electrical connection is formed with the conductive elements forming the first conductor pattern or the second conductor pattern, or the electrical connection is intended. Say nothing. Also, it may not have or be intended to have any electrical or electronic function in relation to the first conductor pattern or the second conductor pattern! /.
- This position measurement mark is formed on the same layer as either the layer on which the first conductor pattern is formed or the layer on which the second conductor pattern is formed.
- the position measurement mark is preferably formed at a position where the aperture ratio of the picture element is not lowered. For example, if the layer on which the position measurement mark is formed is the same layer as the layer on which the second conductor pattern is formed, at least a part of the position to be formed overlaps the first conductor pattern. It is preferable to set the position.
- the position measurement mark has a shape capable of accurately detecting the position when image recognition is used.
- it is preferably formed in a shape including at least one straight part.
- a pattern including a gate signal line can be applied as the first conductor pattern, and a pattern including a source signal line and a drain line can be applied as the second conductor pattern.
- the alignment accuracy of the first conductor pattern (for example, the pattern of the gate signal line) and the second conductor pattern (for example, the pattern of the source signal line and the drain line) is measured. It can be measured using a position measurement mark formed in a floating island shape. Therefore, it is not necessary to form a straight line portion for position measurement in the second conductor pattern and the like, and the degree of freedom in designing the second conductor pattern is improved. As a result, the second conductor pattern can be designed to overlap with other light-shielding elements as much as possible, so that the aperture ratio of the picture element can be improved.
- the position measurement mark indicates the aperture ratio of the pixel. Do not decrease.
- the position measurement mark force has a shape including at least one straight line portion
- the position can be accurately measured by detecting the edge of the straight line portion using image recognition.
- a display panel is configured using such a substrate, it is possible to provide a display panel with a large aperture ratio of picture elements and high luminance.
- FIG. 1 is a diagram schematically showing a configuration of a picture element formed using a display panel substrate according to an embodiment of the present invention, where (a) is a plan view and (b) is A — Cross section along line A.
- FIG. 2 is a plan view schematically showing a configuration of a picture element formed using a display panel substrate according to a modification of the embodiment of the present invention.
- FIG. 3 is a plan view schematically showing an example of the configuration of a conventional picture element.
- FIG. 1 (a) is a plan view schematically showing the configuration of a pixel constructed using a display panel substrate according to an embodiment of the present invention
- FIG. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1 (a).
- a substrate 1 for a display panel according to an embodiment of the present invention includes a gate signal line 12 and an auxiliary capacitance line 15 on a surface of a transparent substrate 16 such as a glass substrate, and a first insulation.
- the layer 17, the source signal line 13 and the drain 14 line, and the second insulating layer 18 are stacked.
- the position measurement mark 11 is formed in a floating island shape at a position overlapping the gate signal line 12.
- convex structures 21a to 21e for controlling the alignment of the liquid crystal are formed on the counter substrate (for example, a color filter substrate).
- this structure is referred to as an “alignment control structure”.
- the gate signal line 12 and the auxiliary capacitance line 15 are formed in the same layer in the same process using the same material.
- An insulating layer is formed on the surface.
- the source signal line 13 and the drain line 14 are formed on the same layer by the same material in the same process and in the same layer.
- the pattern of the gate signal line 12 and the auxiliary capacitance line 15 and the pattern of the source signal line 13 and the drain line 14 are stacked with the insulating film layer interposed therebetween.
- the configuration, material, formation method, and the like of the gate signal line 12, the auxiliary capacitor line 15, the source signal line 13, and the drain line 14 can be applied to conventional configurations and methods, and thus description thereof is omitted.
- the position measurement mark 11 is a pattern for measuring a relative position between the pattern of the source signal line 13 and the drain line 14 and the pattern of the gate signal line 12.
- the position measurement mark 11 is formed in the same layer as the pattern of the source signal line 13 and the drain line 14. And in the process of forming the pattern of the source signal line 13 and the drain line 14, it is formed in the same process using the same material. Therefore, the relative positional relationship between the position measurement mark 11 and the pattern of the source signal line 13 and the drain line 14 is fixed.
- This position measurement mark 11 has no electrical connection or no electrical connection between the gate signal line 12, the auxiliary capacitance line 15, the source signal line 13 or the drain line 14, even if they are shifted. Not intended. In other words, this positioning mark 11 does not have or is not intended to function in any electrical or electronic function in relation to the lines 12, 1 3, 14, 15. . In other words, it is intended to have any contribution or influence on the driving of the thin film transistor.
- the position measurement mark 11 is formed in a shape that can detect the edge by using image recognition and can also calculate the position of the detected edge force. For example, squares as shown in Fig. 1 and other quadrilaterals such as rectangles can be applied. If the sides have opposite sides, such as a quadrilateral, the edges of the opposite sides can be detected and their centers can be calculated, so the position can be measured with high accuracy.
- the present invention is not limited to a quadrilateral, and a shape including a straight portion having at least one side can also be applied.
- the position measurement mark 11 is used to measure the alignment accuracy in the Y-axis direction.
- the straight portion has a shape extending in the X-axis direction.
- the linear portion extends in the Y-axis direction. With such a shape, the position in each axial direction can be measured by detecting the edge of this straight line portion.
- the gate signal line 12 and the auxiliary capacitance line 15, the first insulating layer 17, the source signal line 13 and the drain line 14, the position measurement mark 11, and the second insulating layer 18 were formed. Then, the area including the position measurement mark 11 is photographed. At this time, the edge of the gate signal line 12 is set within the visual field. Then, the edge of the side parallel to the X axis direction of the position measurement mark 11 and the edge of the side parallel to the X axis direction of the gate signal line are detected by image recognition.
- Figure 1 shows the center line of the position measurement mark 11 and the center line of the gate signal line 12).
- the A—A line is the common center line for both.
- the relative positional relationship in the Y-axis direction between the position measurement mark 11 and the gate signal line 12 is calculated from each calculated center line. Thereby, the alignment accuracy in the Y-axis direction between the pattern of the gate signal line 12 and the pattern of the source signal line 13 and the drain line 14 can be measured.
- the process proceeds to the next step. If the relative position deviates beyond the allowable range, the source signal line 13 and the drain line 14 are formed again. It should be noted that various methods and various devices that are conventionally used can be applied to the image recognition method and the device used for image recognition. Therefore, these explanations are omitted.
- the position measurement mark 11 is used to measure the alignment accuracy, it is not necessary to form a straight line portion for measuring the alignment accuracy on the drain line 14. For this reason, the degree of freedom in designing the drain line 14 is improved. Therefore, the drain line 14 is connected to any of the orientation control structures 21a to 21e formed on the counter substrate over almost the entire length thereof. It can be designed to be superimposed on the force, and the aperture ratio of the picture element can be improved. Further, since it is not necessary to reduce the width of the drain line 14 in order not to reduce the aperture ratio, it is not necessary to reduce the process margin. Further, since the position measurement mark 11 is superimposed on the gate signal line 12, the aperture ratio of the picture element is not lowered. Also, because it is formed in a floating island shape, it will not affect the driving of the picture elements.
- the force indicating the configuration in which the position measurement mark 11 is formed in a square is not limited to this shape. In short, it is only necessary that the edge can be detected by using image recognition and the detected edge force can be calculated in its shape.
- FIG. 2 shows a modification of the substrate according to the embodiment of the present invention.
- the position measurement mark 11 ′ may be formed in a rectangular shape. If this position measurement mark 1 1 ′ is used to measure the alignment accuracy in the Y-axis direction, the edge force parallel to the X-axis should be able to detect the edge with a predetermined accuracy using image recognition.
- the length of the side parallel to the Y axis is not particularly limited. Therefore, it can be short in the Y-axis direction as shown in the figure, rectangular, long in the Y-axis direction, or rectangular.
- the shape may be a triangle or other polygons.
- the shape is not limited to a shape having a straight line portion, and may be a shape having a curved line portion.
- the edge of the floating island pattern includes a circular arc shape, the center of the circular arc can be calculated from the detected edge. Therefore, it may be a circular shape, a half-moon shape, a sector shape, or the like.
- the position where the position measurement mark is formed may be a position where a relative positional relationship with the gate signal line can be measured. For example, if the gate signal line and the auxiliary capacitance line are formed at the same time as in this embodiment (in other words, the relative positional relationship between the gate signal line and the auxiliary capacitance line is fixed). If so, the position may be superimposed on the auxiliary capacitance line. Further, it is not always necessary to overlap the gate signal line or the auxiliary capacitance line. For example, it may be a position in the vicinity of the gate signal line or the auxiliary capacitance line. However, in order not to reduce the pixel opening, it is preferable to be outside the pixel area. Yes.
- the layer in which the position measurement mark is formed does not have to be the same as the layer in which the pattern of the source signal line and the drain line is formed. Further, in the above-described embodiment and the modification thereof, the force indicating the configuration in which the position measurement mark is completely superimposed on the gate signal line is not necessarily a configuration in which the whole is superimposed, and a part of which is not necessarily overlapped is configured. Also good.
- the force shown in the configuration used for measuring the alignment accuracy in the Y-axis direction can also be used for measuring the alignment accuracy in the X-axis direction.
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/067,518 US8022559B2 (en) | 2005-09-22 | 2006-09-15 | Substrate for a display panel, and a display panel having the same |
JP2007536469A JP4660552B2 (ja) | 2005-09-22 | 2006-09-15 | 表示パネル用の基板とこの基板を備える表示パネル |
US12/981,699 US8008789B2 (en) | 2005-09-22 | 2010-12-30 | Substrate for a display panel, and a display panel having the same |
US13/182,466 US8193649B2 (en) | 2005-09-22 | 2011-07-14 | Substrate for a display panel, and a display panel having the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005275640 | 2005-09-22 | ||
JP2005-275640 | 2005-09-22 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/067,518 A-371-Of-International US8022559B2 (en) | 2005-09-22 | 2006-09-15 | Substrate for a display panel, and a display panel having the same |
US12/981,699 Continuation US8008789B2 (en) | 2005-09-22 | 2010-12-30 | Substrate for a display panel, and a display panel having the same |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007034740A1 true WO2007034740A1 (ja) | 2007-03-29 |
Family
ID=37888785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/318331 WO2007034740A1 (ja) | 2005-09-22 | 2006-09-15 | 表示パネル用の基板とこの基板を備える表示パネル |
Country Status (4)
Country | Link |
---|---|
US (3) | US8022559B2 (ja) |
JP (1) | JP4660552B2 (ja) |
CN (1) | CN101268415A (ja) |
WO (1) | WO2007034740A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102646629B (zh) * | 2011-07-05 | 2014-04-02 | 北京京东方光电科技有限公司 | 一种阵列基板及其制造方法 |
CN105511126B (zh) * | 2016-01-21 | 2018-11-13 | 京东方科技集团股份有限公司 | 显示面板及其制备方法和检测方法 |
KR102673361B1 (ko) * | 2019-08-02 | 2024-06-13 | 삼성디스플레이 주식회사 | 표시 장치 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04294329A (ja) * | 1991-03-22 | 1992-10-19 | G T C:Kk | 液晶表示装置およびその製造方法 |
JP2001042547A (ja) * | 1999-07-29 | 2001-02-16 | Nec Corp | アライメントマーク及びその製造方法 |
JP2002221735A (ja) * | 2001-01-26 | 2002-08-09 | Matsushita Electric Ind Co Ltd | アクティブマトリクス基板、液晶表示装置、および、それらの製造方法 |
JP2003058073A (ja) * | 2001-08-08 | 2003-02-28 | Seiko Epson Corp | 電気光学装置の製造方法、電気光学装置、および電子機器 |
JP2003209041A (ja) * | 2002-01-15 | 2003-07-25 | Seiko Epson Corp | パターンの位置合わせ精度測定方法、パターンの形成方法、電気光学装置の製造方法、半導体装置の製造方法 |
JP2004304083A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | パターニング精度測定方法、パターンの形成方法、薄膜トランジスタの製造方法、半導体装置の製造方法、電気光学装置、および電子機器 |
JP2004317728A (ja) * | 2003-04-15 | 2004-11-11 | Seiko Epson Corp | アライメントマーク付き基板及びその製造方法並びに電気光学装置用基板及び電気光学装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05323342A (ja) * | 1992-05-19 | 1993-12-07 | Casio Comput Co Ltd | 導電性パターン形成パネル |
TW543787U (en) * | 1996-03-29 | 2003-07-21 | Toshiba Corp | Liquid crystal display apparatus |
TW520457B (en) * | 1997-09-30 | 2003-02-11 | Toshiba Corp | Display panel and position adjusting method for the display panel |
JP2001148480A (ja) * | 1999-11-18 | 2001-05-29 | Nec Corp | 薄膜トランジスタ、薄膜トランジスタの製造装置、および薄膜トランジスタその製造方法 |
JP4884586B2 (ja) * | 2000-12-18 | 2012-02-29 | 株式会社 日立ディスプレイズ | 液晶表示装置 |
KR100801151B1 (ko) * | 2001-10-04 | 2008-02-05 | 엘지.필립스 엘시디 주식회사 | 액정표시장치용 블랙매트릭스 |
JP3992976B2 (ja) * | 2001-12-21 | 2007-10-17 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
TWI310849B (en) * | 2002-02-06 | 2009-06-11 | Au Optronics Corp | Pixel structure |
JP2003302654A (ja) * | 2002-04-12 | 2003-10-24 | Hitachi Ltd | 表示装置 |
JP2004054069A (ja) * | 2002-07-23 | 2004-02-19 | Advanced Display Inc | 表示装置及び表示装置の断線修復方法 |
JP4522145B2 (ja) | 2004-05-25 | 2010-08-11 | シャープ株式会社 | 表示装置用基板、その製造方法及び表示装置 |
TW200638143A (en) * | 2004-10-29 | 2006-11-01 | Toshiba Matsushita Display Tec | Display device |
KR101140241B1 (ko) * | 2005-06-27 | 2012-04-26 | 엘지디스플레이 주식회사 | 얼라인 마크를 포함한 액정표시소자 |
-
2006
- 2006-09-15 WO PCT/JP2006/318331 patent/WO2007034740A1/ja active Application Filing
- 2006-09-15 CN CNA2006800348352A patent/CN101268415A/zh active Pending
- 2006-09-15 JP JP2007536469A patent/JP4660552B2/ja not_active Expired - Fee Related
- 2006-09-15 US US12/067,518 patent/US8022559B2/en active Active
-
2010
- 2010-12-30 US US12/981,699 patent/US8008789B2/en active Active
-
2011
- 2011-07-14 US US13/182,466 patent/US8193649B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04294329A (ja) * | 1991-03-22 | 1992-10-19 | G T C:Kk | 液晶表示装置およびその製造方法 |
JP2001042547A (ja) * | 1999-07-29 | 2001-02-16 | Nec Corp | アライメントマーク及びその製造方法 |
JP2002221735A (ja) * | 2001-01-26 | 2002-08-09 | Matsushita Electric Ind Co Ltd | アクティブマトリクス基板、液晶表示装置、および、それらの製造方法 |
JP2003058073A (ja) * | 2001-08-08 | 2003-02-28 | Seiko Epson Corp | 電気光学装置の製造方法、電気光学装置、および電子機器 |
JP2003209041A (ja) * | 2002-01-15 | 2003-07-25 | Seiko Epson Corp | パターンの位置合わせ精度測定方法、パターンの形成方法、電気光学装置の製造方法、半導体装置の製造方法 |
JP2004304083A (ja) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | パターニング精度測定方法、パターンの形成方法、薄膜トランジスタの製造方法、半導体装置の製造方法、電気光学装置、および電子機器 |
JP2004317728A (ja) * | 2003-04-15 | 2004-11-11 | Seiko Epson Corp | アライメントマーク付き基板及びその製造方法並びに電気光学装置用基板及び電気光学装置 |
Also Published As
Publication number | Publication date |
---|---|
JP4660552B2 (ja) | 2011-03-30 |
JPWO2007034740A1 (ja) | 2009-03-26 |
CN101268415A (zh) | 2008-09-17 |
US8022559B2 (en) | 2011-09-20 |
US8193649B2 (en) | 2012-06-05 |
US20110096284A1 (en) | 2011-04-28 |
US20090236760A1 (en) | 2009-09-24 |
US8008789B2 (en) | 2011-08-30 |
US20110267569A1 (en) | 2011-11-03 |
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