Nothing Special   »   [go: up one dir, main page]

TWI655683B - 承載晶圓與其製造方法、封裝半導體元件之製造方法 - Google Patents

承載晶圓與其製造方法、封裝半導體元件之製造方法 Download PDF

Info

Publication number
TWI655683B
TWI655683B TW102138194A TW102138194A TWI655683B TW I655683 B TWI655683 B TW I655683B TW 102138194 A TW102138194 A TW 102138194A TW 102138194 A TW102138194 A TW 102138194A TW I655683 B TWI655683 B TW I655683B
Authority
TW
Taiwan
Prior art keywords
glass layer
carrier wafer
thermal expansion
coefficient
layer
Prior art date
Application number
TW102138194A
Other languages
English (en)
Other versions
TW201419394A (zh
Inventor
陳承先
李明機
余振華
胡延章
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201419394A publication Critical patent/TW201419394A/zh
Application granted granted Critical
Publication of TWI655683B publication Critical patent/TWI655683B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/02—Physical, chemical or physicochemical properties
    • B32B7/027—Thermal properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
    • B32B7/04—Interconnection of layers
    • B32B7/06—Interconnection of layers permitting easy separation
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C27/00—Joining pieces of glass to pieces of other inorganic material; Joining glass to glass other than by fusing
    • C03C27/06—Joining glass to glass by processes other than fusing
    • C03C27/10—Joining glass to glass by processes other than fusing with the aid of adhesive specially adapted for that purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
    • Y10T428/2495—Thickness [relative or absolute]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thermal Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明提供一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數。

Description

承載晶圓與其製造方法、封裝半導體元件之製造方法
本發明係有關於一種半導體元件，且特別是有關於一種承載晶圓與其製法。
半導體元件廣泛使用於各種電子應用中，例如個人化電腦、行動電話、數位相機以及其他電子元件。半導體元件的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層、導電層以及半導體材料層，並且利用微影技術(lithography)圖案化所形成的各種材料層，以形成電路零件及組件於半導體基板上。
通常是在一個單一半導體晶圓上製造數十個或數百個積體電路。藉由沿著切割線(scribe line)切割積體電路以分割成單一晶粒。舉例而言，在多晶片模組(multi-chip modules)中，或在其他的封裝類型中，接著將分別封裝單一晶粒。
藉由持續降低最小特徵尺寸(minimum faeature size)，半導體工業持續改善各種電子組件(例如電晶體、二極體、電阻、電容等等)的集積密度(integration density)，如此一來，可使更多元件整合於一特定區域中。在一些應用中，這些 尺寸較小的電子組件也僅需要使用較小型封裝即可，其中這些較小型封裝所需使用的區域較傳統的封裝更小。
就半導體元件的應用而言，近來所發展的一種較小型封裝技術為晶圓級封裝層疊(wafer level packaging,WLPs)。舉例而言，在半導體元件的應用方面，近來所發展的其他封裝技術包括三維積體電路(three dimensional integrated circuit,3DIC)與封裝層疊(package on package,PoP)。對於部份封裝製程而言，承載晶圓(carrier wafer)在封裝過程中作為一個臨時安裝或支撐表面使用。
本發明提供一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數。
本發明另提供一種承載晶圓之製造方法，包括：提供一第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數；以及耦合一第二玻璃層到該第一玻璃層，其中該第二玻璃層包括一第二熱膨脹係數。
本發明亦提供一種封裝半導體元件之製造方法，包括：耦合複數個積體電路晶粒到一承載晶圓之上，其中該承載晶圓包括一第一玻璃層耦合到一第二玻璃層；形成一封裝系統於每一個該些積體電路晶粒及該承載晶圓之上，以及移除該承載晶圓。
100a‧‧‧第一玻璃層
100b‧‧‧第二玻璃層
100c‧‧‧玻璃層
100d‧‧‧玻璃層
102‧‧‧膠黏劑
104‧‧‧熱源
106‧‧‧壓力
110‧‧‧承載晶圓
110’‧‧‧承載晶圓
112‧‧‧承載晶圓之形成製程
114a‧‧‧研磨製程
114b‧‧‧研磨製程
116‧‧‧對準特徵結構
117‧‧‧區域
118‧‧‧區域
119‧‧‧區域
120‧‧‧黏合劑
122‧‧‧絕緣層
124‧‧‧晶種層
126‧‧‧乾膜
128‧‧‧組裝體通孔(through assembly vias,TAVs)
130‧‧‧積體電路晶粒
132‧‧‧黏合劑
134‧‧‧接觸墊
135‧‧‧絕緣材料
136‧‧‧模造成型化合物
138‧‧‧第一重新分配層
140‧‧‧第二重新分配層
150‧‧‧封裝半導體元件
152‧‧‧封裝系統
154‧‧‧切割線
160‧‧‧封裝半導體元件的方法流程圖
162‧‧‧耦合積體電路晶粒到承載晶圓，其中承載晶圓包括第 一玻璃層耦合到第二玻璃層
164‧‧‧形成封裝系統於積體電路晶粒及承載晶圓之上
166‧‧‧移除承載晶圓
d1‧‧‧第一玻璃層之厚度
d2‧‧‧第二玻璃層之厚度
d3‧‧‧承載晶圓之總厚度
第1圖至第3圖為一系列剖面圖，用以顯示製造承載晶圓的方法。
第4圖為第3圖所示之承載晶圓的俯視圖。
第5圖為一承載晶圓的剖面圖。
第6圖為一圖表，顯示承載晶圓及承載晶圓之玻璃層的熱膨脹係數(CTE)。
第7圖至第14圖為一系列剖面圖，用以顯示使用本文所描述之承載晶圓的方法。
第15圖為一流程圖，用以顯示封裝半導體元件的方法。
本發明所揭露的部份實施例係關於用於封裝半導體元件的承載晶圓(carrier wafer)。本發明將描述新穎的承載晶圓、及其製造方法以及將其用於半導體元件的封裝方法。
依據本發明所揭露之部份實施例，第1圖至第3圖為一系列剖面圖，用以顯示製造承載晶圓110(請參照第2圖)的方法。首先請參照第1圖，依據本發明所揭露之實施例，第1圖為一剖面圖，顯示第一玻璃層100a以及第二玻璃層100b，其中第二玻璃層100b耦合到第一玻璃層100a。舉例而言，第一玻璃層100a及第二玻璃層100b包括玻璃材料，例如硼矽酸鹽玻璃(borosilicate glass)、鋁矽酸鹽玻璃(alumino-silicate glass)、鹼基鋇矽酸鹽玻璃(alkali-barium silicate glass)或石英(quartz)。舉例而言，在本發明之部份實施例中，第一玻璃層100a及第二玻璃層100b可包括主要成分SiO2，一個或複數個其他成分，以 實現所需的玻璃特性。此外，第一玻璃層100a及第二玻璃層100b可包括其他材料。
第一玻璃層100a包括厚度為尺寸d1，其中尺寸d1為約1.2mm或小於1.2mm。第二玻璃層100b包括一厚度為尺寸d2，其中尺寸d2為約1.2mm或小於1.2mm。在本發明之部份實施例中，尺寸d2基本上與尺寸d1相同。在其他實施例中，尺寸d2與尺寸d1不同。此外，尺寸d1及d2可包括其他數值。
第一玻璃層100a包括第一熱膨脹係數(coefficient of thermal expansion,CTE)，以及第二玻璃層100b包括第二熱膨脹係數。在本發明之部份實施例中，第二玻璃層100b之第二熱膨脹係數不同於第一玻璃層100a之第一熱膨脹係數。舉例而言，依據本發明所揭露之部份實施例，藉由選擇第一玻璃層100a及第二玻璃層100b的材料，以達到所需的整體熱膨脹係數(desired overall CTE)，符合承載晶圓110預定的整體熱膨脹係數值，本文將針對此部份進一步說明。舉例而言，在本發明之部份實施例中，第一玻璃層100a之第一熱膨脹係數及第二玻璃層100b之第二熱膨脹係數包括約5、小於5、7或大於7。此外，在其他實施例中，第一熱膨脹係數及第二熱膨脹係數可包括其他數值，且第二熱膨脹係數基本上(substantially)可與第一熱膨脹係數相同。
第2圖為一剖面圖，用以顯示包括第一玻璃層100a及第二玻璃層100b的複合承載晶圓(composite carrier wafer)110。依據部份實施例，可使用熱接合製程(thermal bonding process)、氫鍵接合製程(hydrogen bonding process)、 壓力接合製程(pressure bonding process)、膠黏劑黏接合製程(gluing process)及/或上述方法之組合，將第二玻璃層100b耦合到第一玻璃層100a。舉例而言，膠黏劑102可用於將第一玻璃層100a與第二玻璃層100b接合在一起。舉例而言，膠黏劑102可包括接著劑(adhesive)或膠帶(tape)。在本發明之部份實施例中，施加膠黏劑102之前，可對第一玻璃層100a及第二玻璃層100b其中之一實施塗轉塗佈(spin-coating)，或對第一玻璃層100a及第二玻璃層100b兩者皆實施塗轉塗佈。舉例而言，膠黏劑102可包括一材料，例如苯並環丁烯(benzocyclobutene,BCB)或SU-8，其中膠黏劑102可包括環氧樹脂(epoxy resin)、γ-丁內酯(gamma butyrolactone)及三芳香基鋶鹽(triaryl sulfonium salt)，此外，膠黏劑102亦可使用其他材料。在熱接合製程的接合步驟中，可將第一玻璃層100a及第二玻璃層100b暴露於熱源104中。舉例而言，第一玻璃層100a及第二玻璃層100b可被加熱至約100℃~約250℃。此外，也可使用其他的溫度。在壓力接合製程中，也可使用壓力106將第一玻璃層100a及第二玻璃層100b接合在一起。舉例而言，壓力106的大小可包括約20到100KN並持續一段預定的時間。此外，也可使用其他數量的壓力106。舉例而言，可使用夾具(clamp)或其他器械施加壓力106，或利用在一腔室中所施加的內部壓力施加壓力106。舉例而言，在本發明之部份實施例中，可使用壓力、氫及/或熱源104，藉由凡德瓦力(Van der Waal’s force)的作用將第一玻璃層100a及第二玻璃層100b接合在一起。此外，可使用其他類型的接合製程。
在本發明之部份實施例中，進行接合製程之後，承載晶圓110包括總厚度為尺寸d3，其中尺寸d3為約1.5mm或小於1.5mm。在其他實施例中，尺寸d3可為約0.85mm。此外，尺寸d3的可包括其他數值。在本發明之部份實施例中，複合承載晶圓110並未包括膠黏劑102。
在本發明之部份實施例中，在耦合第二玻璃層100b到第一玻璃層100a之後，分別利用研磨製程114a或研磨製程114b研磨第一玻璃層100a及/或第二玻璃層100b，如第3圖所示。舉例而言，研磨製程或製程114a及/或114b用於製備承載晶圓110的表面或複數個表面。在本發明之部份實施例中，利用形成製程(forming process)112形成承載晶圓110，同樣顯示於第3圖中。形成製程112包括研磨及/或平坦化(smoothing)承載晶圓110的邊緣，使其成為預定的尺寸及形狀，藉此重新整形(re-shaping)承載晶圓110之第一玻璃層100a及第二玻璃層100b的邊緣。在本發明之部份實施例中，從俯視方向觀察，承載晶圓110的形狀基本上是圓形的，如第4圖所示。
第4圖為第3圖所示之承載晶圓110的俯視圖。在接合製程之後，對準特徵結構(alignment feature)116形成於第一玻璃層100a及第二玻璃層100b的邊緣上，其中對準特徵結構116包括凹口(notch)或其他類型的對準特徵。複數個對準特徵116可交錯地形成於承載晶圓110的邊緣上，圖中未顯示。在本發明之部份實施例中，承載晶圓110可包括直徑為約300mm。此外，承載晶圓110可包括其他的大小或尺寸。
依據其他實施例，第5圖為一承載晶圓110的剖面 圖。承載晶圓110是一個複合的晶圓(composite wafer)，包括複數個玻璃層100a、100b、100c及100d。四個玻璃層100a、100b、100c及100d顯示在第5圖中，然而，依據本發明所揭露之實施例，在承載晶圓100中包括兩個或兩個以上的玻璃層100a、100b、100c及100d。在本發明之部份實施例中，至少一個第三(third)玻璃層100c及100d耦合到第二玻璃層100b或第一玻璃層100a。在承載晶圓110中亦可包括多於四個玻璃層100a、100b、100c及100d。舉例而言，在本發明之部份實施例中，可依序將玻璃層100a、100b、100c及100d接合在一起，或是將玻璃層100a、100b、100c及100d的整體堆疊(entire stack)同時接合在一起。
第6圖為一圖表，顯示承載晶圓110及承載晶圓110之玻璃層100a、100b、100c及100d的熱膨脹係數(CTE)。一些目前可用的市售玻璃層之厚度及熱膨脹係數(CTE)繪製在此圖表中。來自複數個供應商V1、V2、V3、V4的市售玻璃層，以玻璃層的熱膨脹係數(單位：ppm/°K)對玻璃層的厚度(單位：mm)作圖，獲得第6圖。區域118顯示的熱膨脹係數範圍約在4.8-7.0之間，在區域118中，目前尚未有可用的市售玻璃層可以購買。
此方法的優點在於，所製造的複合承載晶圓110具有複數個玻璃層100a及100b，如第2圖所示，或是具有複數個玻璃層100a、100b、100c及/或100d，如第5圖所示，可使承載晶圓110具有落入區域118(如第6圖的圖表所示)中的整體熱膨脹係數。由於部份的封裝系統或整體封裝系統的熱膨脹係數落 入此範圍內，而在封裝應用領域中需要落於該範圍內的熱膨脹係數，因此元件的熱膨脹係數落於該範圍內是非常有利的。本發明所揭露的實施例提供之封裝系統材料的熱膨脹係數是接近或精確匹配的(exact matching of CTE)。舉例而言，在本發明之部份實施例中，承載晶圓110包括整體熱膨脹係數介於約3-11的範圍內。此外，此整體熱膨脹係數可包括其他數值。
舉例而言，第一玻璃層100a可包括在第6圖的圖表上所示的區域117，其中區域117具有熱膨脹係數為約3.8，及第二玻璃層100b可包括在第6圖的圖表上所示的區域119，其中區域119具有熱膨脹係數為約8.0，使承載晶圓110的整體熱膨脹係數為約5.9。此方法的優點在於，可選擇承載晶圓110的玻璃層100a、100b、100c及100d之厚度及熱膨脹係數的各種不同組合，藉以達到所需的承載晶圓110之整體熱膨脹係數值，使承載晶圓110之整體熱膨脹係數值落在區域118內，或低於或高於區域118的熱膨脹係數值。可利用第6圖的圖表選擇玻璃層100a、100b、100c及100d，以達到所需的複合承載晶圓110之整體熱膨脹係數值，並實現更寬的製程容許度(process window)。
依據本發明所揭露之部份實施例，第7圖至第14圖為一系列剖面圖，用以顯示使用本文所描述之承載晶圓110的方法。承載晶圓110用於封裝半導體元件，例如顯示於第10圖至第14圖中的積體電路晶粒130。雖然在第10圖至第14圖中僅顯示一個積體電路晶粒130，然而，依據本發明所揭露之部份實施例，複數個積體電路晶粒130同時封裝在承載晶圓110的表 面上方。移除承載晶圓110之後，切割封裝積體電路晶粒130成單獨的封裝半導體元件，此部份於下文中將進一步描述。
在第7圖中，首先提供本文所述的承載晶圓110，其中此承載晶圓110包括複數個玻璃層100a、100b、100c及/或100d，以達到特定封裝系統所需的熱膨脹係數。在本文中，承載晶圓110亦稱為第一承載晶圓110。黏合劑(adhesive)120形成於承載晶圓110之，其中黏合劑120包括膠黏劑(glue)或膠帶(tape)。絕緣層122形成於黏合劑120之上，其中絕緣層122包括聚苯噁唑(polybenzoxazole,PBO)、聚亞醯胺(polyimide)或其他材料。晶種層(seed layer)124形成於絕緣層122之上。晶種層124包括一金屬，此金屬在電鍍製程中的功能是作為晶種，藉以形成組裝體通孔(through assembly vias,TAVs)128(參照第8圖)。
在第8圖中，乾膜126形成於晶種層122之上，其中乾膜126包括一絕緣材料。使用微影製程圖案化乾膜126，在乾膜126中留下形成組裝體通孔(TAVs)128圖案。在本發明之部份實施例中，使用微影製程圖案化乾膜126，藉由在乾膜126之上沉積一光阻層(圖中未顯示)，並且將光阻層暴露於光源或能量之下，其中此光源或能量係來自於具有所需圖案形成於其上的光罩(lithography mask)所反射。顯影光阻層，並且灰化(ashed)或蝕刻移除部份的光阻層，留下已圖案化的光阻層於乾膜126的頂部之上。接著利用光阻層作為蝕刻罩幕(etch mask)，蝕刻移除乾膜126的暴露部份。接著移除光阻層。又例如，也可使用直接圖案化製程(direct patterning process)圖案化乾膜126。
利用電鍍製程形成組裝體通孔(TAVs)128於乾膜 126的圖案中。在本發明之部份實施例中，組裝體通孔(TAVs)128包括銅(Cu)或銅合金。在本發明之部份實施例中，從俯視的方向觀察，組裝體通孔(TAVs)128包括圓形，橢圓形，正方形或矩形的形狀。此外，組裝體通孔(TAVs)128可包括其他材料及其他形狀。接著移除乾膜126，如第9圖所示。
接著使用黏合劑132將積體電路晶粒130接合到晶種層124，其中黏合劑132包括膠黏劑(glue)或膠帶(tape)，如第10圖所示。舉例而言，積體電路晶粒130包括形成於半導體基板之上的半導體電路，其中半導體基板包括矽或其他類型的半導體材料。積體電路晶粒130包括主動元件或電路，圖中未顯示，其中主動元件或電路可包括電晶體(transistors)、二極體(diodes)、電容(capacitors)、電感(inductors)及其他類型的元件。舉例而言，積體電路晶粒130可包括記憶體元件(memory device)、邏輯元件(logic device)或其他類型的電路。積體電路晶粒130包括複數個接觸墊134設置於絕緣材料135之中，其中絕緣材料135形成於積體電路晶粒130的頂部表面之上。舉例而言，接觸墊134包括銅、銅合金或其他金屬或材料。
同樣顯示於第10圖中，模造成型化合物(molding compound)136形成於積體電路晶粒130、組裝體通孔(TAVs)128及晶種層124的暴露部份之上。如第11圖所示，對模造成型化合物136進行化學機械研磨，以暴露組裝體通孔(TAVs)128的頂部表面以及積體電路晶粒130之接觸墊134的頂部表面。
如第12圖所示，第一重新分配層(RDL)138形成於模造成型化合物136之上，組裝體通孔(TAVs)128的暴露頂部表 面及積體電路晶粒130的接觸墊134之上。第一重新分配層138包括一層或複數層絕緣材料層及一層或複數層導電線層，圖中未顯示。舉例而言，導電線層可包括銅、鋁及其合金或其他材料。舉例而言，絕緣材料層可包括二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、其他絕緣體或上述材料之組合。舉例而言，第一重新分配層層138可包括扇形展開區域(fan-out regions)，圖中未顯示，其中此扇形展開區域適於扇形展開積體電路晶粒130之接觸墊134的足跡範圍(footprint)，在本發明之部份實施例中的擴大到更大的足跡範圍(footprint)。在本發明之部份實施例中，第一重新分配層138可包括凸塊下方金屬化層(under-ball metallization layer,UBM)於其頂部表面上方，用以耦合複數個焊料凸塊(solder bumps)或焊料球(solder balls)，圖中亦未顯示。舉例而言，在本發明之部份實施例中，第一重新分配層138的部份將位於積體電路晶粒130上的接觸墊134電性連接到組裝體通孔(TAVs)128。
同樣顯示於第12圖中，接著承載晶圓110'耦合到第一重新分配層138。承載晶圓110'在本文中也稱為第二承載晶圓110'。在本發明之部份實施例中，第二個承載晶圓110'可包括複數個玻璃層100a、100b、100c及100d，其中複數個玻璃層100a、100b、100c及100d與本文所述用於第一承載晶圓110的複數個玻璃層100a、100b、100c及100d相似或不同。在其他實施例中，第二承載晶圓110'包括單一的玻璃層。在其他實施例中，第二承載晶圓110'包括複數個玻璃層100a、100b、100c及100d，以及第一承載晶圓110包括單一的玻璃層。依據本發 明所揭露的部份實施例，至少第一承載晶圓110及第二承載晶圓110'的其中之一包括複數個玻璃層100a、100b、100c及100d。
如第13圖所示，當第二承載晶圓110'接合到第一重新分配層138之後，使用去接合製程(de-bonding process)移除第一承載晶圓110。也使用一個或複數個蝕刻製程或去接合製程(de-bonding process)移除黏合劑120、絕緣層122及晶種層124。接著，第二重新分配層140形成於模造成型化合物136的底部表面、組裝體通孔(TAVs)128暴露的底部表面以及積體電路晶粒130的底部表面之上。舉例而言，如第14圖所示，第二重新分配層140可包括與上述第一重新分配層138相似的材料層。接著使用去接合製程(de-bonding process)移除第二承載晶圓110'。
封裝半導體元件150包括封裝系統152及積體電路晶粒130。在本發明之部份實施例中，形成於體電路晶粒130之上的封裝系統152包括第一重新分配層138及第二重新分配層140。在其他實施例中，如在第14圖中虛線部份所示，封裝系統152僅包括第一重新分配層138。封裝系統152包括顯示於第14圖中除了積體電路晶粒130之外的組件，亦即，使用封裝系統152封裝積體電路晶粒130。對封裝系統152而言，組裝體通孔(TAVs)128提供垂直連接，例如，介於第一重新分配層138及第二重新分配層140之間的垂直連接。在本發明之部份實施例中，對封裝系統152而言，第一重新分配層138及第二重新分配層140提供水平連接。
在第7圖到第14圖所示的製造流程之後，沿著切割線154分割包括封裝半導體元件150的封裝積體電路晶粒130，如第14圖所示。舉例而言，沿著切割線154分割設置於積體電路晶粒130之上的封裝系統，以形成複數個獨立的封裝半導體元件150。藉由耦合複數個焊料凸塊或焊料球到第一重新分配層138及/或第二重新分配層140，可以耦合每一個封裝半導體元件150到另一個封裝半導體元件150。接著，可將焊料凸塊或焊料球耦合到本文所述之另一個封裝半導體元件150的重新分配層138或重新分配層140，或將焊料凸塊或焊料球耦合到另一種類型的封裝半導體元件，以形成一個封裝體層疊(package-on-package,PoP)元件(圖中未顯示)。
依據本發明所揭露之部份實施例，第15圖為一流程圖，用以顯示封裝半導體元件的方法160。在步驟162中，耦合積體電路晶粒130到承載晶圓110，其中承載晶圓110包括第一玻璃層100a耦合到第二玻璃層100b(也可參照第10圖)。在步驟164中，封裝系統152形成於積體電路晶粒及承載晶圓110之上(第14圖)。在步驟166中，移除承載晶圓110(第12圖及第13圖)。
本發明所揭露的某些實施例包括形成複合承載晶圓110的方法，其中複合承載晶圓110具有複數個玻璃層100a、100b、100c及/或100d，同時也包括形成承載晶圓110的方法，其中承載晶圓110包括複數個玻璃層100a、100b、100c及100d。本發明所揭露的部份實施例包括使用此新穎承載晶圓110封裝半導體元件的方法。
本發明所揭露之部份實施例的優點包括提供新穎的複合承載晶圓110，其中複合承載晶圓110包括複數個玻璃層100a、100b、100c及/或100d。由本文所描述的部份實施例中，可以實現承載晶圓(Carrier wafer)110具有與各種封裝系統及結構的熱膨脹係數值基本上等效(substantially equivalent)的熱膨脹係數。在承載晶圓110的結構中包括複數個玻璃層100a、100b、100c及100d，可實現承載晶圓110之熱膨脹係數值的可調整性。使熱膨脹係數與封裝系統的熱膨脹係數相匹配的能力，能夠達到封裝半導體元件150的翹曲降低(warpage reduction)、翹曲優化(warpage optimization)及翹曲控制(warpage control)，並且也可實現更廣泛的凸塊製程限度(bumping process margin)，例如，後續焊料凸塊形成於第一重新分配層138或第二重新分配層140之上。本方法的優點在於，能夠使承載晶圓110的整體熱膨脹係數落於有利的範圍，此有利的範圍是目前市售的單層承載晶圓所無法實現的熱膨脹係數範圍。新型承載晶圓110的結構及設計易於與封裝製造流程結合。
依據本發明所揭露的部份實施例，提供一承載晶圓，包括：一第一玻璃層，以及一第二玻璃層耦合到該第一玻璃層。該第一玻璃層包括一第一熱膨脹係數，以及該第二玻璃層包括一第二熱膨脹係數。
依據本發明所揭露的其他實施例，提供一承載晶圓的製造方法，包括：提供一第一玻璃層，以及耦合一第二玻璃層到該第一玻璃層。該第一玻璃層包括一第一熱膨脹係數， 以及該第二玻璃層包括一第二熱膨脹係數。
依據本發明所揭露的其他實施例，提供一封裝半導體元件的製造方法，包括：提供一承載晶圓，其中該承載晶圓包括一第一玻璃層耦合到一第二玻璃層。此封裝半導體元件的製造方法尚包括：耦合複數個積體電路晶粒到該承載晶圓之上，形成一封裝系統於每一個該些複數個積體電路晶粒及該承載晶圓之上，以及移除該承載晶圓。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (10)

  1. 一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層藉由一膠黏劑耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數，且其中該第一玻璃層與該第二玻璃層不具金屬層，且該第一玻璃層與該第二玻璃層用於暫時支持一晶圓且之後會被移除，且該膠黏劑包括γ-丁內酯、三芳香基鋶鹽或上述組合。
  2. 如申請專利範圍第1項所述之承載晶圓，其中該第一玻璃層包括一第一厚度，且其中該第二玻璃層包括一第二厚度，其中該第二厚度基本上與該第一厚度相同或不同。
  3. 如申請專利範圍第1項所述之承載晶圓，其中該第二熱膨脹係數與該第一熱膨脹係數不同或相同。
  4. 如申請專利範圍第1項所述之承載晶圓，其中該承載晶圓包括一整體熱膨脹係數介於約3-11ppm/k的範圍內。
  5. 如申請專利範圍第1項所述之承載晶圓，其中該第一熱膨脹係數及第二熱膨脹係數包括約5、小於5、7或大於7ppm/k。
  6. 一種承載晶圓之製造方法，包括：提供一第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數；以及藉由一膠黏劑耦合一第二玻璃層到該第一玻璃層，其中該第二玻璃層包括一第二熱膨脹係數，其中該第一玻璃層與該第二玻璃層不具金屬層，且該第一玻璃層與該第二玻璃層 用於暫時支持一晶圓且之後會被移除，且該膠黏劑包括γ-丁內酯、三芳香基鋶鹽或上述組合。
  7. 如申請專利範圍第6項所述之承載晶圓之製造方法，尚包括耦合至少一第三玻璃層到該第二玻璃層或該第一玻璃層。
  8. 如申請專利範圍第7項所述之承載晶圓之製造方法，尚包括選擇該第一玻璃層之該第一熱膨脹係數，以及該第二玻璃層之該第二熱膨脹係數，以達到承載晶圓預定的整體熱膨脹係數值。
  9. 一種封裝半導體元件之製造方法，包括：耦合複數個積體電路晶粒到一承載晶圓之上，其中該承載晶圓包括一第一玻璃層藉由一膠黏劑耦合到一第二玻璃層，其中該第一玻璃層與該第二玻璃層不具金屬層，且該第一玻璃層與該第二玻璃層用於暫時支持一晶圓且之後會被移除，且該膠黏劑包括γ-丁內酯、三芳香基鋶鹽或上述組合；形成一封裝系統於每一個該些積體電路晶粒及該承載晶圓之上；以及移除該承載晶圓。
  10. 如申請專利範圍第9項所述之封裝半導體元件之製造方法，其中形成該封裝系統包括形成複數個組裝體通孔(through assembly vias,TAVs)於該承載晶圓之上，接合每一個該些積體電路晶粒到該承載晶圓，形成一模造成型化合物(molding compound)於該些組裝體通孔(TAVs)及該些積 體電路晶粒之上，以及形成一第一重新分配層(RDL)於該模造成型化合物之上。
TW102138194A 2012-11-07 2013-10-23 承載晶圓與其製造方法、封裝半導體元件之製造方法 TWI655683B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/671,307 US20140127857A1 (en) 2012-11-07 2012-11-07 Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods
US13/671,307 2012-11-07

Publications (2)

Publication Number Publication Date
TW201419394A TW201419394A (zh) 2014-05-16
TWI655683B true TWI655683B (zh) 2019-04-01

Family

ID=50622731

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102138194A TWI655683B (zh) 2012-11-07 2013-10-23 承載晶圓與其製造方法、封裝半導體元件之製造方法

Country Status (3)

Country Link
US (1) US20140127857A1 (zh)
CN (1) CN103811394B (zh)
TW (1) TWI655683B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130137475A (ko) * 2012-06-07 2013-12-17 삼성전자주식회사 기판 처리방법 및 그에 사용되는 서포트 기판
CN116199432A (zh) 2015-05-28 2023-06-02 Ａｇｃ株式会社 玻璃基板及层叠基板
CN112776425B (zh) * 2015-12-29 2023-05-30 康宁公司 用于减小层压结构中的弓形弯曲的不对称处理方法
TW201806759A (zh) * 2016-05-09 2018-03-01 康寧公司 具有經控制的熱膨脹係數之玻璃積層以及彼之製造方法
WO2017213191A1 (ja) * 2016-06-08 2017-12-14 旭硝子株式会社 調光積層体および複層ガラス
TWI620256B (zh) * 2016-09-14 2018-04-01 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI637468B (zh) * 2017-03-09 2018-10-01 矽品精密工業股份有限公司 封裝結構及其製法
US10829412B2 (en) 2018-07-13 2020-11-10 Corning Incorporated Carriers for microelectronics fabrication
KR20200046265A (ko) 2018-10-24 2020-05-07 삼성전자주식회사 캐리어 기판 및 이를 이용한 패키징 방법
EP3953170A1 (en) * 2019-04-11 2022-02-16 Corning Incorporated Improved edge strength using cte mismatch
EP3953172A1 (en) 2019-04-11 2022-02-16 Corning Incorporated Improved edge stress using differential cooling
US11780210B2 (en) * 2019-09-18 2023-10-10 Intel Corporation Glass dielectric layer with patterning

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313411B1 (en) * 1996-11-08 2001-11-06 W. L. Gore & Associates, Inc. Wafer level contact sheet and method of assembly
US20060210819A1 (en) * 2005-03-15 2006-09-21 Dueber Thomas E Polyimide composite coverlays and methods and compositions relating thereto
US7153759B2 (en) * 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
US20110108940A1 (en) * 2009-11-06 2011-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating backside-illuminated image sensor
US20110316059A1 (en) * 2010-06-29 2011-12-29 Sungkyunkwan University Foundation For Corporate Collaboration Flexible ferroelectric memory device and manufacturing method for the same
US20120183756A1 (en) * 2009-09-28 2012-07-19 Asahi Glass Company, Limited Laminated glass substrate, process for production of the laminated glass substrate, and electronic device equipped with the laminated glass substrate
US20120276689A1 (en) * 2010-11-05 2012-11-01 Joseph Eugene Canale Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same

Family Cites Families (123)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242403A (en) * 1976-08-02 1980-12-30 Libbey-Owens-Ford Company Automotive glazing units and method of producing the same
DE3230554C2 (de) * 1982-04-28 1984-07-26 GTI Glastechnische Industrie Peter Lisec, GmbH, Amstetten Verfahren und Vorrichtung zum Schneiden von Verbundglas
JPS62154614A (ja) * 1985-12-27 1987-07-09 Toshiba Corp 接合型半導体基板の製造方法
WO1989005782A1 (en) * 1987-12-24 1989-06-29 Asahi Glass Company Ltd. Structure and method for fitting mirror base to glass sheet surface
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
JPH0719737B2 (ja) * 1990-02-28 1995-03-06 信越半導体株式会社 Ｓ０１基板の製造方法
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
US5274959A (en) * 1991-06-05 1994-01-04 Texas Instruments Incorporated Method for polishing semiconductor wafer edges
US5567529A (en) * 1991-11-27 1996-10-22 E. I. Du Pont De Nemours And Company Multilayered glass laminate having enhanced resistance to penetration by high velocity projectiles
JPH07109573A (ja) * 1993-10-12 1995-04-25 Semiconductor Energy Lab Co Ltd ガラス基板および加熱処理方法
US5668045A (en) * 1994-11-30 1997-09-16 Sibond, L.L.C. Process for stripping outer edge of BESOI wafers
US6113721A (en) * 1995-01-03 2000-09-05 Motorola, Inc. Method of bonding a semiconductor wafer
US5937312A (en) * 1995-03-23 1999-08-10 Sibond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator wafers
EP0840653B1 (en) * 1995-07-24 2004-06-30 Southwall Technologies, Inc. Improved laminate structure and process for its production
US5645736A (en) * 1995-12-29 1997-07-08 Symbios Logic Inc. Method for polishing a wafer
JPH10259041A (ja) * 1997-03-19 1998-09-29 Fujitsu Ltd 貼り合わせガラス基板構造およびその製造方法
US6784023B2 (en) * 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
JP3266041B2 (ja) * 1996-05-22 2002-03-18 株式会社島津製作所 部材接合法及びこの方法により製造した光学測定装置
FR2762541B1 (fr) * 1997-04-24 1999-07-02 Saint Gobain Vitrage Procede de fabrication d'un vitrage feuillete
US6221774B1 (en) * 1998-04-10 2001-04-24 Silicon Genesis Corporation Method for surface treatment of substrates
US6627478B2 (en) * 1999-05-24 2003-09-30 Tessera, Inc. Method of making a microelectronic assembly with multiple lead deformation using differential thermal expansion/contraction
US6263941B1 (en) * 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
JP4846915B2 (ja) * 2000-03-29 2011-12-28 信越半導体株式会社 貼り合わせウェーハの製造方法
US20010049021A1 (en) * 2000-04-07 2001-12-06 Valimont James L. Methods of improving bonding strength in primer/sealant adhesive systems
US7804552B2 (en) * 2000-05-12 2010-09-28 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device with light shielding portion comprising laminated colored layers, electrical equipment having the same, portable telephone having the same
US7345316B2 (en) * 2000-10-25 2008-03-18 Shipley Company, L.L.C. Wafer level packaging for optoelectronic devices
JP3693972B2 (ja) * 2002-03-19 2005-09-14 富士通株式会社 貼合せ基板製造装置及び基板貼合せ方法
US7140204B2 (en) * 2002-06-28 2006-11-28 Guardian Industries Corp. Apparatus and method for bending glass using microwaves
US7036932B2 (en) * 2002-10-04 2006-05-02 Vision-Ease Lens Laminated functional wafer for plastic optical elements
JP4066889B2 (ja) * 2003-06-09 2008-03-26 株式会社Ｓｕｍｃｏ 貼り合わせ基板およびその製造方法
US20050081993A1 (en) * 2003-10-16 2005-04-21 Ilkka Steven J. Method of bonding glass
DE10348946B4 (de) * 2003-10-18 2008-01-31 Schott Ag Bearbeitungsverbund für ein Substrat
DE10355728B4 (de) * 2003-11-28 2006-04-13 X-Fab Semiconductor Foundries Ag Verbinden von Halbleiterscheiben gleichen Durchmessers zum Erhalt einer gebondeten Scheibenanordnung
JP4465715B2 (ja) * 2004-04-16 2010-05-19 セイコーエプソン株式会社 薄膜デバイス、集積回路、電気光学装置、電子機器
US7387838B2 (en) * 2004-05-27 2008-06-17 Delaware Capital Formation, Inc. Low loss glass-ceramic materials, method of making same and electronic packages including same
JP4918229B2 (ja) * 2005-05-31 2012-04-18 信越半導体株式会社 貼り合わせウエーハの製造方法
KR101285442B1 (ko) * 2005-08-09 2013-07-12 아사히 가라스 가부시키가이샤 박판 유리 적층체 및 박판 유리 적층체를 이용한 표시장치의 제조 방법
US7588481B2 (en) * 2005-08-31 2009-09-15 Shin-Etsu Chemical Co., Ltd. Wafer polishing method and polished wafer
US7862898B2 (en) * 2005-09-08 2011-01-04 3M Innovative Properties Company Adhesive composition and articles made therefrom
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
JP2007245364A (ja) * 2006-03-13 2007-09-27 Fujifilm Corp ノズルプレートの製造方法及び液滴吐出ヘッド並びに画像形成装置
JP5028845B2 (ja) * 2006-04-14 2012-09-19 株式会社Ｓｕｍｃｏ 貼り合わせウェーハ及びその製造方法
JPWO2008007622A1 (ja) * 2006-07-12 2009-12-10 旭硝子株式会社 保護ガラス付ガラス基板、保護ガラス付ガラス基板を用いた表示装置の製造方法及び剥離紙用シリコーン
US7800303B2 (en) * 2006-11-07 2010-09-21 Corning Incorporated Seal for light emitting display device, method, and apparatus
KR101378072B1 (ko) * 2006-11-29 2014-03-27 엘아이지에이디피 주식회사 기판 합착 장치
JP5061694B2 (ja) * 2007-04-05 2012-10-31 信越半導体株式会社 研磨パッドの製造方法及び研磨パッド並びにウエーハの研磨方法
US20080254373A1 (en) * 2007-04-13 2008-10-16 Canyon Materials, Inc. Method of making PDR and PBR glasses for holographic data storage and/or computer generated holograms
JP2009035720A (ja) * 2007-07-11 2009-02-19 Seiko Epson Corp 接合膜付き基材、接合方法および接合体
EP2188225A1 (en) * 2007-08-10 2010-05-26 Guardian Industries Corp. Method of making a heat-treated coated glass article using a polymer dispersion
CN101785086B (zh) * 2007-09-20 2012-03-21 夏普株式会社 显示装置的制造方法和叠层构造体
JP4525734B2 (ja) * 2007-11-02 2010-08-18 セイコーエプソン株式会社 電子部品の実装構造
US7846813B2 (en) * 2008-02-04 2010-12-07 Fairchild Semiconductor Corporation Method and apparatus for bonded substrates
US8450442B2 (en) * 2008-03-04 2013-05-28 Dow Corning Corporation Borosiloxane composition, borosiloxane adhesive, coated and laminated substrates
KR20100137441A (ko) * 2008-03-04 2010-12-30 다우 코닝 코포레이션 실리콘 조성물, 실리콘 접착제, 피복된 기판 및 적층 기판
JP5273875B2 (ja) * 2008-04-08 2013-08-28 株式会社島津製作所 接着剤注入装置
JP5317586B2 (ja) * 2008-08-28 2013-10-16 ラピスセミコンダクタ株式会社 カメラモジュール及びその製造方法
FR2935536B1 (fr) * 2008-09-02 2010-09-24 Soitec Silicon On Insulator Procede de detourage progressif
JP5500076B2 (ja) * 2008-10-23 2014-05-21 旭硝子株式会社 ガラス基板積層装置及び積層ガラス基板の製造方法
EP2351076B1 (en) * 2008-11-16 2016-09-28 Suss MicroTec Lithography GmbH Method and apparatus for wafer bonding with enhanced wafer mating
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP2012040449A (ja) * 2008-12-19 2012-03-01 Sharp Corp 基板洗浄装置
JP5384313B2 (ja) * 2008-12-24 2014-01-08 日本碍子株式会社 複合基板の製造方法及び複合基板
US8193555B2 (en) * 2009-02-11 2012-06-05 Megica Corporation Image and light sensor chip packages
JP5321111B2 (ja) * 2009-02-13 2013-10-23 船井電機株式会社 マイクロホンユニット
DE102009001771A1 (de) * 2009-03-24 2010-09-30 Henkel Ag & Co. Kgaa Erstarrende Klebstoffe mit Silanvernetzung
US8159070B2 (en) * 2009-03-31 2012-04-17 Megica Corporation Chip packages
JP2010275422A (ja) * 2009-05-28 2010-12-09 Seiko Epson Corp 接合方法および接合体
CN102474239B (zh) * 2009-07-30 2014-10-29 日本碍子株式会社 复合基板及其制造方法
US8021755B2 (en) * 2009-08-28 2011-09-20 Corning Incorporated Low thermal expansion glass for EUVL applications
JP5562597B2 (ja) * 2009-08-28 2014-07-30 荒川化学工業株式会社 支持体、ガラス基板積層体、支持体付き表示装置用パネル、および表示装置用パネルの製造方法
CN102481764B (zh) * 2009-09-08 2014-11-05 旭硝子株式会社 玻璃/树脂层叠体、及使用其的电子设备
JP5407693B2 (ja) * 2009-09-17 2014-02-05 旭硝子株式会社 ガラス基板の製造方法、研磨方法及び研磨装置、並びにガラス基板
DE102009051007B4 (de) * 2009-10-28 2011-12-22 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe
US8623496B2 (en) * 2009-11-06 2014-01-07 Wisconsin Alumni Research Foundation Laser drilling technique for creating nanoscale holes
JP5567319B2 (ja) * 2009-11-25 2014-08-06 浜松ホトニクス株式会社 ガラス溶着方法及びガラス層定着方法
KR101640417B1 (ko) * 2010-01-22 2016-07-25 삼성전자 주식회사 반도체 패키지 및 이의 제조 방법
FR2955697B1 (fr) * 2010-01-25 2012-09-28 Soitec Silicon Insulator Technologies Procede de recuit d'une structure
JP5710320B2 (ja) * 2010-03-31 2015-04-30 富士フイルム株式会社 デヒドロアビエチン酸由来の重合体およびその用途
US8329482B2 (en) * 2010-04-30 2012-12-11 Cree, Inc. White-emitting LED chips and method for making same
FR2962363B1 (fr) * 2010-07-07 2013-01-04 Saint Gobain Structure feuilletee pour la visualisation d'informations
US9263314B2 (en) * 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US8846499B2 (en) * 2010-08-17 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Composite carrier structure
JP2013536305A (ja) * 2010-08-23 2013-09-19 ダウ コーニング コーポレーション ホスホシロキサン樹脂、並びにホスホシロキサン樹脂を含む硬化性シリコーン組成物、自立フィルム、及び積層体
BR112013004758A8 (pt) * 2010-08-31 2018-04-03 Mitsubishi Plastics Inc Filme de cobertura de bateria solar e módulo de bateria solar fabricado com o uso do mesmo
US9178105B2 (en) * 2010-09-21 2015-11-03 Amberwave Inc. Flexible monocrystalline thin silicon cell
FI20106063A (fi) * 2010-10-14 2012-06-08 Valtion Teknillinen Akustisesti kytketty laajakaistainen ohutkalvo-BAW-suodatin
US9561639B2 (en) * 2010-11-09 2017-02-07 Sekisui Chemical Co., Ltd. Intermediate film for laminated glasses, and laminated glass
EP2457881B1 (en) * 2010-11-30 2019-05-08 Corning Incorporated Method and apparatus for bending a sheet of material into a shaped article
DE102010063179B4 (de) * 2010-12-15 2012-10-04 Siltronic Ag Verfahren zur gleichzeitigen Material abtragenden Bearbeitung beider Seiten mindestens dreier Halbleiterscheiben
KR20130128439A (ko) * 2010-12-21 2013-11-26 쓰리엠 이노베이티브 프로퍼티즈 컴파니 광학 접착제를 갖는 물품 및 그 제조 방법
JP5814774B2 (ja) * 2010-12-22 2015-11-17 日本碍子株式会社 複合基板及び複合基板の製造方法
JP2014510801A (ja) * 2010-12-22 2014-05-01 ダウ コーニング コーポレーション シリコーン組成物、シリコーン接着剤、コーティングされた基材、及び積層された基材
US8697541B1 (en) * 2010-12-24 2014-04-15 Ananda H. Kumar Methods and structures for preparing single crystal silicon wafers for use as substrates for epitaxial growth of crack-free gallium nitride films and devices
KR20140005241A (ko) * 2011-01-18 2014-01-14 덴끼 가가꾸 고교 가부시키가이샤 초음파 세정 방법 및 장치
WO2012099124A1 (ja) * 2011-01-18 2012-07-26 旭硝子株式会社 合わせガラス及び合わせガラスの製造方法
US20120180854A1 (en) * 2011-01-18 2012-07-19 Bellanger Mathieu Mechanical stacking structure for multi-junction photovoltaic devices and method of making
US20120192928A1 (en) * 2011-01-27 2012-08-02 Mark Francis Krol Laminated pv module package
JP5286382B2 (ja) * 2011-04-11 2013-09-11 株式会社日立製作所 半導体装置およびその製造方法
US20120280368A1 (en) * 2011-05-06 2012-11-08 Sean Matthew Garner Laminated structure for semiconductor devices
DE102011051146B3 (de) * 2011-06-17 2012-10-04 Precitec Optronik Gmbh Prüfverfahren zum Prüfen einer Verbindungsschicht zwischen waferförmigen Proben
TWI572480B (zh) * 2011-07-25 2017-03-01 康寧公司 經層壓及離子交換之強化玻璃疊層
FR2978525B1 (fr) * 2011-07-29 2018-05-18 Saint-Gobain Glass France Vitrage multiple lumineux de meuble
JP5659118B2 (ja) * 2011-09-20 2015-01-28 株式会社東芝 半導体装置及びその製造方法
US20130180760A1 (en) * 2011-09-22 2013-07-18 Hitachi Chemical Company, Ltd. Laminate body, laminate plate, multilayer laminate plate, printed wiring board, and method for manufacture of laminate plate
US20130112459A1 (en) * 2011-09-22 2013-05-09 Hitachi Chemical Company, Ltd. Laminate body, laminate plate, multilayer laminate plate, printed wiring board, and method for manufacture of laminate plate
US9117682B2 (en) * 2011-10-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and structures thereof
US9492990B2 (en) * 2011-11-08 2016-11-15 Picosys Incorporated Room temperature glass-to-glass, glass-to-plastic and glass-to-ceramic/semiconductor bonding
US20130114219A1 (en) * 2011-11-08 2013-05-09 Sean Matthew Garner Opto-electronic frontplane substrate
BE1020331A4 (fr) * 2011-11-29 2013-08-06 Agc Glass Europe Vitrage de contrôle solaire.
JP5836223B2 (ja) * 2011-12-02 2015-12-24 株式会社神戸製鋼所 貼合基板の回転ズレ量計測装置、貼合基板の回転ズレ量計測方法、及び貼合基板の製造方法
KR101317396B1 (ko) * 2011-12-05 2013-10-14 한국과학기술연구원 피에이치 농도 측정이 가능한 탐침 구조체
EP2858106B1 (en) * 2012-05-30 2019-05-08 Olympus Corporation Method for producing semiconductor apparatus
DE112013003488B4 (de) * 2012-07-12 2021-08-19 Ngk Insulators, Ltd. Verbundsubstrat, piezoelektrische vorrichtung und verfahren zur herstellung eines verbundsubstrats
US9165792B2 (en) * 2012-09-25 2015-10-20 Infineon Technologies Ag Integrated circuit, a chip package and a method for manufacturing an integrated circuit
EP2717307A1 (en) * 2012-10-04 2014-04-09 Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO Releasable substrate on a carrier
US9322820B2 (en) * 2013-03-14 2016-04-26 Wisconsin Alumni Research Foundation System and apparatus for nanopore sequencing
JP6159426B2 (ja) * 2013-03-14 2017-07-05 ラヴィヴ エルリク 高度の回転性を有するｍｅｍｓヒンジ
DE112013006831T5 (de) * 2013-03-15 2015-12-10 Schott Glass Technologies (Suzhou) Co., Ltd. Chemisch vorgespanntes flexibles ultradünnes Glas
JP2016520501A (ja) * 2013-03-15 2016-07-14 キネストラル テクノロジーズ，インク． レーザ切断強化ガラス
CN105393336B (zh) * 2013-07-22 2017-10-31 日本碍子株式会社 复合基板、其制造方法、功能元件以及晶种基板
KR102265083B1 (ko) * 2013-08-22 2021-06-15 삼성전자주식회사 가변강성 필름, 가변강성 유연 디스플레이 및 이의 제조 방법
US9527769B2 (en) * 2013-10-09 2016-12-27 Corning Incorporated Reverse photochromic borosilicate glasses
US9318632B2 (en) * 2013-11-14 2016-04-19 University Of South Florida Bare quantum dots superlattice photonic devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313411B1 (en) * 1996-11-08 2001-11-06 W. L. Gore & Associates, Inc. Wafer level contact sheet and method of assembly
US7153759B2 (en) * 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
US20060210819A1 (en) * 2005-03-15 2006-09-21 Dueber Thomas E Polyimide composite coverlays and methods and compositions relating thereto
US20120183756A1 (en) * 2009-09-28 2012-07-19 Asahi Glass Company, Limited Laminated glass substrate, process for production of the laminated glass substrate, and electronic device equipped with the laminated glass substrate
US20110108940A1 (en) * 2009-11-06 2011-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating backside-illuminated image sensor
US20110316059A1 (en) * 2010-06-29 2011-12-29 Sungkyunkwan University Foundation For Corporate Collaboration Flexible ferroelectric memory device and manufacturing method for the same
US20120276689A1 (en) * 2010-11-05 2012-11-01 Joseph Eugene Canale Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same

Also Published As

Publication number Publication date
CN103811394B (zh) 2016-12-28
TW201419394A (zh) 2014-05-16
US20140127857A1 (en) 2014-05-08
CN103811394A (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
TWI655683B (zh) 承載晶圓與其製造方法、封裝半導體元件之製造方法
US11069656B2 (en) Three-layer package-on-package structure and method forming same
TWI556349B (zh) 半導體裝置的結構及其製造方法
US10867896B2 (en) Molding compound structure
US9953955B2 (en) Integrated fan-out package structures with recesses in molding compound
KR101562709B1 (ko) 반도체 다이 패키지의 휨 제어
US8803306B1 (en) Fan-out package structure and methods for forming the same
TWI717580B (zh) 封裝結構及其製造方法
TWI514542B (zh) 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ）
TWI630664B (zh) 封裝結構及其形成方法
US7772691B2 (en) Thermally enhanced wafer level package
TWI575664B (zh) 封裝結構及其形成方法
TW201913928A (zh) 半導體元件封裝及其製造方法
TW201603202A (zh) 封裝半導體裝置的方法及封裝的半導體裝置
CN105895616A (zh) 金属氧化物层状结构及其形成方法
CN105428329A (zh) 具有ubm的封装件和形成方法
TWI574333B (zh) 電子封裝件及其製法
TW201639085A (zh) 電子封裝件之製法及電子封裝結構
CN109216215B (zh) 半导体器件和制造方法
US20160307833A1 (en) Electronic packaging structure and method for fabricating electronic package