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TWI570879B - 半導體總成及晶粒堆疊總成 - Google Patents

半導體總成及晶粒堆疊總成 Download PDF

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TWI570879B
TWI570879B TW099120462A TW99120462A TWI570879B TW I570879 B TWI570879 B TW I570879B TW 099120462 A TW099120462 A TW 099120462A TW 99120462 A TW99120462 A TW 99120462A TW I570879 B TWI570879 B TW I570879B
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die
conductive material
assembly
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TW201119007A (en
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雷納度 高
格蘭特 維拉芬森席歐
傑佛瑞 李爾
西門 麥克艾瑞爾
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英維瑟斯公司
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Description

半導體總成及晶粒堆疊總成
本申請案根據R.公司等於2009年6月26日所提出名稱為“用於以鋸齒組態堆疊之晶粒之電連接”之美國暫時申請案61/220,986,且併提於此以供參考。
本發明係有關積體電路晶片之電連接,特別是堆疊晶粒之電互連。
典型的半導體晶粒具有形成積體電路之前(主動)側、背側及側壁。側壁與前側相接於前緣,並與後側相接於後緣。半導體晶粒通常設有互連墊(晶粒墊),其位於晶粒上電路之電互連前側,裝置中另一電路佈設晶粒。通常,晶粒墊包含諸如銅或鋁之導電或金屬化之金屬。
所提供某些晶粒在沿一或更多晶粒邊緣之前側具有晶粒墊,且此等均稱為周緣墊晶粒。所提供其他晶粒墊在接近晶粒中央之前側上配置成一行或兩行,且此等均稱為中央墊晶粒。某些晶粒具有配置成區域陣列之墊。然而,晶粒墊可如所提供,配置於晶粒中,該晶粒可“重選路”以提供適當的互連墊配置於晶粒之一或更多邊緣。
曾提議多種方法來增加積體電路晶片封裝中之主動半導體電路之密度,惟將封裝尺寸(封裝映罩表面、封裝厚度)減至最小。於製造具有較小映罩表面之高密度封裝之方法中,互疊及安裝相同或不同功能之二或更多半導體晶粒於封裝基板上。
S. McElrea等人於2008年五月20日提出申請,名稱為“電連接堆疊總成”之美國申請案12/124,077說明一種堆疊晶粒組態,其中晶粒上之互連墊藉導電互連材料之引線電連接。於某些組態中,堆疊中之相鄰晶粒設有沿晶粒邊緣配置於前側之互連墊,且上方晶粒之邊緣之緣相對於其下方之晶粒之邊緣錯位。該錯位顯示下晶粒上互連墊區域之至少一部分,俾下晶粒上之墊可用來與位於上方之晶粒之墊電連接。導電互連材料係就像例如可固化導電環氧樹脂之導電聚合物。較大堆疊總成可藉由於模組設計中建構錯位堆疊晶粒單元及接著堆疊此等單元製造。一個此種模組單元可藉對齊及連接之個別模組單元之互連端反轉及互疊安裝;所形成兩層總成提供鋸齒組態。
T. Caskey等人於2008年五月20日提出申請,名稱為“藉由脈衝調配形成之電互連”之美國申請案12/124,097說明一種堆疊中晶粒電互連方法,及藉由於一系列脈衝中原位沉積電互連材料以形成連續電互連之具有基板之堆疊晶粒。互連材料可為可固化材料,其可在未固化或局部固化狀態下沉積;且該材料可於調配後之中間步驟局部或額外固化;且可在完成調配時,完全固化。適當互連材料包含充填粒子形式之導電材料之聚合物,就像例如充填金屬聚合物,其例如包含金屬充填環氧樹脂、金屬充填熱固聚合物、金屬充填熱塑聚合物或導電油墨。
於本發明之一般態樣中,特點在於安裝並隆起於支撐上方,以及電連接於支撐中之電路之晶粒(或晶粒堆疊)。導電材料柱形成於支撐之安裝側之一組接合墊上,且隆起晶粒(隆起晶粒堆疊之至少一晶粒)藉使晶粒上互連墊接觸柱之導電材料之引線電連接於支撐,並透過此等柱電連接於該支撐。
於某些實施例中,下晶粒或下晶粒堆疊或半導體封裝位於支撐與隆起晶粒間;且於某些實施例中,下晶粒或下晶粒堆疊或半導體封裝電連接於支撐。於某些實施例中,下晶粒堆疊係下成層錯位堆疊晶粒總成,且第一層中之晶粒以晶粒對晶粒方式電連接,又,下層藉使晶粒上互連墊接觸柱之導電材料之引線以及一組支撐上之接合墊,電連接於支撐。
於某些實施例中,隆起晶粒堆疊係成層錯位堆疊晶粒總成,其中晶粒層之互連緣面對第一方向,且互連晶粒墊緣對準柱。
於本發明各個實施例中,特點在於以鋸齒組態成層錯位堆疊晶粒總成,其中第一(下)層之互連緣面對第一方向,且堆疊於第一層之第二(上)層之互連緣面對異於第一方向之第二方向。第二層互連緣方向可正對或正交第一層互連緣方向。第一層中之晶粒以晶粒對晶粒方式電連接,又,該層藉使晶粒上互連墊接觸之導電材料之引線以及一組支撐上之接合墊,電連接於支撐。導電材料柱形成於第二組接合墊上,且第二層之晶粒以晶粒對晶粒方式電互連,又該層藉使晶粒上互連墊接觸柱之導電材料之引線電連接於支撐,並透過多數柱電連接於基板。
導電材料包含於聚合物基質中的金屬粒子。適當材料包含能以可流動形式沉積且之後硬化或容許硬化以形成導體之材料。互連材料可為可固化材料,且可沉積成未固化或局部固化狀態;且該材料可於沉積後之中間階段局部或額外固化,並可在沉積完成時完全固化。適當的互連材料包含充填粒子形式之導電材料之聚合物,例如金屬充填聚合物,其例如包含金屬充填環氧樹脂、金屬充填熱固化聚合物、金屬充填熱塑聚合物以及導電油墨。
互連材料可藉適於特定材料之任何技術沉積。於某些實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網版印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈動調配例如成滴狀。
於本發明之另一一般態樣中,特點在於一種藉由以下步驟將安裝並隆起於支撐上方之晶粒(或一疊晶粒)電連接於支撐中之電路之方法:於支撐之安裝側之一組接合墊上形成多數導電材料柱;以及形成導電材料之引線,各該引線與隆起晶粒(或在隆起疊之晶粒的至少一晶粒)上之互連晶粒墊及柱接觸。於某些實施例中,引線跨柱與互連晶粒墊間之間隙。於某些實施例中,形成柱包括沉積可固化導電柱材料於接合墊上及固化沉積之引線材料。於某些實施例中,形成引線包括沉積與柱接觸之可固化導電引線材料,以及固化沉積之引線材料。
於本發明之一般態樣中,特點在於一種藉由以下步驟製造以鋸齒組態成層錯位堆疊之晶粒總成之方法:堆疊或安裝第一(下)層於支撐上,配置成第一(下)層之互連緣面對第一方向,俾第一層中至少最下方晶粒上之互連墊與該支撐上之第一組接合墊對齊;晶粒對晶粒電互連該第一層中之晶粒,並藉由形成第一層導電材料引線,電連接該層於該支撐,該第一層導電材料引線之每一者與該晶粒上之至少一互連墊以及該等第一組接合墊接觸;堆疊或安裝第二(上)層於該第一層上方,配置成第二(上)層之互連緣面對第二方向;形成導電材料柱於該支撐上之第二組接合墊上;以及形成導電材料之第二(上)層引線,各該引線與該第二(上)層中至少一晶粒上之互連晶粒墊及該柱接觸。於某些實施例中,形成第一層導電材料引線包括沉積可固化導電引線材料,該導電引線材料與至少一下層晶粒上之晶粒墊接觸,以及固化沉積之引線材料。於某些實施例中,形成第二層引線包括跨該柱與該互連晶粒墊間之間隙形成引線。於某些實施例中,形成柱包括沉積可固化導電柱材料於接合墊及固化沉積之引線材料。於某些實施例中,形成第二層導電材料引線包括沉積可固化導電引線材料,該導電引線材料與至少一上層晶粒上之晶粒墊接觸及固化沉積之引線材料。柱、第一層引線及第二層引線可由相同或不同材料形成。
於某些實施例中,製造成層錯位堆疊之晶粒總成之方法包括於堆疊或安裝第一層之後及形成第一層引線之前,以保形介電塗層塗布該總成,並形成多數開口於待與該等第一層引線接觸之至少經選擇之晶粒墊及接合墊。於某些實施例中,製造成層錯位堆疊之晶粒總成之方法包括於堆疊或安裝第二層之後及形成該等柱之前,以保形介電塗層塗布該總成,並形成多數開口於待與該等柱接觸之至少經選擇之第二層晶粒墊及接合墊。
現在參考說明本發明之選擇性實施例之圖式,進一步說明本發明。此等圖式顯示本發明之特點及其與其他特點和構造間之關係,惟其未按比例繪製。為改進顯示之清晰度,於圖式中顯示本發明之實施例,對應於其他圖式之元件的元件並未全部特別另標元件符號,雖則其在所有圖式中均可馬上辨識。亦為顯示之清晰度,於圖式中未顯示某些特點,畢竟其等對本發明瞭解不必要。於說明中的某些點,可參考圖式中諸視點之位向,使用“上方”、“下方”、“上”、“下”、“頂部”、“底部”等,此等用辭不擬限制使用中裝置之位向。
第1A圖以俯視圖顯示安裝於支撐上之錯位堆疊晶粒10之配置之圖式,各晶粒具有互連墊,其配置在鄰接前晶粒緣之一邊緣;且第1B圖如第1A圖中1B-1B所示,俯視顯示安裝於支撐上之堆疊。於此例子中,堆疊包含七個晶粒141,142,143,144,145,146,147,各安裝成晶粒之主動側背離支撐17。參考堆疊中之最上方晶粒147,例如,互連墊148位在沿前晶粒緣149之一行142中。此例子中之晶粒147藉電絕緣保形塗層144覆蓋於所有表面(背表面、前表面及側壁)上,該電絕緣保形塗層144設有露出互連墊148之開口145。如於此等例子中,堆疊中之連續塗佈直接靠在另一個上,俾上晶粒之背側上之塗層可接觸下晶粒之前側上之塗層。於其他例子中,保形塗層可覆蓋較所有晶粒表面小,或者其可僅覆蓋一或更多晶粒表面之一部分;一般而言,電絕緣保形塗層可至少形成於須要與其他特點或表面電絕緣之表面或特點,此等其他特點或表面可與完成之總成接觸。任選地或額外地,晶粒附接膜可層疊於一或更多晶粒之背側。
於第1A及1B圖所示例子中,各晶粒具有位於沿一前晶粒緣(“互連”緣)之邊緣之互連墊,且堆疊中之連續晶粒配置成其個別互連緣面朝堆疊之相同面。堆疊中之連續晶粒沿正交晶粒緣之方向位移(錯位),多數墊沿晶粒緣,且於在此所示之例子中,此錯位使諸墊在各下晶粒中完全露出。該組態提供梯狀晶粒堆疊,且電連接形成於此等梯級上方。
堆疊安裝在支撐17(例如封裝基板)上,該支撐17具有一行露出於晶粒安裝表面171之接合位置172之行173。接合位置連接於(或構成一部分)支撐中之電路(未圖示)。該晶粒附著於基板之晶粒安裝表面171,並配置成第一(最下方)晶粒141之前側壁沿接合位置172之行173對齊。於在此所示例子中,最下方晶粒之前側壁重疊接合位置至很小程度;於其他例子中,最下方晶粒之前側壁可從接合位置之行後退,或可重疊接合位置至較大程度。如於此等例子中,第一晶粒之塗佈背側可直接接觸晶粒安裝表面171,並可用來附著該堆疊於支撐。任選地,晶粒附接膜可層疊於第一晶粒之背側,以附著該堆疊於支撐。
如第1C圖所示,於堆疊中,晶粒電連接(晶粒對晶粒),且堆疊藉配設成與例如墊148及接合墊172接觸之互連材料之引線174,電連接於支撐。互連材料可為導電聚合物,就像包含導電材料之粒子之聚合物基質。該材料可為諸如可固化聚合物之可固化材料,例如就像是導電環氧樹脂(例如充填銀之環氧樹脂);且互連可藉由將未固化之材料形成為預定圖案,且此後固化材料以獲得與接合墊及接合位置之電接觸,並確保其間引線之完整性來形成。該材料可為導電油墨,其可於載體中包含導電粒子,且其可或不可包含聚合物基質。
如於美國申請案12/124,097中所說明,可藉由於模組設計中建構錯位晶粒堆疊單元,並接著堆疊這些單元,製成較大堆疊晶粒總成。可藉對齊及連接之個別模組單元,反轉及互疊安裝一個此種模組單元;例如依第2A,2B圖所示,形成之二層總成提供鋸齒組態。第一錯位晶粒堆疊構成第一模組單元(第一層)210,其可安裝於及電連接於支撐217上之接合墊272;且可藉對齊及連接之互連214,224之端部,反轉及安裝第二模組單元(第二層)212於第一層210上方。於第2A圖中舉例顯示形成之總成。一隔件(於第2A圖中未圖示)可設在第一與第二層間。如可理解,在第一與第二模組單元相同情況下,當第二單元反轉時,互接端之個別墊行反平行;亦即,現在,第一單元上之第一互連對齊第二晶粒上之最後互連。於此種組態中,可能需要重選路電路來將適當的個別特點連接於晶粒上。重選路電路可設在第一單元上之頂部晶粒之主動層;或者,在包含隔件情況下,該隔件可構成一插入件(於第2A圖中未圖示),其包含一或更多介電層及一或更多導電重選路層。第2B圖顯示第二層安裝於第一層上方惟未翻轉之組態。在此,第二層220之互連224之端部接近第一層210中頂部晶粒之相對緣。包含至少一介電層216(就像例如玻璃)及至少一圖型化導電層244之插入件位於諸模組單元間,以提供從第一層210之一緣上之互連214之端部至第二層220之一(相對)緣上之互連224之端部之重選路。
可利用特定互連材料之流變性質(就像例如黏度或觸變性)來提供具有控制形狀之沉積。特別是,對某些材料而言,在調配脈衝完成後的一段時間內,沉積團塊之一部分可保持與沉積工具接觸,且可在分離完成前移動該工具。在未固化狀態下,具有較高黏度及觸變性之導電聚合物材料可在沉積期間,藉由於調配脈衝完成後不久移動沉積工具,予以成形,以沿選擇方向拉出材料之“尾部”,形成具有選擇形狀之互連。結果,可藉工具之方向及移動速率及材料之流變性質判定沉積團塊之形狀。
如以上所述,第1A,1B,1C,2A及2B圖所示例子中之錯位晶粒堆疊如圖示具有七個晶粒。考慮具有其他數目之晶粒之錯位堆疊,且通常較常見的是偶數晶粒(例如每一錯位堆疊有四個晶粒或八個晶粒)。
參考第3A圖,例如依圖示附接液滴304於支撐320(諸如晶粒上之墊,或基板上之接合墊)上之電接觸328。於圖示例子中,在液滴形成期間,使工具梢朝向電接觸328,並調配材料團塊於接觸。接著,當材料團塊仍與工具梢接觸時,垂直移動離開目標以向上拉出材料“尾巴”。最後,液滴團塊與工具梢分離,且形成之液滴304具有大致錐形。適於形成成形液滴之材料包含導電環氧樹脂(充填金屬之環氧樹脂),其在未固化狀態下,具有約30000cps或更大的黏度及/或約6.5或更大的觸變指數。如可瞭解,黏度及/或觸變度不得太高,否則,材料沒有用,否則其無法與互接端子良好接觸。
以上參考及併提於此供參考之美國申請案12/124,097說明形成一系列此種大致錐形之自由立起液滴,此等液滴於晶粒堆疊面上相互鄰接,提供接觸互連端子之材料柱。此種柱組態可在垂直相鄰之晶粒間有很大空隙,以致互連引線須在無側面支撐下垂直越過該間時特別有用。如以上參考及併提於此供參考之美國申請案12/124,097所說明,這可提供於具有相互安裝及藉隔件分隔之多數晶粒堆疊中;或藉晶粒之交錯配置(亦即,在待連接晶粒間之間隙大約等於(或略微超過)夾裝之錯位晶粒之厚度情況下)提供;或於具有長形堆疊晶粒之晶粒堆疊中,各晶粒在位向上相對於下方之晶粒成90°。
如於美國申請案12/124,097中進一步說明,工具可在異於垂直遠離目標之其他方向中移動,且可形成各種有用液滴。例如參考第3B圖,如圖所示,晶粒錯位堆疊341,342,343,344安裝於基板317上,該基板317在堆疊安裝側具有電連接位置(諸如接合墊)372。此例中的所有晶粒具有例如周緣墊348,其沿晶粒之邊緣,配置於互接緣。堆疊中的每一晶粒可相對於下方之晶粒位移,露出墊區域之至少一部分(於圖示例子中露出墊的全部)。如圖示,第一互接液滴314將第一晶粒341上之晶粒墊348連接至基板317中的接合墊372。為形成液滴,使工具朝向第一目標接合墊,並將材料團塊調配於接合墊。接著,當材料團塊仍與工具梢部接觸時,該工具移動,首先向上,側面離開第一目標,接著向下,側面朝晶粒墊348(如斷箭所示),以成弧形朝第二墊拉出材料“尾部”。可同樣形成第二及後續液滴以連接連續晶粒上之墊,形成晶粒對晶粒互連。
根據第4A、4B及4C圖所示發明實施例,以鋸齒組態成層錯位堆疊之晶粒總成安裝及電連接於支撐。於此例子中,包含各具有四個錯位堆疊晶粒之二層之堆疊晶粒總成428安裝於支撐(諸如封裝基板)447。於本例子中,下層包含晶粒441,442,443,444;且上層包含晶粒445,446,447,448。且各晶粒之後側層疊晶粒附接膜(分別為431,432,433,434,435,436,437,438)。互接晶粒墊(例如548;648)配置於接近各晶粒之互接緣之晶粒緣。互接材料之引線404形成於第一層之互接面,其接觸互接晶粒墊(例如548)以形成晶粒對晶粒互連,並接觸支撐上第一行之接合墊472,以形成層對支撐電連接。互連材料之柱502形成接觸支撐上第二行之接合墊474;且互連材料之引線504形成於第二層之互連面上方,接觸互接晶粒墊(例如648)以形成晶粒對晶粒互連,並接觸柱502,以形成層對支撐電連接。
基板477於面對堆疊安裝面之表面包含焊墊476,其用來將總成二級電連接(例如作為焊墊格柵陣列或球形格柵陣列或標記陣列)於裝置中的下層電路(未顯示於此等圖中),其中佈置總成供使用。接合墊472,474及焊墊476連接於圖案化之導電層,並於基板中為一或更多介電層所分隔,且基板中之圖案化導電層藉貫穿單一或多數介電層之通孔連接。
如第4A、4B及4C圖所示,用來建構以鋸齒組態成層錯位堆疊之晶粒總成安裝及電連接於支撐之程序例子之步驟顯示於第5A、5B及5C圖;第6A、6B及6C圖;第7A、7B及7C圖;第8A、8B及8C圖;以及第9A、9B及9C圖。以下係此種程序之說明。
用於晶粒陣列之習知半導體電路形成於半導體晶圓之主動側(前側)。通常藉由背部硏磨薄化,且晶粒附接膜安裝於薄化晶圓之背側。接著,晶粒藉由沿陣列中之晶粒間之切割道切割(鋸割)單一化。
使用諸如拾取及安置工具,將單一化的晶粒堆疊於錯位配置中。於在此顯示之例子中,將構成第一層420之第一錯位晶粒堆疊(於此例子中為四個)安裝於基板477之堆疊安裝表面。第一層定位成最下方晶粒441之晶粒附接側璧對齊(鄰接或局部重疊於)基板上第一接合墊行中的接合墊472。此後,該總成塗以介電塗層544。介電塗層之材料可為多種材料的任一種,並可使用適於特定材料之多種技術之任一種形成。適當的材料包含有機聚合物,且特別適當之材料包含聚對二甲苯,其藉由蒸汽形式之先驅分子之原位聚合物化形成。塗層覆蓋在塗佈期間暴露於材料之所有表面,包含待形成電連接之區域。因此,開口例如藉由選擇性雷射磨滅形成於選擇區域上方。例如,開口545透過塗層形成以露出基板上第一行之互連晶粒墊(例如548)及接合墊(例如472)。完成之架構顯示於第5A圖中,並局部放大於第5B,5C圖。
此後,藉由形成與互連晶粒墊以及與接合墊472接觸之引線404,形成於第一層420中晶粒之互連以及第一層與基板之連接。於第6A圖中顯示並於第6B,6C圖中局部放大顯示完成之建構。介電塗層用來將可藉導電引線接觸,惟不欲電接觸之特點絕緣,此等特點像是邊緣,晶粒墊沿其安置,以及相鄰晶粒緣和側壁。如以上所述,導電材料包含可以流動形式沉積且此後硬化或容許硬化以形成導體之材料。導電材料可為可固化材料,且可沉積成未固化或局部固化狀態;且該材料可於沉積後之中間階段局部或額外固化,並可在沉積完成時完全固化。適當的互連材料包含充填粒子形式之導電材料之聚合物,就像例如金屬充填聚合物,其例如包含金屬充填環氧樹脂、金屬充填熱固化聚合物、金屬充填熱塑聚合物以及導電油墨。
互接材料可藉由適於特定材料之任何技術沉積。於某些實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網版印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈動調配例如成滴狀。在調配後,固化材料以完成互連。
此後,將構成第二層422之第二錯位晶粒堆疊(於本例子中為四個)安裝於第一層420之上表面。於此例子中,第二層定位成最下方晶粒445之晶粒附接側壁懸於第一層上,且相對於基板上第二接合墊行中之接合墊474垂直對齊。此後,所形成之總成塗以第二介電塗層644。第二介電塗層之材料可為多種材料之任一種,且可使用適於特定材料之多種技術之任一種形成。第二塗層材料可與第一塗層材料相同或不同。適當材料包含有機聚合物,且特別是適當材料包含聚對二甲苯,其藉由蒸汽形式之先驅分子之原位聚合物化形成。塗層覆蓋在塗佈期間暴露於材料之所有表面,包含待形成電連接之區域。因此,開口例如藉由選擇性雷射磨滅形成於選擇區域上方。例如,開口645透過塗層形成以露出基板上第一行之互連晶粒墊(例如648)及接合墊(例如474)。完成之架構顯示於第7A圖中,並局部放大於第7B,7C圖。
此後,導電材料之柱502形成與基板上第二行中之接合墊474接觸。完成之架構顯示於第8A圖中,並局部放大於第8B,8C圖。如以上所述,導電材料包含可以可流動方式沉積,且此後硬化或容許硬化以形成導體之材料。導電材料可為可固化材料,且可沉積成未固化或局部固化狀態;且該材料可於沉積後之中間階段局部或額外固化,並可在沉積完成時完全固化。適當的導電材料包含充填粒子形式之導電材料之聚合物,就像例如金屬充填聚合物,其例如包含金屬充填環氧樹脂、金屬充填熱固化聚合物、金屬充填熱塑聚合物以及導電油墨。在調配時及最後固化以前,選擇具有適於維持柱高度及一般形狀之適當材料。於特定實施例中,柱具有大致錐形,範圍約在190-310μm間之高度,且基底半徑範圍例如約在160-180μm間。依材料之性質而定,可製成具有較大的高度對半徑比例。在沉積及固化程序期間可形成如第8B圖中512所示,圍繞基底之環氧樹脂“印流”;惟於某些實施例中,這可能不是理想的特點。
用於導電柱之適當材料之特定例子包含OrmetCircuits公司以“800,700,500,400,200系列油墨”銷售之導電糊。此等材料包含5-15 wt%之環氧樹脂混合物以及高達5 wt%之丁基乙甘醇;其餘包含各種Cu,Bi,Sn及Ag粒子之比率。
用於導電柱之適當材料之其他特定例子包含Lord公司以諸如“Thermoset MD-141”“晶粒附接黏著劑”銷售之導電糊。此等材料包含約10 wt%之酚醛清漆樹脂、約5 wt%之乙醇乙醚、約5 wt%之環氧樹脂以及約80 wt%之銀。
用於柱之互接材料可藉由適於特定材料及柱形狀之任何技術沉積。於某些實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網版印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈動調配例如成滴狀。在調配後,固化柱材料以完成柱之機械完整性。
此後,藉由形成與互連晶粒墊以及與柱502接觸之引線504,形成於第二層422中晶粒之互連以及第二層與基板之連接(藉柱502)。於第9A圖中顯示並於第9B,9C圖中局部放大顯示完成之建構。介電塗層用來將可藉導電引線接觸,惟不欲電接觸之特點絕緣,此等特點像是邊緣,晶粒墊沿其安置,以及相鄰晶粒緣和側壁。如以上所述,導電材料包含可以流動形式沉積且此後硬化或容許硬化以形成導體之材料。導電材料可為可固化材料,且可沉積成未固化或局部固化狀態;且該材料可於沉積後之中間階段局部或額外固化,並可在沉積完成時完全固化。適當的互連材料包含充填粒子形式之導電材料之聚合物,就像例如金屬充填聚合物,其例如包含金屬充填環氧樹脂、金屬充填熱固化聚合物、金屬充填熱塑聚合物以及導電油墨。在調配之後,最後固化以前,選擇具有適於維持其跨晶粒445之側壁與柱梢間之間隙之形狀之適當流變性質的適當材料。
互接材料可藉由適於特定材料之任何技術沉積。於某些實施例中,材料可使用噴嘴或針調配或噴灑成霧,或網版印刷或噴墨印刷;材料可透過噴射或噴嘴連續調配或脈動調配例如成滴狀。
第10A及10B圖係顯示於第一層420中進行晶粒對晶粒互連及第一層420對基板上接合墊472之導電引線404之部分視圖。
第11A及11B圖係顯示於第二層422中進行晶粒對晶粒互連及第二層422對基板上柱502之連接之導電引線504之部分視圖。
第12A、12B、12C圖係顯示於第二層422中進行晶粒對晶粒互連及第一層422對基板上接合墊474上之柱502之導電引線504之形成步驟之部分視圖。
其他實施例在本發明之範圍內。
例如,圖式顯示總成,其中,成層晶粒堆疊(於此等例子中,上錯位晶粒堆疊)隆起於支撐上方;且佈設柱以用來電連接隆起之錯位晶粒堆疊於支撐上之接合墊。於所考慮其他實施例中,佈設柱以用來電連接隆起之晶粒或晶粒堆疊(錯位或非錯位)於支撐上之接合墊。且例如,圖式顯示總成,其中,下錯位晶粒堆疊位於上堆疊與支撐間。特別是,於圖示之例子中,下錯位晶粒堆疊安裝於支撐,且上堆疊安裝於下堆疊,俾上堆疊之隆起藉下堆疊之高度強施於基板表面(或下堆疊之高度)上方。於所考慮其他實施例中,上堆疊可安裝在異於下堆疊之某些特點上方,就像例如下晶粒或下非錯位晶粒堆疊或封裝上方。
例如,圖示之鋸齒狀成層錯位晶粒堆疊總成亦具有兩層(下層及上層),且各層如圖示具有四個晶粒。考慮兩層以上之總成,並考慮具有其他數目之晶粒之層。例如,一或更多的額外層可被堆疊在第二層上。例如,一或更多層可具有四個以上或以下之晶粒,且於某些實施例中,一或更多層可例如具有八個晶粒。
如圖所示,上及下層中之晶粒亦具有相同長度。此種情況可例如適用於所有晶粒具有相同類型或相同功能情況下。成層堆疊之每一者例如包含同型之記憶晶粒。考慮其他晶粒型。例如,具有不同功能之晶粒可包含於一層內;或者,例如,一層中之晶粒可具有相同功能,而其他層中之晶粒則具有一或更多不同功能。結果,於所考慮之某些實施例中,晶粒可大小不同;或一層中之晶粒可大小相同,而其他層中之晶粒則具有不同尺寸。
於如圖示例子中,上層中之最下方晶粒之互接緣亦向外延伸超過下特點之下緣(亦即於圖示之例子中,超過下層中最上方晶粒之下晶粒緣)。於另一考慮之例子中,上堆疊中之互連緣可垂直對齊或可從下特點之下緣向內。
於例如圖示例子中,介電塗層亦自堆疊中所有晶粒上之互連墊移除。這容許所有墊接觸後續形成之引線。可能較佳係形成僅與墊之選擇者連接之電連接。如於以上參考且併提於此供參考之美國申請案12/124,077中所圖示及討論,開口可形成於任何晶粒中所選墊的上方,或對應堆疊中連續晶粒上之墊選擇,留下為介電塗層所覆蓋且對電連接無用之墊。且,例如,塗層如說明形成於多數相中,各相出現在層之每一者建構後。於某些所考慮之實施例中,塗層應用於形成兩個(或更多)以後之單一相中。在上層位於下層上方俾下層中之互連晶粒墊可便於用來移除(例如藉由雷射磨滅)情況下,這可能特別理想。
於例如圖示例子中,說明在二調配操作中進行柱之形成,及連接隆起(上)晶粒或晶粒堆疊於柱之引線之形成。於某些實施例中,可於連續操作中,藉由調配及調配工具之適當控制,形成各柱及對應引線。
10...錯位堆疊晶粒
141...最下方晶粒
143,144,146...晶粒
142,173...行
145...開口
147...最上方晶粒
148...互連墊
149...前晶粒緣
17,217,320,447...支撐
171...晶粒安裝表面
172...接合位置
174...引線
210...第一模組單元(第一層)
212...第二模組單元(第二層)
214,224...互連
220...第二層
244...導電層
272...接合墊
304...液滴
317...基板
328...接觸
341,342,343,344...晶粒
348...周緣墊
372...接合墊
404...引線
420...第一層
428...堆疊晶粒總成
431,432,433,434,435,436,437,438...晶粒附接膜
441,442,443,444...晶粒
445,446,447,448...晶粒
472,474...接合墊
476...焊墊
477...基板
502...柱
504...引線
544,644...介電塗層
545,645...開口
548,648...互連晶粒墊
第1A及1B圖係以俯視圖(第1A圖)及剖視圖(第1B圖)顯示安裝於支撐上之錯位晶粒堆疊之圖式。
第1C圖係如第1B圖剖視顯示安裝於支撐上之錯位晶片堆疊之圖式,其中晶粒以晶粒對晶粒方式電連接,且晶粒堆疊電連接於支撐。
第2A及2B圖係剖視顯示以鋸齒組態相互安裝之二堆疊晶粒單元之圖式。
第3A圖係顯示可固化互連材料之自由立起液滴之圖式,第3B圖係顯示於晶粒與支撐間形成電連接之步驟之圖式。
第4A、4B及4C圖係剖視顯示以鋸齒組態成層錯位堆疊之晶粒總成,其安裝及電連接於支撐。
第5A、5B及5C圖;第6A、6B及6C圖;第7A、7B及7C圖;第8A、8B及8C圖;以及第9A、9B及9C圖係如第4A、4B及4C圖剖視顯示以鋸齒組態建構成層錯位堆疊之晶粒總成之步驟的圖式,第4B,5B,6B,7B,8B及9B圖分別係如於4A,5A,6A,7A,8A及9A圖中B所示部分剖視之圖式,且第4C,5C,6C,7C,8C及9C圖分別係如於4A,5A,6A,7A,8A及9A圖中C所示部分剖視之圖式。
第10A圖係安裝於支撐上之成層錯位堆疊之晶粒總成一部分之正視圖,其顯示下層對支撐之電連接。
第10B圖係安裝於支撐上之成層錯位堆疊之晶粒總成一部分之俯視圖,其顯示下層對支撐之電連接。
第11A圖係安裝於支撐上之成層錯位堆疊之晶粒總成一部分之正視圖,其顯示上層對支撐之電連接。
第11B圖係安裝於支撐上之成層錯位堆疊之晶粒總成一部分之俯視圖,其顯示上層對支撐之電連接。
第12A圖係安裝於支撐上之成層錯位堆疊之晶粒總成一部分之正視圖,其顯示形成上層對支撐之電連接之步驟。
第12B圖係如第12A圖安裝於支撐上之成層錯位堆疊之晶粒總成一部分之俯視圖,其顯示上層對支撐之電連接。
第12C圖係如第12A圖安裝於支撐上之成層錯位堆疊之晶粒總成一部分之俯視圖,其顯示形成上層對支撐之電連接之步驟。
404...引線
428...堆疊晶粒總成
472,474...接合墊
476...焊墊
477...基板
502...柱
504...引線

Claims (31)

  1. 一種半導體總成,其包括安裝並隆起於支撐上方之隆起晶粒,該隆起晶粒於其前側具有複數個互連墊,該支撐具有第一導電材料的柱,每一個柱設置在該支撐的安裝側上的個別接合墊上,其中,藉由第二導電材料的引線,該隆起晶粒電連接於該支撐,每一引線分別接觸該複數個互連墊中的至少兩個互連墊以及對應的該接合墊上之對應的該柱,其中該第二導電材料包括於聚合物基質中之粒子形式之導電材料。
  2. 如申請專利範圍第1項之總成,其中,該第一導電材料及該第二導電材料包括相同材料。
  3. 如申請專利範圍第1項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括部分經固化材料。
  4. 如申請專利範圍第1項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括可固化材料。
  5. 如申請專利範圍第1項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括充填金屬之聚合物。
  6. 如申請專利範圍第5項之總成,其中,該充填金屬之聚合物包括充填金屬之環氧樹脂。
  7. 如申請專利範圍第5項之總成,其中,該充填金屬之聚合物包括充填金屬之熱固聚合物。
  8. 如申請專利範圍第5項之總成,其中,該充填金屬之聚合物包括充填金屬之熱塑聚合物。
  9. 如申請專利範圍第1項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括於載體中之粒子形式之導電材料。
  10. 如申請專利範圍第9項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括導電墨。
  11. 一種半導體總成,其包括安裝於支撐上方之晶粒堆疊之複數個晶粒,至少該複數個晶粒中之第一晶粒隆起於該支撐上,該第一晶粒於其前側具有互連墊,該支撐於其安裝側接合墊上具有第一導電材料的柱,其中,藉由第二導電材料的引線,該第一晶粒電連接於該支撐,該第二導電材料的引線使該晶粒上的該互連墊接觸該接合墊上的該柱,其中該第二導電材料包括於聚合物基質中之粒子形式之導電材料,其中,藉由第三導電材料的引線,至少該複數個晶粒中之第二晶粒電連接至該第一晶粒,該第三導電材料的引線使該第一晶粒上的該互連墊接觸該第二晶粒上的互連墊。
  12. 如申請專利範圍第11項之總成,其中,該第一導電材料及該第二導電材料包括相同材料。
  13. 如申請專利範圍第11項之總成,其中,該第三導電材料及該第二導電材料包括相同材料。
  14. 如申請專利範圍第11項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括部分經固化材料。
  15. 如申請專利範圍第11項之總成,其中,該第一導 電材料及該第二導電材料之至少一者包括可固化材料。
  16. 如申請專利範圍第11項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括充填金屬之聚合物。
  17. 如申請專利範圍第16項之總成,其中,該充填金屬之聚合物包括充填金屬之環氧樹脂。
  18. 如申請專利範圍第16項之總成,其中,該充填金屬之聚合物包括充填金屬之熱固聚合物。
  19. 如申請專利範圍第16項之總成,其中,該充填金屬之聚合物包括充填金屬之熱塑聚合物。
  20. 如申請專利範圍第11項之總成,其中,該第一導電材料及該第二導電材料之至少一者包括於載體中之粒子形式之導電材料。
  21. 如申請專利範圍第20項之總成,其中,該導電材料包括導電墨。
  22. 一種半導體總成,其包括安裝於並隆起於支撐上方之上晶粒堆疊中之複數個晶粒,該上晶粒堆疊中之至少第一晶粒於其前側具有互連墊,該支撐於其安裝側接合墊上具有第一導電材料的柱,其中,藉由第二導電材料的引線,該上晶粒堆疊中之該第一晶粒電連接於該支撐,該第二導電材料的引線使該第一晶粒上的該互連墊接觸該接合墊上的該柱,其中該第二導電材料包括於聚合物基質中之粒子形式之導電材料,其中,藉由第三導電材料的引線,至少該上晶粒堆疊中之第二晶粒電連接至該第一晶粒,該 第三導電材料的引線使該第一晶粒上的該互連墊接觸該第二晶粒上的互連墊。
  23. 如申請專利範圍第22項之半導體總成,進一步包括位於該支撐與該上晶粒堆疊間之下晶粒。
  24. 如申請專利範圍第22項之半導體總成,進一步包括位於該支撐與該上晶粒堆疊間之下晶粒堆疊。
  25. 如申請專利範圍第24項之半導體總成,其中,該下晶粒堆疊包括成層錯位堆疊的晶粒總成,且其中,該下晶粒堆疊中之晶粒以晶粒對晶粒方式電互連,且該下晶粒堆疊藉使該下晶粒堆疊之該晶粒上的互連墊及該支撐上之一組接合墊接觸之導電材料之引線電連接於該支撐。
  26. 如申請專利範圍第22項之半導體總成,進一步包括位於該支撐與該上晶粒堆疊間之半導體封裝。
  27. 如申請專利範圍第22項之半導體總成,其中,該上晶粒堆疊包括成層錯位堆疊的晶粒總成,其中,該上晶粒堆疊中之該晶粒之互連緣面對第一方向,且該互連晶粒墊對準該柱。
  28. 一種晶粒堆疊總成,包括:以鋸齒組態堆疊的成層錯位的第一晶粒堆疊及第二晶粒堆疊;支撐,具有第一組接合墊及第二組接合墊;以及複數個柱,突出於該第二組接合墊上方並與該第二組接合墊電連接,其中藉由導電材料的第一引線,該第一晶粒堆疊中之晶粒以晶粒對晶粒方式電互連,該第一引線接觸該第一晶粒堆疊的晶粒上的互連墊,而且導電材料的該第一引線將該第 一晶粒堆疊中之該晶粒與該第一組接合墊電連接;並且藉由導電材料的第二引線,該第二晶粒堆疊中之晶粒以晶粒對晶粒方式電互連,該第二引線接觸該第二晶粒堆疊的晶粒上的互連墊,而且導電材料的該第二引線將該第二晶粒堆疊中之該晶粒與該複數個柱電連接,其中該導電材料包括於聚合物基質中之粒子形式之導電材料。
  29. 如申請專利範圍第28項之晶粒堆疊總成,其中,該第一晶粒堆疊中之該晶粒之互連緣面對第一方向,且該第二晶粒堆疊中之該晶粒之互連緣面對異於第一方向之第二方向。
  30. 如申請專利範圍第28項之晶粒堆疊總成,其中,該第一方向與該第二方向相對。
  31. 如申請專利範圍第28項之晶粒堆疊總成,其中,該第一方向與該第二方向正交。
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Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
TWI515863B (zh) * 2008-03-12 2016-01-01 英維瑟斯公司 載體安裝式電氣互連晶粒組成件
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US8829677B2 (en) 2010-10-14 2014-09-09 Invensas Corporation Semiconductor die having fine pitch electrical interconnects
US8765031B2 (en) 2009-08-13 2014-07-01 Align Technology, Inc. Method of forming a dental appliance
KR101563630B1 (ko) * 2009-09-17 2015-10-28 에스케이하이닉스 주식회사 반도체 패키지
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
JP5512292B2 (ja) * 2010-01-08 2014-06-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9211166B2 (en) 2010-04-30 2015-12-15 Align Technology, Inc. Individualized orthodontic treatment index
US9241774B2 (en) 2010-04-30 2016-01-26 Align Technology, Inc. Patterned dental positioning appliance
US8587088B2 (en) 2011-02-17 2013-11-19 Apple Inc. Side-mounted controller and methods for making the same
US9403238B2 (en) 2011-09-21 2016-08-02 Align Technology, Inc. Laser cutting
US9196588B2 (en) * 2011-11-04 2015-11-24 Invensas Corporation EMI shield
US9375300B2 (en) 2012-02-02 2016-06-28 Align Technology, Inc. Identifying forces on a tooth
US9220580B2 (en) 2012-03-01 2015-12-29 Align Technology, Inc. Determining a dental treatment difficulty
US20130234330A1 (en) * 2012-03-08 2013-09-12 Infineon Technologies Ag Semiconductor Packages and Methods of Formation Thereof
US9414897B2 (en) 2012-05-22 2016-08-16 Align Technology, Inc. Adjustment of tooth position in a virtual dental model
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
CN104769714B (zh) 2013-02-26 2018-10-26 晟碟信息科技(上海)有限公司 包括交替形成台阶的半导体裸芯堆叠的半导体器件
KR20140109134A (ko) * 2013-03-05 2014-09-15 삼성전자주식회사 멀티-채널을 갖는 반도체 패키지 및 관련된 전자 장치
CN103474421B (zh) * 2013-08-30 2016-10-12 晟碟信息科技(上海)有限公司 高产量半导体装置
US10449016B2 (en) 2014-09-19 2019-10-22 Align Technology, Inc. Arch adjustment appliance
US9610141B2 (en) 2014-09-19 2017-04-04 Align Technology, Inc. Arch expanding appliance
US9744001B2 (en) 2014-11-13 2017-08-29 Align Technology, Inc. Dental appliance with cavity for an unerupted or erupting tooth
US10504386B2 (en) 2015-01-27 2019-12-10 Align Technology, Inc. Training method and system for oral-cavity-imaging-and-modeling equipment
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US11554000B2 (en) 2015-11-12 2023-01-17 Align Technology, Inc. Dental attachment formation structure
US11931222B2 (en) 2015-11-12 2024-03-19 Align Technology, Inc. Dental attachment formation structures
US11103330B2 (en) 2015-12-09 2021-08-31 Align Technology, Inc. Dental attachment placement structure
US11596502B2 (en) 2015-12-09 2023-03-07 Align Technology, Inc. Dental attachment placement structure
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
WO2017218951A1 (en) 2016-06-17 2017-12-21 Align Technology, Inc. Orthodontic appliance performance monitor
EP3471599A4 (en) 2016-06-17 2020-01-08 Align Technology, Inc. INTRAORAL DEVICES WITH SENSOR
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
KR102443088B1 (ko) 2016-07-27 2022-09-14 얼라인 테크널러지, 인크. 치아 진단 기능이 있는 구강 내 스캐너
CN113648088B (zh) 2016-11-04 2023-08-22 阿莱恩技术有限公司 用于牙齿图像的方法和装置
US11273011B2 (en) 2016-12-02 2022-03-15 Align Technology, Inc. Palatal expanders and methods of expanding a palate
US11376101B2 (en) 2016-12-02 2022-07-05 Align Technology, Inc. Force control, stop mechanism, regulating structure of removable arch adjustment appliance
WO2018102811A1 (en) 2016-12-02 2018-06-07 Align Technology, Inc. Methods and apparatuses for customizing rapid palatal expanders using digital models
US11026831B2 (en) 2016-12-02 2021-06-08 Align Technology, Inc. Dental appliance features for speech enhancement
US10548700B2 (en) 2016-12-16 2020-02-04 Align Technology, Inc. Dental appliance etch template
US10779718B2 (en) 2017-02-13 2020-09-22 Align Technology, Inc. Cheek retractor and mobile device holder
US10147705B2 (en) * 2017-02-21 2018-12-04 Micron Technology, Inc. Stacked semiconductor die assemblies with die substrate extensions
WO2018183358A1 (en) 2017-03-27 2018-10-04 Align Technology, Inc. Apparatuses and methods assisting in dental therapies
US10613515B2 (en) 2017-03-31 2020-04-07 Align Technology, Inc. Orthodontic appliances including at least partially un-erupted teeth and method of forming them
CN108878398B (zh) * 2017-05-16 2020-07-21 晟碟半导体(上海)有限公司 包括导电凸块互连的半导体器件
KR20180130043A (ko) * 2017-05-25 2018-12-06 에스케이하이닉스 주식회사 칩 스택들을 가지는 반도체 패키지
US11045283B2 (en) 2017-06-09 2021-06-29 Align Technology, Inc. Palatal expander with skeletal anchorage devices
US11996181B2 (en) 2017-06-16 2024-05-28 Align Technology, Inc. Automatic detection of tooth type and eruption status
US10639134B2 (en) 2017-06-26 2020-05-05 Align Technology, Inc. Biosensor performance indicator for intraoral appliances
US10885521B2 (en) 2017-07-17 2021-01-05 Align Technology, Inc. Method and apparatuses for interactive ordering of dental aligners
US11419702B2 (en) 2017-07-21 2022-08-23 Align Technology, Inc. Palatal contour anchorage
CN116327391A (zh) 2017-07-27 2023-06-27 阿莱恩技术有限公司 用于通过光学相干断层扫描术来处理正畸矫正器的系统和方法
CN115462921A (zh) 2017-07-27 2022-12-13 阿莱恩技术有限公司 牙齿着色、透明度和上釉
WO2019035979A1 (en) 2017-08-15 2019-02-21 Align Technology, Inc. EVALUATION AND CALCULATION OF BUCCAL CORRIDOR
WO2019036677A1 (en) 2017-08-17 2019-02-21 Align Technology, Inc. SURVEILLANCE OF CONFORMITY OF DENTAL DEVICE
US10813720B2 (en) 2017-10-05 2020-10-27 Align Technology, Inc. Interproximal reduction templates
EP3700458B1 (en) 2017-10-27 2023-06-07 Align Technology, Inc. Alternative bite adjustment structures
CN111295153B (zh) 2017-10-31 2023-06-16 阿莱恩技术有限公司 具有选择性牙合负荷和受控牙尖交错的牙科器具
US11096763B2 (en) 2017-11-01 2021-08-24 Align Technology, Inc. Automatic treatment planning
WO2019100022A1 (en) 2017-11-17 2019-05-23 Align Technology, Inc. Orthodontic retainers
US11219506B2 (en) 2017-11-30 2022-01-11 Align Technology, Inc. Sensors for monitoring oral appliances
WO2019118876A1 (en) 2017-12-15 2019-06-20 Align Technology, Inc. Closed loop adaptive orthodontic treatment methods and apparatuses
US10980613B2 (en) 2017-12-29 2021-04-20 Align Technology, Inc. Augmented reality enhancements for dental practitioners
KR20200115580A (ko) 2018-01-26 2020-10-07 얼라인 테크널러지, 인크. 구강 내 진단 스캔 및 추적
US11937991B2 (en) 2018-03-27 2024-03-26 Align Technology, Inc. Dental attachment placement structure
WO2019200008A1 (en) 2018-04-11 2019-10-17 Align Technology, Inc. Releasable palatal expanders
US11024604B2 (en) * 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
KR20220067572A (ko) 2020-11-16 2022-05-25 삼성전자주식회사 메모리 패키지 및 이를 포함하는 저장 장치
US11942430B2 (en) 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
CN114220744A (zh) * 2021-11-24 2022-03-22 长江存储科技有限责任公司 芯片的封装方法及结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073803A (ja) * 2005-09-08 2007-03-22 Toshiba Corp 半導体装置及びその製造方法
US20090065948A1 (en) * 2007-09-06 2009-03-12 Micron Technology, Inc. Package structure for multiple die stack
TW200913208A (en) * 2007-06-11 2009-03-16 Vertical Circuits Inc Electrically interconnected stacked die assemblies
TW200921887A (en) * 2007-09-07 2009-05-16 Vertical Circuits Inc Electrical interconnect formed by pulsed dispense

Family Cites Families (192)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53147968A (en) * 1977-05-30 1978-12-23 Hitachi Ltd Thick film circuit board
US4323914A (en) * 1979-02-01 1982-04-06 International Business Machines Corporation Heat transfer structure for integrated circuit package
US4363076A (en) * 1980-12-29 1982-12-07 Honeywell Information Systems Inc. Integrated circuit package
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
JPS6149432A (ja) * 1984-08-18 1986-03-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5138438A (en) * 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
JPH063819B2 (ja) * 1989-04-17 1994-01-12 セイコーエプソン株式会社 半導体装置の実装構造および実装方法
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5311401A (en) * 1991-07-09 1994-05-10 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5218234A (en) * 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
US5331591A (en) * 1993-02-01 1994-07-19 At&T Bell Laboratories Electronic module including a programmable memory
FR2704690B1 (fr) 1993-04-27 1995-06-23 Thomson Csf Procédé d'encapsulation de pastilles semi-conductrices, dispositif obtenu par ce procédé et application à l'interconnexion de pastilles en trois dimensions.
US7073254B2 (en) 1993-11-16 2006-07-11 Formfactor, Inc. Method for mounting a plurality of spring contact elements
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
US6255726B1 (en) * 1994-06-23 2001-07-03 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5698895A (en) * 1994-06-23 1997-12-16 Cubic Memory, Inc. Silicon segment programming method and apparatus
US5891761A (en) * 1994-06-23 1999-04-06 Cubic Memory, Inc. Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US6228686B1 (en) * 1995-09-18 2001-05-08 Tessera, Inc. Method of fabricating a microelectronic assembly using sheets with gaps to define lead regions
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
US5616953A (en) * 1994-09-01 1997-04-01 Micron Technology, Inc. Lead frame surface finish enhancement
US5619476A (en) * 1994-10-21 1997-04-08 The Board Of Trustees Of The Leland Stanford Jr. Univ. Electrostatic ultrasonic transducer
US5466634A (en) * 1994-12-20 1995-11-14 International Business Machines Corporation Electronic modules with interconnected surface metallization layers and fabrication methods therefore
DE69621983T2 (de) * 1995-04-07 2002-11-21 Shinko Electric Industries Co., Ltd. Struktur und Verfahren zur Montage eines Halbleiterchips
US5721151A (en) * 1995-06-07 1998-02-24 Lsi Logic Corporation Method of fabricating a gate array integrated circuit including interconnectable macro-arrays
US5691248A (en) * 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges
US5648684A (en) * 1995-07-26 1997-07-15 International Business Machines Corporation Endcap chip with conductive, monolithic L-connect for multichip stack
US5538758A (en) * 1995-10-27 1996-07-23 Specialty Coating Systems, Inc. Method and apparatus for the deposition of parylene AF4 onto semiconductor wafers
JP3527350B2 (ja) * 1996-02-01 2004-05-17 株式会社ルネサステクノロジ 半導体装置
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5880530A (en) * 1996-03-29 1999-03-09 Intel Corporation Multiregion solder interconnection structure
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
JP3685585B2 (ja) * 1996-08-20 2005-08-17 三星電子株式会社 半導体のパッケージ構造
US6034438A (en) * 1996-10-18 2000-03-07 The Regents Of The University Of California L-connect routing of die surface pads to the die edge for stacking in a 3D array
US6962829B2 (en) * 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
KR100447313B1 (ko) * 1996-11-21 2004-09-07 가부시키가이샤 히타치세이사쿠쇼 반도체 장치 및 그 제조방법
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JP3779789B2 (ja) * 1997-01-31 2006-05-31 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2980046B2 (ja) * 1997-02-03 1999-11-22 日本電気株式会社 半導体装置の実装構造および実装方法
US5879965A (en) * 1997-06-19 1999-03-09 Micron Technology, Inc. Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
US6271598B1 (en) 1997-07-29 2001-08-07 Cubic Memory, Inc. Conductive epoxy flip-chip on chip
WO1999009599A2 (en) 1997-08-21 1999-02-25 Cubic Memory, Inc. Vertical interconnect process for silicon segments with dielectric isolation
US5888850A (en) * 1997-09-29 1999-03-30 International Business Machines Corporation Method for providing a protective coating and electronic package utilizing same
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6138349A (en) 1997-12-18 2000-10-31 Vlt Corporation Protective coating for an electronic device
US6315856B1 (en) * 1998-03-19 2001-11-13 Kabushiki Kaisha Toshiba Method of mounting electronic component
DE19833713C1 (de) * 1998-07-27 2000-05-04 Siemens Ag Verfahren zur Herstellung eines Verbundkörpers aus wenigstens zwei integrierten Schaltungen
JP3516592B2 (ja) * 1998-08-18 2004-04-05 沖電気工業株式会社 半導体装置およびその製造方法
US6153929A (en) * 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
US6084297A (en) * 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6175158B1 (en) * 1998-09-08 2001-01-16 Lucent Technologies Inc. Interposer for recessed flip-chip package
US6303977B1 (en) * 1998-12-03 2001-10-16 Texas Instruments Incorporated Fully hermetic semiconductor chip, including sealed edge sides
US6297657B1 (en) * 1999-01-11 2001-10-02 Wentworth Laboratories, Inc. Temperature compensated vertical pin probing device
EP1041624A1 (en) 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multilayer thin film device
US6326689B1 (en) * 1999-07-26 2001-12-04 Stmicroelectronics, Inc. Backside contact for touchchip
US6338980B1 (en) * 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
WO2001018864A1 (fr) * 1999-09-03 2001-03-15 Seiko Epson Corporation Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique
US6621155B1 (en) * 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
JP2001183415A (ja) * 1999-12-28 2001-07-06 Molex Inc ベアチップ用icソケット
JP3879351B2 (ja) 2000-01-27 2007-02-14 セイコーエプソン株式会社 半導体チップの製造方法
DE10004941A1 (de) * 2000-02-06 2001-08-09 Reimer Offen Temperierter Probennehmer für Flüssigkeiten
JP2001223323A (ja) 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
JP3960802B2 (ja) 2000-03-02 2007-08-15 マイクロチップス・インコーポレーテッド 化学物質およびデバイスを格納し、選択的に露出させるための微細加工されたデバイス
US6335224B1 (en) * 2000-05-16 2002-01-01 Sandia Corporation Protection of microelectronic devices during packaging
US6956283B1 (en) 2000-05-16 2005-10-18 Peterson Kenneth A Encapsulants for protecting MEMS devices during post-packaging release etch
US6384473B1 (en) * 2000-05-16 2002-05-07 Sandia Corporation Microelectronic device package with an integral window
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
JP4361670B2 (ja) * 2000-08-02 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体素子積層体、半導体素子積層体の製造方法、及び半導体装置
JP3377001B2 (ja) * 2000-08-31 2003-02-17 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3405456B2 (ja) 2000-09-11 2003-05-12 沖電気工業株式会社 半導体装置,半導体装置の製造方法,スタック型半導体装置及びスタック型半導体装置の製造方法
SG97938A1 (en) * 2000-09-21 2003-08-20 Micron Technology Inc Method to prevent die attach adhesive contamination in stacked chips
US6580165B1 (en) * 2000-11-16 2003-06-17 Fairchild Semiconductor Corporation Flip chip with solder pre-plated leadframe including locating holes
DE10103186B4 (de) * 2001-01-24 2007-01-18 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Halbleiter-Chip
US20020100600A1 (en) * 2001-01-26 2002-08-01 Albert Douglas M. Stackable microcircuit layer formed from a plastic encapsulated microcircuit and method of making the same
JP2002305286A (ja) * 2001-02-01 2002-10-18 Mitsubishi Electric Corp 半導体モジュールおよび電子部品
US6910268B2 (en) 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US7115986B2 (en) 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
WO2002096389A1 (en) * 2001-05-30 2002-12-05 Microchips, Inc. Conformal coated microchip reservoir devices
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US20030006493A1 (en) 2001-07-04 2003-01-09 Matsushita Electric Industrial Co., Ltd. Semiconductor device and manufacturing method thereof
JP2003023138A (ja) * 2001-07-10 2003-01-24 Toshiba Corp メモリチップ及びこれを用いたcocデバイス、並びに、これらの製造方法
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US20030038353A1 (en) * 2001-08-23 2003-02-27 Derderian James M. Assemblies including stacked semiconductor devices separated by discrete conductive elements therebetween, packages including the assemblies, and methods
US7518223B2 (en) 2001-08-24 2009-04-14 Micron Technology, Inc. Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
US20030038356A1 (en) * 2001-08-24 2003-02-27 Derderian James M Semiconductor devices including stacking spacers thereon, assemblies including the semiconductor devices, and methods
US6569709B2 (en) 2001-10-15 2003-05-27 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US6747348B2 (en) * 2001-10-16 2004-06-08 Micron Technology, Inc. Apparatus and method for leadless packaging of semiconductor devices
JP2003142518A (ja) 2001-11-02 2003-05-16 Nec Electronics Corp 半導体製造装置、半導体製造方法、半導体装置及び電子装置
US6611052B2 (en) * 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
US6627509B2 (en) * 2001-11-26 2003-09-30 Delaware Capital Formation, Inc. Surface flashover resistant capacitors and method for producing same
JP2003163324A (ja) 2001-11-27 2003-06-06 Nec Corp ユニット半導体装置及びその製造方法並びに3次元積層型半導体装置
US6750547B2 (en) * 2001-12-26 2004-06-15 Micron Technology, Inc. Multi-substrate microelectronic packages and methods for manufacture
TW544882B (en) * 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
US7190060B1 (en) 2002-01-09 2007-03-13 Bridge Semiconductor Corporation Three-dimensional stacked semiconductor package device with bent and flat leads and method of making same
US6607941B2 (en) * 2002-01-11 2003-08-19 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
US6802446B2 (en) * 2002-02-01 2004-10-12 Delphi Technologies, Inc. Conductive adhesive material with metallurgically-bonded conductive particles
KR100486832B1 (ko) 2002-02-06 2005-05-03 삼성전자주식회사 반도체 칩과 적층 칩 패키지 및 그 제조 방법
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
USD475981S1 (en) * 2002-03-29 2003-06-17 Mitsubishi Denki Kabushiki Kaisha Integrated circuits substrate
US7340181B1 (en) * 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
US6756252B2 (en) * 2002-07-17 2004-06-29 Texas Instrument Incorporated Multilayer laser trim interconnect method
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
JP4081666B2 (ja) 2002-09-24 2008-04-30 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
US6656827B1 (en) * 2002-10-17 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical performance enhanced wafer level chip scale package with ground
US6667543B1 (en) * 2002-10-29 2003-12-23 Motorola, Inc. Optical sensor package
US7268005B2 (en) 2002-10-30 2007-09-11 Finisar Corporation Apparatus and method for stacking laser bars for uniform facet coating
TWI227550B (en) 2002-10-30 2005-02-01 Sanyo Electric Co Semiconductor device manufacturing method
JP2004153130A (ja) 2002-10-31 2004-05-27 Olympus Corp 半導体装置及びその製造方法
JP2004158536A (ja) 2002-11-05 2004-06-03 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP4381675B2 (ja) 2002-11-21 2009-12-09 富士通株式会社 半導体装置及びその製造方法、該半導体装置に係る測定用治具
US6881610B2 (en) * 2003-01-02 2005-04-19 Intel Corporation Method and apparatus for preparing a plurality of dice in wafers
JP2004214548A (ja) 2003-01-08 2004-07-29 Mitsubishi Electric Corp 部品内蔵基板型モジュール、それを搭載した基板、部品内蔵基板型モジュールの製造方法、および部品内蔵基板型モジュールを搭載した基板の製造方法
US7035113B2 (en) * 2003-01-30 2006-04-25 Endicott Interconnect Technologies, Inc. Multi-chip electronic package having laminate carrier and method of making same
KR101186919B1 (ko) 2003-02-06 2012-10-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시장치의 제조 방법
KR100499289B1 (ko) 2003-02-07 2005-07-04 삼성전자주식회사 패턴 리드를 갖는 반도체 패키지 및 그 제조 방법
JP3772984B2 (ja) 2003-03-13 2006-05-10 セイコーエプソン株式会社 電子装置及びその製造方法、回路基板並びに電子機器
JP2004281538A (ja) 2003-03-13 2004-10-07 Seiko Epson Corp 電子装置及びその製造方法、回路基板並びに電子機器
TWI231023B (en) * 2003-05-27 2005-04-11 Ind Tech Res Inst Electronic packaging with three-dimensional stack and assembling method thereof
EP1636842B1 (en) 2003-06-03 2011-08-17 Casio Computer Co., Ltd. Stackable semiconductor device and method of manufacturing the same
JP2005005380A (ja) * 2003-06-10 2005-01-06 Sanyo Electric Co Ltd 半導体装置の製造方法
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
TWM243783U (en) * 2003-06-30 2004-09-11 Innolux Display Corp Structure of chip on glass
WO2005004195A2 (en) 2003-07-03 2005-01-13 Shellcase Ltd. Method and apparatus for packaging integrated circuit devices
JP3718205B2 (ja) 2003-07-04 2005-11-24 松下電器産業株式会社 チップ積層型半導体装置およびその製造方法
KR20050009036A (ko) 2003-07-15 2005-01-24 삼성전자주식회사 적층 패키지 및 그 제조 방법
US20050067694A1 (en) 2003-09-30 2005-03-31 Pon Florence R. Spacerless die stacking
SG120123A1 (en) 2003-09-30 2006-03-28 Micron Technology Inc Castellated chip-scale packages and methods for fabricating the same
US7064010B2 (en) 2003-10-20 2006-06-20 Micron Technology, Inc. Methods of coating and singulating wafers
US7064069B2 (en) 2003-10-21 2006-06-20 Micron Technology, Inc. Substrate thinning including planarization
JP2005197491A (ja) * 2004-01-08 2005-07-21 Matsushita Electric Ind Co Ltd 半導体装置
JP4198072B2 (ja) 2004-01-23 2008-12-17 シャープ株式会社 半導体装置、光学装置用モジュール及び半導体装置の製造方法
DE102004008135A1 (de) 2004-02-18 2005-09-22 Infineon Technologies Ag Halbleiterbauteil mit einem Stapel aus Halbleiterchips und Verfahren zur Herstellung desselben
JP3811160B2 (ja) 2004-03-09 2006-08-16 株式会社東芝 半導体装置
KR100890073B1 (ko) 2004-03-23 2009-03-24 텍사스 인스트루먼츠 인코포레이티드 수직으로 적층된 반도체 장치 및 그 제조 방법
US7095105B2 (en) 2004-03-23 2006-08-22 Texas Instruments Incorporated Vertically stacked semiconductor device
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7245021B2 (en) 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US20050251031A1 (en) 2004-05-06 2005-11-10 Scimed Life Systems, Inc. Apparatus and construction for intravascular device
US7239020B2 (en) 2004-05-06 2007-07-03 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Multi-mode integrated circuit structure
TWI236110B (en) 2004-06-25 2005-07-11 Advanced Semiconductor Eng Flip chip on leadframe package and method for manufacturing the same
JP2006019493A (ja) 2004-07-01 2006-01-19 Disco Abrasive Syst Ltd ウェーハの分割方法
DE102004039906A1 (de) 2004-08-18 2005-08-18 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauelements sowie ein elektronisches Bauelement mit mindestens zwei integrierten Bausteinen
CN100539135C (zh) 2004-09-08 2009-09-09 松下电器产业株式会社 立体电路装置、使用它的电子机器及其制造方法
TWI288448B (en) 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
US7566634B2 (en) 2004-09-24 2009-07-28 Interuniversitair Microelektronica Centrum (Imec) Method for chip singulation
US8324725B2 (en) 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
DE102004052921A1 (de) 2004-10-29 2006-05-11 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen
JP2006140294A (ja) 2004-11-11 2006-06-01 Fujitsu Ltd 半導体基板、半導体装置の製造方法及び半導体装置の試験方法
KR100626618B1 (ko) 2004-12-10 2006-09-25 삼성전자주식회사 반도체 칩 적층 패키지 및 제조 방법
US20060138626A1 (en) 2004-12-29 2006-06-29 Tessera, Inc. Microelectronic packages using a ceramic substrate having a window and a conductive surface region
US7326592B2 (en) 2005-04-04 2008-02-05 Infineon Technologies Ag Stacked die package
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7208345B2 (en) 2005-05-11 2007-04-24 Infineon Technologies Ag Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device
US20060267173A1 (en) 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US7351657B2 (en) 2005-06-10 2008-04-01 Honeywell International Inc. Method and apparatus for applying external coating to grid array packages for increased reliability and performance
JP2006351793A (ja) 2005-06-15 2006-12-28 Fujitsu Ltd 半導体装置
US7196262B2 (en) 2005-06-20 2007-03-27 Solyndra, Inc. Bifacial elongated solar cell devices
KR100629498B1 (ko) 2005-07-15 2006-09-28 삼성전자주식회사 마이크로 패키지, 멀티―스택 마이크로 패키지 및 이들의제조방법
JP2007035911A (ja) * 2005-07-27 2007-02-08 Seiko Epson Corp ボンディングパッドの製造方法、ボンディングパッド、及び電子デバイスの製造方法、電子デバイス
US7452743B2 (en) 2005-09-01 2008-11-18 Aptina Imaging Corporation Microelectronic imaging units and methods of manufacturing microelectronic imaging units at the wafer level
JP2007134486A (ja) 2005-11-10 2007-05-31 Toshiba Corp 積層型半導体装置及びその製造方法
US7981726B2 (en) 2005-12-12 2011-07-19 Intel Corporation Copper plating connection for multi-die stack in substrate package
US7408243B2 (en) 2005-12-14 2008-08-05 Honeywell International Inc. High temperature package flip-chip bonding to ceramic
US20070158807A1 (en) * 2005-12-29 2007-07-12 Daoqiang Lu Edge interconnects for die stacking
US20070158799A1 (en) 2005-12-29 2007-07-12 Chin-Tien Chiu Interconnected IC packages with vertical SMT pads
TWI284971B (en) 2006-01-26 2007-08-01 Siliconware Precision Industries Co Ltd Multichip stack structure
SG135074A1 (en) 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US8710675B2 (en) 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands
US7429521B2 (en) 2006-03-30 2008-09-30 Intel Corporation Capillary underfill of stacked wafers
US7732912B2 (en) 2006-08-11 2010-06-08 Tessera, Inc. Semiconductor chip packages and assemblies with chip carrier units
US7888185B2 (en) 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
JP2008071953A (ja) 2006-09-14 2008-03-27 Nec Electronics Corp 半導体装置
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
KR100813624B1 (ko) 2006-10-25 2008-03-17 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8154881B2 (en) 2006-11-13 2012-04-10 Telecommunication Systems, Inc. Radiation-shielded semiconductor assembly
US8242607B2 (en) * 2006-12-20 2012-08-14 Stats Chippac Ltd. Integrated circuit package system with offset stacked die and method of manufacture thereof
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US20080173792A1 (en) 2007-01-23 2008-07-24 Advanced Chip Engineering Technology Inc. Image sensor module and the method of the same
US20080180242A1 (en) 2007-01-29 2008-07-31 Cottingham Hugh V Micron-scale implantable transponder
US20080203566A1 (en) 2007-02-27 2008-08-28 Chao-Yuan Su Stress buffer layer for packaging process
US7638869B2 (en) 2007-03-28 2009-12-29 Qimonda Ag Semiconductor device
KR100914977B1 (ko) 2007-06-18 2009-09-02 주식회사 하이닉스반도체 스택 패키지의 제조 방법
JP5049684B2 (ja) * 2007-07-20 2012-10-17 新光電気工業株式会社 積層型半導体装置及びその製造方法
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
EP2186131A2 (en) 2007-08-03 2010-05-19 Tessera Technologies Hungary Kft. Stack packages using reconstituted wafers
WO2009052150A1 (en) 2007-10-18 2009-04-23 Vertical Circuits, Inc. Chip scale stacked die package
TWI515863B (zh) 2008-03-12 2016-01-01 英維瑟斯公司 載體安裝式電氣互連晶粒組成件
WO2009154761A1 (en) 2008-06-16 2009-12-23 Tessera Research Llc Stacking of wafer-level chip scale packages having edge contacts

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073803A (ja) * 2005-09-08 2007-03-22 Toshiba Corp 半導体装置及びその製造方法
TW200913208A (en) * 2007-06-11 2009-03-16 Vertical Circuits Inc Electrically interconnected stacked die assemblies
US20090065948A1 (en) * 2007-09-06 2009-03-12 Micron Technology, Inc. Package structure for multiple die stack
TW200921887A (en) * 2007-09-07 2009-05-16 Vertical Circuits Inc Electrical interconnect formed by pulsed dispense

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