Nothing Special   »   [go: up one dir, main page]

TW202336970A - 電子封裝件及其製法 - Google Patents

電子封裝件及其製法 Download PDF

Info

Publication number
TW202336970A
TW202336970A TW111107998A TW111107998A TW202336970A TW 202336970 A TW202336970 A TW 202336970A TW 111107998 A TW111107998 A TW 111107998A TW 111107998 A TW111107998 A TW 111107998A TW 202336970 A TW202336970 A TW 202336970A
Authority
TW
Taiwan
Prior art keywords
electronic
layer
component
electronic package
wiring structure
Prior art date
Application number
TW111107998A
Other languages
English (en)
Other versions
TWI818458B (zh
Inventor
卜昭強
何祈慶
符毅民
王愉博
劉帥麟
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW111107998A priority Critical patent/TWI818458B/zh
Priority to CN202210246848.7A priority patent/CN116759410A/zh
Priority to US17/740,796 priority patent/US12176291B2/en
Publication of TW202336970A publication Critical patent/TW202336970A/zh
Application granted granted Critical
Publication of TWI818458B publication Critical patent/TWI818458B/zh
Priority to US18/916,941 priority patent/US20250038113A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381—Crossover interconnections, e.g. bridge stepovers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種電子封裝件，係於承載組件之佈線結構上配置一晶片封裝模組、具有複數接點之電子元件、以及電子連接器，以藉由該電子元件及電子連接器通訊連接該晶片封裝模組，進而提升訊號傳輸速度。

Description

電子封裝件及其製法
本發明係有關一種半導體裝置，尤指一種具電子連接器之電子封裝件及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂開發出不同的立體封裝技術，以將不同功能之積體電路整合於單一封裝結構，例如將不同功用之電子元件(如：記憶體、中央處理器、繪圖處理器、影像應用處理器等)，藉由堆疊設計達到系統的整合，以應用於輕薄型電子產品。
圖1係為習知半導體封裝件1之剖面示意圖。該半導體封裝件1係包括：一基板結構14及一設於該基板結構14上之晶片封裝模組1a，其中該晶片封裝模組1a係包含一第一封裝膠體15、一嵌埋於該第一封裝膠體15中之第一半導體晶片11、一設於該第一封裝膠體15相對兩側之線路結構10與複數導電元件17、複數嵌埋於該第一封裝膠體15中以電性連接該線路結構10與導電元件17之導電柱13、複數設於該線路結構10 上之第二半導體晶片12以及一包覆該第二半導體晶片12之第二封裝膠體16，以令該導電元件17係接置於該基板結構14上。另外，該基板結構14上側可配置一散熱件18，並於該基板結構14下側形成複數銲球19，以供接合一電路板(圖略)。
惟，習知半導體封裝件1僅配置一個晶片封裝模組1a，故於該電路板上，多個晶片封裝模組1a之間的通訊僅能依靠該基板結構14進行電性傳輸，致使傳輸速度相當緩慢，尤其是，當該半導體封裝件1應用於高資料速率、逐漸增加的頻寬及逐漸降低時延等需求的人工智慧(artificial intelligence，簡稱AI)相關的電子產品時，更將凸顯該半導體封裝件1之不適用。
再者，隨著包含高性能計算(high-performance computing，簡稱HPC)元件的半導體封裝件1的封裝尺寸需要增大之情況下，各該晶片封裝模組1a之間的通訊更難以符合運作需求。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種電子封裝件，係包括：承載組件，係具有佈線結構；晶片封裝模組，係設於該承載組件上並電性連接該佈線結構；具有複數接點之電子元件，係設於該承載組件上並電性連接該佈線結構，以接收該晶片封裝模組之電性訊號；以及 電子連接器，係設於該承載組件上並電性連接該佈線結構，以接收該電子元件之電性訊號。
本發明亦提供一種電子封裝件之製法，係包括：提供一具有佈線結構之承載組件；以及將晶片封裝模組、具有複數接點之電子元件及電子連接器設於該承載組件上，使該晶片封裝模組、電子元件及電子連接器電性連接該佈線結構，以令該電子元件接收該晶片封裝模組之電性訊號，且令該電子連接器接收該電子元件之電性訊號。
前述之電子封裝件及其製法中，該佈線結構係包含線路重佈層。例如，該佈線結構復包含介電層，使該線路重佈層結合該介電層。
前述之電子封裝件及其製法中，復包括將該承載組件設於一基板結構上。
前述之電子封裝件及其製法中，該承載組件係包含一嵌埋有複數第二導電柱之第二封裝層，以令該佈線結構設於該第二封裝層上並電性連接該複數第二導電柱。進一步，該晶片封裝模組係包含一埋設有複數第一導電柱之第一封裝層。例如，該第一封裝層與該第二封裝層係配置於該佈線結構之相對兩側。另外，該第一封裝層之硬度係大於該第二封裝層之硬度。
前述之電子封裝件及其製法中，該晶片封裝模組係包含橋接元件。
前述之電子封裝件及其製法中，該電子連接器係設有一用以連接外部裝置之訊號傳輸線。
由上可知，本發明之電子封裝件及其製法中，主要藉由該第二電子元件及電子連接器通訊連接該晶片封裝模組，以提升訊號傳輸速度，因而可避免多個電子封裝件之間的通訊速度太慢之問題，故相較於習知技 術，本發明於該電路板上，多個電子封裝件上之晶片封裝模組之間的通訊藉由該電子連接器進行電性傳輸，以增快傳輸速度，尤其是，當該電子封裝件應用於高資料速率、逐漸增加的頻寬及逐漸降低時延等需求的人工智慧相關的電子產品時，更可凸顯該電子封裝件之適用性極佳。
再者，隨著包含高性能計算元件的電子封裝件的封裝尺寸需要增大之情況下，各該晶片封裝模組之間的通訊更能符合運作需求。
1:半導體封裝件
1a,2a:晶片封裝模組
10,20:線路結構
11:第一半導體晶片
12:第二半導體晶片
13:導電柱
14,34:基板結構
15:第一封裝膠體
16:第二封裝膠體
17,37:導電元件
18,38:散熱件
19,39:銲球
2:電子封裝件
200,300,81,91:絕緣層
201,301:線路重佈層
202,302:電性接觸墊
21:第一橋接元件
210:電極墊
211:保護膜
212:導電體
213:結合層
22:第一電子元件
220,27:導電凸塊
221,36:底膠
23:第一導電柱
23a,23b:端面
24:線路部
240:導電跡線
241:外接墊
25:第一封裝層
25a:第一表面
25b:第二表面
26:包覆層
28:第二電子元件
280:接點
29:電子連接器
290:訊號傳輸線
3a:承載組件
30:佈線結構
303:凸塊底下金屬層
31:第二橋接元件
32:第三橋接元件
33:第二導電柱
340:佈線層
35:第二封裝層
8:支撐板
80,90:離型層
9:承載板
S:切割路徑
圖1係為習知半導體封裝件之剖視示意圖。
圖2A至圖2H係為本發明之電子封裝件之製法之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」、「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之 範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2H係為本發明之電子封裝件2之製法的剖面示意圖。
如圖2A所示，於一整版面(panel)規格或晶圓級(wafer level)規格之承載板9上形成複數第一導電柱23，且設置至少一第一橋接元件21(本實施例顯示有多個第一橋接元件21)於該承載板9上。接著，形成第一封裝層25於該承載板9上，以令該第一封裝層25包覆該些第一橋接元件21與該些第一導電柱23。
所述之承載板9例如為半導體材質(如矽或玻璃)之板體，其上以例如塗佈方式依序形成有一離型層90與一如介電材或防銲材之絕緣層91。
所述之第一橋接元件21係為半導體晶片，其底側藉由一如置晶膜(die attached film，簡稱DAF)之結合層213黏固於該絕緣層91上，而上側具有複數電極墊210與一如鈍化材之保護膜211，且各該電極墊210上設有導電體212，以令該保護膜211包覆複數導電體212。
於本實施例中，該複數導電體212係為如導電線路、銲球之圓球狀、或如銅柱、銲錫凸塊等金屬材之柱狀、或銲線機製作之釘狀(stud)導電件，但不限於此。
所述之第一導電柱23係為如銅柱之金屬柱或含銲錫材料之柱體，且該複數第一導電柱23係貫穿該絕緣層91。
所述之第一封裝層25係具有相對之第一表面25a與第二表面25b，且令該保護膜211與該複數導電體212之上表面及該第一導電柱 23之端面23a外露於該第一封裝層25之第一表面25a，並令該第一封裝層25以其第二表面25b結合至該承載板9之絕緣層91上。
於本實施例中，該第一封裝層25係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。例如，該第一封裝層25之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該絕緣層91上。
再者，可藉由整平製程，使該第一封裝層25之第一表面25a齊平該保護膜211與該複數導電體212之上表面及該第一導電柱23之端面23a，以令該保護膜211、第一導電柱23之端面23a與該複數導電體212外露於該第一封裝層25之第一表面25a。例如，該整平製程係藉由研磨方式，移除該保護膜211之部分材質、該第一導電柱23之部分材質、該複數導電體212之部分材質與該第一封裝層25之部分材質。
如圖2B所示，形成一線路結構20於該第一封裝層25之第一表面25a上，且令該線路結構20電性連接該複數第一導電柱23與該複數導電體212。
於本實施例中，該線路結構20係包括複數絕緣層200及設於該絕緣層200上之複數線路重佈層(redistribution layer，簡稱RDL)201，其中，最外層之絕緣層200可作為防銲層，且令最外層之線路重佈層201外露於該防銲層，俾供作為電性接觸墊202，如微形墊(u-pad)。進一步，可形成一凸塊底下金屬層(Under Bump Metallurgy，簡稱UBM)(圖略)於該電性接觸墊202上。應可理解地，該線路結構20亦可僅包括單一絕緣層200及單一線路重佈層201。
再者，形成該線路重佈層201之材質係為銅，且形成該絕緣層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(PI)、預浸材(Prepreg，簡稱PP)等之介電材、或如綠漆、油墨等之防銲材。
如圖2C所示，設置至少一第一電子元件22於該線路結構20上，以令該第一電子元件22電性連接該線路結構20(本實施例係顯示有多個第一電子元件22)。接著，移除該承載板9及其上之離型層90，並保留該絕緣層91，使該些第一導電柱23之端面23b外露於該絕緣層91。
所述之第一電子元件22係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
於本實施例中，該第一電子元件22係例如為圖形處理器(graphics processing unit，簡稱GPU)、高頻寬記憶體(High Bandwidth Memory，簡稱HBM)或其它類型半導體晶片之主動元件，但並無特別限制。例如，該第一電子元件22係藉由複數如銲錫凸塊、銅凸塊或其它等之導電凸塊220電性連接該電性接觸墊202，且可藉由包覆層26同時包覆該第一電子元件22與該些導電凸塊220。或者，亦可先形成底膠221於該第一電子元件22與該線路結構20之間以包覆該些導電凸塊220，再形成該包覆層26以包覆該底膠221與該第一電子元件22。
所述之包覆層26係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該線路結構20上。應可理解地，形成該包覆層26之材質可相同或不相同該第一封裝層25之材質。
於本實施例中，可藉由整平製程，如研磨方式，移除該包覆層26之部分材質，使該包覆層26之上表面齊平該第一電子元件22之表面，以令該第一電子元件22外露於該包覆層26。
再者，當配置複數個第一電子元件22時，可使單一該第一橋接元件21藉由該線路結構20電性橋接至少兩個第一電子元件22。
如圖2D所示，形成複數如複數銲錫凸塊或銲球(其規格為C4型)之導電凸塊27於該絕緣層91上，以令該複數導電凸塊27電性連接該複數第一導電柱23。
於本實施例中，可於該絕緣層91上進行RDL製程，以形成包含導電跡線240及外接墊241之線路部24，供該複數導電凸塊27結合於該外接墊241上；或者，亦可於該複數第一導電柱23之端面23b上直接結合該複數導電凸塊27。
如圖2E所示，沿如圖2D所示之切割路徑S進行切單製程，以獲取複數晶片封裝模組2a。
如圖2F所示，於一支撐板8上製作一整版面規格或晶圓級規格之承載組件3a。於本實施例中，該承載組件3a之製程可如圖2A至圖2B所示之方式，故該承載組件3a係包含設於該支撐板8上之至少一第二橋接元件31、至少一第三橋接元件32及複數第二導電柱33，再形成一包覆該第二橋接元件31、該第三橋接元件32及該些第二導電柱33之第二封裝層35，並於該第二封裝層35上形成一佈線結構30。
所述之支撐板8上依序具有一離型層80及一如介電材或防銲材之絕緣層81，以結合該第二橋接元件31、該第三橋接元件32、該些第二導電柱33及該第二封裝層35。
所述之佈線結構30係包含至少一絕緣層300及結合該絕緣層300之至少一線路重佈層(redistribution layer，簡稱RDL)301，且最外層之線路重佈層301係具有複數如微形墊(u-pad)之電性接觸墊302。進一步，可形成一凸塊底下金屬層(UBM)303於該電性接觸墊302上。
於本實施例中，形成該線路重佈層301之材質係為銅，且形成該絕緣層300之材質係如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)或其它適合之介電材，且可採用線路重佈層(redistribution layer，簡稱RDL)製程形成該佈線層301與該絕緣層300。
所述之第二橋接元件31係為半導體晶片構造，其電性連接該線路重佈層301。
所述之第三橋接元件32係為半導體晶片構造，其電性連接該線路重佈層301。
所述之第二導電柱33係為如銅柱之金屬柱或含銲錫材料之柱體，其電性連接該線路重佈層301，並與該第二橋接元件31及該第三橋接元件32相互間隔配置。
所述之第二封裝層35係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)。
於本實施例中，該第二封裝層35之製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)等方式形成於該支撐板8上。
再者，可藉由整平製程，如研磨方式，使該第二封裝層35之表面齊平該複數第二導電柱33之端面，以令該第二導電柱33之端面外露 於該第二封裝層35之表面。應可理解地，該第二橋接元件31及該第三橋接元件32可依需求外露或不外露出該第二封裝層35之表面。
又，該第二封裝層35之材質與該第一封裝層25之材質可相同或不相同。例如，該第一封裝層25之硬度係大於該第二封裝層35之硬度。
如圖2G所示，於該承載組件3a之佈線結構30上設置該晶片封裝模組2a、第二電子元件28及電子連接器(connector)29。接著，移除該支撐板8及離型層80，以外露出該承載組件3a之複數第二導電柱33之端面。
所述之晶片封裝模組2a係以其導電凸塊27電性接合於該佈線結構30上。
所述之第二電子元件28係為半導體晶片構造，其具有複數接點280，並以覆晶方式電性連接該佈線結構30，以接收該晶片封裝模組2a之電性(如數位或類比)訊號。
所述之電子連接器29係以例如銲接方式電性接合該佈線結構30，以接收該第二電子元件28之電性(如數位或類比)訊號。
於本實施例中，該電子連接器29係設有一用以連接外部裝置(圖略)之訊號傳輸線290，以將訊號傳輸至如其它封裝件之外部裝置。應可理解地，可依需求形成底膠36以固定該晶片封裝模組2a、第二電子元件28及電子連接器29。
再者，該第二橋接元件31係電性橋接該晶片封裝模組2a與該第二電子元件28，且該第三橋接元件32係電性橋接該第二電子元件28與該電子連接器29，使該第二電子元件28可藉由該第二橋接元件31與該佈線結構30接收該晶片封裝模組2a之電性訊號，並將該電性訊號藉由該 佈線結構30與該第三橋接元件32傳輸至該電子連接器29，使該電子連接器29將該電性訊號傳輸至該外部裝置。
如圖2H所示，接著於該承載組件3a之絕緣層81上形成複數電性連接該第二導電柱32之導電元件37，再進行切單製程，且該承載組件3a可藉由該些導電元件37堆疊於一基板結構34上。
所述之基板結構34係例如具有核心層之封裝基板(substrate)或無核心層(coreless)式封裝基板，其配置有至少一佈線層340。
所述之導電元件37係為含有銲錫材料之金屬凸塊，其電性連接該基板結構34之佈線層340，並可藉由底膠36包覆該些導電元件37。
於本實施例中，於該基板結構34之上側(即配置該承載組件3a之側)可設置至少一散熱件38，且可於該基板結構34下側之佈線層340上進行值球製程，以形成複數銲球39，供設於一電路板(圖略)上。
因此，本發明之製法主要藉由增設第二電子元件28及電子連接器29，以提升訊號傳輸速度，故相較於習知技術，本發明之電子封裝件2能避免多個電子封裝件之間的通訊速度太慢之問題。例如，於該電路板上，多個晶片封裝模組2a之間的通訊藉由該訊號傳輸線290進行電性傳輸，而無需透過該基板結構34，以增快傳輸速度，尤其是，當該電子封裝件2應用於高資料速率、逐漸增加的頻寬及逐漸降低時延等需求的人工智慧(artificial intelligence，簡稱AI)相關的電子產品時，更能凸顯該電子封裝件2之適用性極佳。
再者，隨著包含高性能計算(high-performance computing，簡稱HPC)元件的電子封裝件2的封裝尺寸需要增大之情況下，各該晶片封裝模組2a之間的通訊更能符合運作需求。
本發明亦提供一種電子封裝件2，係包括：一承載組件3a、一晶片封裝模組2a、一具有複數接點280之第二電子元件28以及一電子連接器29。
所述之承載組件3a係具有佈線結構30。
所述之晶片封裝模組2a係設於該承載組件3a上並電性連接該佈線結構30。
所述之第二電子元件28係設於該承載組件3a上並電性連接該佈線結構30，以接收該晶片封裝模組2a之電性訊號。
所述之電子連接器29係設於該承載組件3a上並電性連接該佈線結構30，以接收該第二電子元件28之電性訊號。
於一實施例中，該佈線結構30係包含絕緣層300及結合該絕緣層300之線路重佈層301。
於一實施例中，所述之電子封裝件2復包括一用以設置該承載組件3a之基板結構34。
於一實施例中，該承載組件3a係包含一嵌埋有複數第二導電柱33之第二封裝層35，以令該佈線結構30設於該第二封裝層35上並電性連接該複數第二導電柱33。進一步，該晶片封裝模組2a係包含一埋設有複數第一導電柱23及第一橋接元件21之第一封裝層25。例如，該第一封裝層25與該第二封裝層35係配置於該佈線結構30之相對兩側。另外，該第一封裝層25之硬度係大於該第二封裝層35之硬度。
於一實施例中，該晶片封裝模組2a係包含第一橋接元件21。
於一實施例中，該電子連接器29係設有一用以連接外部裝置之訊號傳輸線290。
綜上所述，本發明之電子封裝件及其製法，係藉由該第二電子元件及電子連接器通訊連接該晶片封裝模組，以提升訊號傳輸速度，故本發明能避免多個電子封裝件之間的通訊速度太慢之問題。
再者，隨著包含高性能計算元件的電子封裝件的封裝尺寸需要增大之情況下，各該晶片封裝模組之間的通訊更能符合運作需求。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2:電子封裝件
2a:晶片封裝模組
21:第一橋接元件
28:第二電子元件
29:電子連接器
290:訊號傳輸線
3a:承載組件
33:第二導電柱
34:基板結構
340:佈線層
36:底膠
37:導電元件
38:散熱件
39:銲球

Claims (18)

  1. 一種電子封裝件，係包括：
    承載組件，係具有佈線結構；
    晶片封裝模組，係設於該承載組件上並電性連接該佈線結構；
    具有複數接點之電子元件，係設於該承載組件上並電性連接該佈線結構，以接收該晶片封裝模組之電性訊號；以及
    電子連接器，係設於該承載組件上並電性連接該佈線結構，以接收該電子元件之電性訊號。
  2. 如請求項1所述之電子封裝件，其中，該佈線結構係包含介電層及結合該介電層之線路重佈層。
  3. 如請求項1所述之電子封裝件，復包括一用以設置該承載組件之基板結構。
  4. 如請求項1所述之電子封裝件，其中，該承載組件係包含一嵌埋有複數第二導電柱之第二封裝層，以令該佈線結構設於該第二封裝層上並電性連接該複數第二導電柱。
  5. 如請求項4所述之電子封裝件，其中，該晶片封裝模組係包含一埋設有複數第一導電柱之第一封裝層。
  6. 如請求項5所述之電子封裝件，其中，該第一封裝層與該第二封裝層係配置於該佈線結構之相對兩側。
  7. 如請求項5所述之電子封裝件，其中，該第一封裝層之硬度係大於該第二封裝層之硬度。
  8. 如請求項1所述之電子封裝件，其中，該晶片封裝模組係包含橋接元件。
  9. 如請求項1所述之電子封裝件，其中，該電子連接器係設有一用以連接外部裝置之訊號傳輸線。
  10. 一種電子封裝件之製法，係包括：
    提供一設有佈線結構之承載組件；以及
    將晶片封裝模組、具有複數接點之電子元件及電子連接器設於該承載組件上，並使該晶片封裝模組、電子元件及電子連接器電性連接該佈線結構，以令該電子元件接收該晶片封裝模組之電性訊號，且令該電子連接器接收該電子元件之電性訊號。
  11. 如請求項10所述之電子封裝件之製法，其中，該佈線結構係包含介電層及結合該介電層之線路重佈層。
  12. 如請求項10所述之電子封裝件之製法，復包括將該承載組件設於一基板結構上。
  13. 如請求項10所述之電子封裝件之製法，其中，該承載組件係包含一嵌埋有複數第二導電柱之第二封裝層，以令該佈線結構設於該第二封裝層上並電性連接該複數第二導電柱。
  14. 如請求項13所述之電子封裝件之製法，其中，該晶片封裝模組係包含一埋設有複數第一導電柱之第一封裝層。
  15. 如請求項14所述之電子封裝件之製法，其中，該第一封裝層與該第二封裝層係配置於該佈線結構之相對兩側。
  16. 如請求項14所述之電子封裝件之製法，其中，該第一封裝層之硬度係大於該第二封裝層之硬度。
  17. 如請求項10所述之電子封裝件之製法，其中，該晶片封裝模組係包含橋接元件。
  18. 如請求項10所述之電子封裝件之製法，其中，該電子連接器係設有一用以連接外部裝置之訊號傳輸線。
TW111107998A 2022-03-04 2022-03-04 電子封裝件及其製法 TWI818458B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW111107998A TWI818458B (zh) 2022-03-04 2022-03-04 電子封裝件及其製法
CN202210246848.7A CN116759410A (zh) 2022-03-04 2022-03-14 电子封装件及其制法
US17/740,796 US12176291B2 (en) 2022-03-04 2022-05-10 Electronic package and manufacturing method thereof
US18/916,941 US20250038113A1 (en) 2022-03-04 2024-10-16 Electronic package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111107998A TWI818458B (zh) 2022-03-04 2022-03-04 電子封裝件及其製法

Publications (2)

Publication Number Publication Date
TW202336970A true TW202336970A (zh) 2023-09-16
TWI818458B TWI818458B (zh) 2023-10-11

Family

ID=87849908

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111107998A TWI818458B (zh) 2022-03-04 2022-03-04 電子封裝件及其製法

Country Status (3)

Country Link
US (2) US12176291B2 (zh)
CN (1) CN116759410A (zh)
TW (1) TWI818458B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI860156B (zh) * 2023-11-07 2024-10-21 矽品精密工業股份有限公司 電子封裝件及其製法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI818458B (zh) * 2022-03-04 2023-10-11 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307293B2 (en) * 2002-04-29 2007-12-11 Silicon Pipe, Inc. Direct-connect integrated circuit signaling system for bypassing intra-substrate printed circuit signal paths
KR101542915B1 (ko) * 2008-10-10 2015-08-07 퀄컴 엠이엠에스 테크놀로지스, 인크. 분산 조명 시스템
US10553542B2 (en) * 2017-01-12 2020-02-04 Amkor Technology, Inc. Semiconductor package with EMI shield and fabricating method thereof
US10283474B2 (en) * 2017-06-30 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10622326B2 (en) * 2017-08-18 2020-04-14 Industrial Technology Research Institute Chip package structure
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10665520B2 (en) * 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11139249B2 (en) * 2019-04-01 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of forming the same
TWI707408B (zh) * 2019-04-10 2020-10-11 力成科技股份有限公司 天線整合式封裝結構及其製造方法
US11094637B2 (en) * 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
KR20210071539A (ko) * 2019-12-06 2021-06-16 삼성전자주식회사 인터포저, 반도체 패키지, 및 인터포저의 제조 방법
US11817325B2 (en) * 2020-01-17 2023-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing a semiconductor package
US11296032B2 (en) * 2020-05-28 2022-04-05 Taiwan Semiconductor Manufacturing Company Limited Silicon interposer including through-silicon via structures with enhanced overlay tolerance and methods of forming the same
KR20220028310A (ko) * 2020-08-28 2022-03-08 삼성전자주식회사 배선 구조체, 이의 제조 방법 및 배선 구조체를 포함하는 반도체 패키지
KR20220030051A (ko) * 2020-09-02 2022-03-10 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
US11756871B2 (en) * 2020-09-15 2023-09-12 Sj Semiconductor (Jiangyin) Corporation Fan-out packaging structure and method
US12125798B2 (en) * 2021-04-28 2024-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method
TWI754586B (zh) * 2021-05-04 2022-02-01 矽品精密工業股份有限公司 電子封裝件及其製法
WO2022251986A1 (zh) * 2021-05-29 2022-12-08 华为技术有限公司 芯片封装结构、其制备方法及终端设备
TWI773360B (zh) * 2021-06-03 2022-08-01 矽品精密工業股份有限公司 電子封裝件及其承載結構與製法
CN115706104A (zh) * 2021-08-13 2023-02-17 华为技术有限公司 一种在板光互连装置及通信设备
US20230215808A1 (en) * 2021-12-30 2023-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with integrated circuit chip couplers
TWI790916B (zh) * 2022-02-09 2023-01-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI788230B (zh) * 2022-02-23 2022-12-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI818458B (zh) * 2022-03-04 2023-10-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI788237B (zh) * 2022-03-07 2022-12-21 矽品精密工業股份有限公司 電子封裝件及其製法與天線模組及其製法
TWI807827B (zh) * 2022-05-13 2023-07-01 矽品精密工業股份有限公司 電子封裝件及其製法
TWI825790B (zh) * 2022-06-17 2023-12-11 矽品精密工業股份有限公司 電子封裝件及其製法
TWI800416B (zh) * 2022-06-24 2023-04-21 矽品精密工業股份有限公司 電子封裝件及其製法
US20240014111A1 (en) * 2022-07-05 2024-01-11 Byung Joon Han Fan-out packaging device using bridge and method of manufacturing fan-out packaging device using bridge
TWI814524B (zh) * 2022-08-05 2023-09-01 矽品精密工業股份有限公司 電子封裝件及其製法與電子結構及其製法
US20240072019A1 (en) * 2022-08-31 2024-02-29 Siliconware Precision Industries Co., Ltd. Electronic package and manufacturing method thereof
TWI823618B (zh) * 2022-10-14 2023-11-21 矽品精密工業股份有限公司 電子封裝件
TWI827335B (zh) * 2022-11-03 2023-12-21 矽品精密工業股份有限公司 電子封裝件及其製法
TWI832571B (zh) * 2022-11-21 2024-02-11 矽品精密工業股份有限公司 電子封裝件及其製法
KR20240106371A (ko) * 2022-12-29 2024-07-08 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CN117038623B (zh) * 2023-08-18 2024-08-02 上海纳矽微电子有限公司 用于将芯片打线至框架的载具组件和芯片打线方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI860156B (zh) * 2023-11-07 2024-10-21 矽品精密工業股份有限公司 電子封裝件及其製法

Also Published As

Publication number Publication date
TWI818458B (zh) 2023-10-11
US20230282586A1 (en) 2023-09-07
US20250038113A1 (en) 2025-01-30
CN116759410A (zh) 2023-09-15
US12176291B2 (en) 2024-12-24

Similar Documents

Publication Publication Date Title
CN111952274B (zh) 电子封装件及其制法
TWI730917B (zh) 電子封裝件及其製法
TWI765778B (zh) 電子封裝件及其製法
TWI728936B (zh) 電子封裝件及其製法
US20250038113A1 (en) Electronic package and manufacturing method thereof
TWI714269B (zh) 電子封裝件及其製法
US20230369229A1 (en) Electronic package and manufacturing method thereof
TWI753561B (zh) 電子封裝件及其製法
CN117153805A (zh) 电子封装件及其制法
TWI647798B (zh) 電子封裝件及其製法
TW201719841A (zh) 電子封裝件及其製法
TWI827335B (zh) 電子封裝件及其製法
US20230411364A1 (en) Electronic package and manufacturing method thereof
US20240072019A1 (en) Electronic package and manufacturing method thereof
TWI788230B (zh) 電子封裝件及其製法
TWI790945B (zh) 電子封裝件及其製法
TWI778406B (zh) 電子封裝件及其製法
TWI766192B (zh) 電子封裝件及其製法
CN109037179A (zh) 电子封装件及其制法
TWI847245B (zh) 電子封裝件及其製法
TWI819440B (zh) 電子封裝件及其製法
US20240145455A1 (en) Electronic package and manufacturing method thereof
US20250062299A1 (en) Electronic package and manufacturing method thereof
CN118073292A (zh) 电子封装件及其制法