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TW201444048A - 覆晶晶圓級封裝及其方法 - Google Patents

覆晶晶圓級封裝及其方法 Download PDF

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Publication number
TW201444048A
TW201444048A TW102141481A TW102141481A TW201444048A TW 201444048 A TW201444048 A TW 201444048A TW 102141481 A TW102141481 A TW 102141481A TW 102141481 A TW102141481 A TW 102141481A TW 201444048 A TW201444048 A TW 201444048A
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TW
Taiwan
Prior art keywords
die
electronic package
flip chip
package
flip
Prior art date
Application number
TW102141481A
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English (en)
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TWI517342B (zh
Inventor
Thorsten Meyer
Original Assignee
Intel Mobile Comm Gmbh
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Application filed by Intel Mobile Comm Gmbh filed Critical Intel Mobile Comm Gmbh
Publication of TW201444048A publication Critical patent/TW201444048A/zh
Application granted granted Critical
Publication of TWI517342B publication Critical patent/TWI517342B/zh

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    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

一種電子封裝，包含：一覆晶組件，其具有耦合至一覆晶基板之一第一晶粒；堆疊在該第一晶粒上之第二晶粒；形成於該第一晶粒與該第二晶粒周圍之一包封化合物；一組穿過該包封化合物至該覆晶基板之穿包封物通孔(TEV)，其提供從該電子封裝之第一側至該電子封裝之第二側的一組電連接件；及一重分佈層，其將該第二晶粒上之一組接點電連接至該電子封裝之第一側上的該組TEV。

Description

覆晶晶圓級封裝及其方法
本發明係關於製造電子設備之裝置及方法，且更具體而言係關於電子封裝及其製造方法。
在製造積體電路(IC)時，在分佈及與其他電子總成整合之前，稱為晶片或晶粒之IC通常係被封裝。此封裝通常包含將晶片包封在材料中並且在封裝之外部上提供電接點以提供一界面至晶片。除此之外，晶片封裝可提供保護免於污染物、提供機械支撐、分散熱能及減少熱-機械應力。
由於IC製造及IC封裝之間的關係，IC封裝整體而言隨著半導體產業快速發展亦必須進步。特定而言，存在有要求封裝IC及其他電子設備使其更小、更快及更可靠之趨勢。
在本發明之一第一態樣中，一電子封裝包含：具有一 第一晶粒耦合至一覆晶基板之一覆晶組件；堆疊在第一晶粒上之一第二晶粒；形成於第一晶粒及第二晶粒周圍之一包封化合物；一組穿過包封化合物至覆晶基板之穿包封物通孔(TEV)，其提供從電子封裝之一第一側至電子封裝之一第二側的一組電連接件；及一重分佈層，其將第二晶粒上之一組接點電連接至電子封裝之第一側上之該組TEV。
在本發明之另一態樣中係提供用於製造一電子封裝之方法。該方法包含：提供一覆晶組件，其具有耦合至覆晶基板之一第一晶粒；將該第一晶粒黏附至一第二晶粒；於第一晶粒及第二晶粒周圍形成一包封化合物；鑽鑿一組穿包封物通孔(TEV)，係從電子封裝之一第一側鑽鑿至定位在電子封裝之一第二側上的覆晶基板；以一導電材料填充該組TEV；且施加一重分佈層，其將第二晶粒上之一組接點電連接至該電子封裝之第一側上之該組TEV。
在本發明之又另一態樣中，一記憶體裝置包含：一覆晶組件，其具有一第一晶粒耦合至一覆晶基板；堆疊在第一晶粒上之一第二晶粒；形成於第一晶粒及第二晶粒周圍之一包封化合物；一組穿包封物通孔(TEV)，其提供從電子封裝之一第一側至該電子封裝之一第二側穿過該包封化合物至該覆晶基板之一組電連接件；及一重分佈層，其將第二晶粒上之一組接點電連接至在電子封裝之第一側上之該組TEV。第一晶粒及/或第二晶粒包含一記憶體功能。
在本發明之又另一態樣中，一電子封裝包含一第一電子封裝及一第二電子封裝。第二電子封裝包含：一覆晶組 件，其具有耦合至一覆晶基板之一第一晶粒；堆疊在第一晶粒上之一第二晶粒；形成於第一晶粒及第二晶粒周圍之一包封化合物；一組穿包封物通孔(TEV)，其提供從電子封裝之一第一側至電子封裝之一第二側穿過包封化合物至覆晶基板之一組電連接件；及一重分佈層，其將第二晶粒上之一組接點電連接至電子封裝之第一側上之該組TEV。第一電子封裝係與第二電子封裝堆疊在一起以形成一堆疊封裝(PoP)電子封裝。
1‧‧‧晶片
1’‧‧‧晶粒
3‧‧‧晶片
3’‧‧‧晶粒
5‧‧‧焊線
7‧‧‧包封化合物
9‧‧‧凸塊-底部填充層
10‧‧‧覆晶焊線封裝
10’‧‧‧覆晶晶圓級封裝
11‧‧‧層狀基板
11’‧‧‧覆晶基板
13‧‧‧焊料球
15‧‧‧黏著劑
16‧‧‧保護層
16’‧‧‧其他曝露組件
17‧‧‧重分佈層
18‧‧‧覆晶組件
19‧‧‧穿包封物通孔
30‧‧‧方法
33‧‧‧模具載具
35‧‧‧可釋離膠帶
37‧‧‧包封化合物
39‧‧‧介電層
41‧‧‧晶粒
43‧‧‧晶粒
240‧‧‧覆晶晶圓級封裝
為了進一步闡明上述及本發明之其他優點及特徵，本發明之一更詳細說明將參考繪示在附圖中之特定實施例來呈現。可以理解的是，這些圖式只描繪本發明之典型實施例，且因此不應被認為限制其範圍。本發明將透過利用隨附圖式而以額外的特定性及細節來描述及說明，其中：圖1係一覆晶焊線封裝。
圖2係一覆晶晶圓級封裝。
圖3繪示用於製造在圖2中所示之覆晶晶圓級封裝之方法。
圖4至13描繪用於製造在圖2中所示之覆晶晶圓級封裝之程序流程。
圖14至23描繪用於製造在圖2中所示之覆晶晶圓級封裝之替代程序流程。
圖24係具有三個晶片配置之一覆晶晶圓級封裝。
現在將參考圖式，其中相同結構將以相同元件標號來標示。應瞭解，該圖式係本發明之例示性實施例的示意性及概要表示，而非限制本發明，且亦不一定按比例繪製。
在分佈及與其他電子總成整合之前，晶片(在本文中替代地稱為晶粒)通常會被封裝。此封裝通常包含將晶片包封在一材料中且在封裝之外部上提供電接點以提供一界面至晶片。除此之外，晶片封裝可提供保護以免於污染物、提供機械支撐、分散熱能及減少熱-機械應力。
為了例如降低整體總成尺寸、功能性電路速度及整體成本，將多個晶片堆疊在一單一晶片封裝係愈來愈普遍的封裝條件。
圖1係一覆晶焊線封裝10。覆晶焊線封裝10包含兩個晶片1、3，被配置成使得晶片1被堆疊在晶片3之頂部。晶片3經由凸塊-底部填充層9被耦合至一層狀基板11。層狀基板11接著被耦合至焊料球13。以此方式，晶片3在實體上及電學上係間接地耦合至一些焊料球13，使得焊料球13之一子組對於晶片3形成一電性界面。晶片1同樣地藉由焊線5電耦合至層狀基板11。以此方式，晶片1間接地電耦合至一些焊料球13，使得焊料球13之一子組形成用於晶片1之一電性界面。包封化合物7被模製成圍繞晶片1、3、焊線5及凸塊-底部填充層9。包封化合物7大體上形成在層狀基板11之頂部上。以此方式，覆晶焊線封裝10與藉由焊料球13提供之一界面形 成一整體式封裝。
當覆晶焊線封裝10及其他焊線封裝提供用於封裝生產之一方法時，在業界中持續的發展已經朝向較低封裝輪廓及增加的電性效能。
穿矽通孔(TSV)提供穿過半導體晶圓的一連接件以用於堆疊之目的。TSV可提供更好的電性效能及較低輪廓。然而，成本及可靠供應鏈管理一般在業界中可能會限制TSV廣泛的使用。
圖2係一覆晶晶圓級封裝10’。覆晶晶圓級封裝10’包含一覆晶組件18，其包含耦合至覆晶基板11’之晶粒3’。如圖所示，晶粒3’經由凸塊-底部填充層9’而耦合至覆晶基板11’。
晶粒1’被配置在晶粒3’之頂部，而且包封化合物7’被形成在晶粒1’及晶粒3’周圍。在形成包封化合物7’之前，晶粒1’可藉由施加一黏著劑15(諸如在晶粒1’及3’之間之一晶粒附著膜(DAF))而被黏合至晶粒3’。黏著劑15可例如透過積層、印刷或施配黏著劑而被施加至一個晶粒上且接著在固化之前將其餘的晶粒放置在黏著劑上。
一組穿包封物通孔(TEV)19提供穿過覆晶晶圓級封裝10’之包封化合物7’的電連接件。此外，一重分佈層17將TEV 19電連接至晶粒1’。覆晶晶圓級封裝10’進一步包含黏合至覆晶基板11’的焊料球13’，而且一保護層16可覆蓋重分佈層17及TEV 19以保護其他曝露組件16’。覆晶晶圓級封裝10’亦可在第二晶粒及重分佈層之間包含一介 電層。
晶粒1’及3’可依照標準半導體製造程序被製造。亦即，大致上在一錠塊生長之後，其被切割成晶圓。晶圓之區域可經歷沈積、移除、圖案化及摻雜程序。一旦晶圓已經被處理，該晶圓通常會被安裝且切割成個別晶粒。特定而言，晶粒3’被進一步處理且被提供作為覆晶組件18之部分。亦即，晶粒3’利用覆晶技術來予以處理，使得晶粒3’被耦合至覆晶基板11’以藉此形成覆晶組件18。
包封化合物7’大致上係由塑膠材料組成，但若有需要亦可使用其他材料，諸如陶瓷及金屬及矽或玻璃。特定而言，熱固性模製化合物係一種基於環氧樹脂之塑膠材料。這些類型的化合物在過去已被使用於電子封裝應用。熱塑性塑膠(諸如高純度氟聚合物)係可被使用作為包封化合物7’之另一種塑膠材料。
TEV 19係藉由穿過包封化合物7’鑽鑿孔且接著用導電材料填充該等鑽孔而形成。鑽鑿TEV孔可例如用機械鑽頭、雷射或透過化學蝕刻來執行。
在晶粒1’上之接點能以任何方式來配置。然而，如在圖2中所描繪，晶粒1’被配置成使得其接點相對於晶粒3’上之接點而配置。以此方式，重分佈層17可以被直接地施加在晶粒1’上，且藉此連接至晶粒1’上之接點。重分佈層17較佳地利用薄膜技術來施加。薄膜沈積除其他技術外可例如經由濺鍍、電鍍或化學氣相沈積(CVD)來完成。
依照覆晶晶圓級封裝10’所建構之電子封裝可進一步包含或組合以下一或多個特徵。晶粒1’及/或晶粒3’可包含記憶體功能。例如，覆晶晶圓級封裝10’可實施動態隨機存取記憶體(DRAM)。一電子封裝可包含一第一電子封裝及一第二電子封裝，其至少一個係依照覆晶晶圓級封裝10’被建構；該第一電子封裝可與該第二電子封裝一起堆疊以形成一堆疊封裝(PoP)電子封裝。以此方式，如圖1中所描繪之晶粒1’及3’係由第一及第二電子封裝所取代，而覆晶晶圓級封裝10’之其餘結構則相對地保持相同。
覆晶晶圓級封裝10’可在覆晶組件18之晶粒3’上包含額外晶粒堆疊。亦即，除了晶粒1’及3’之外，覆晶晶圓級封裝10’可包含更多晶粒，使得在覆晶晶圓級封裝10’中之晶粒的總數量係三個或更多個。
覆晶晶圓級封裝10’可被構造成使得在第二晶粒上之該組接點及電子封裝之第一側之一表面之間之距離大約小於20μm。此一配置減少封裝尺寸並且可減少整體電子總成尺寸。
關於晶圓級封裝10’之製造之進一步細節在以下將詳細參考圖3至23來描述。圖3繪示用於製造在圖2中所示之覆晶晶圓級封裝之方法，而圖4至13描繪用於製造在圖2中所示之覆晶晶圓級封裝10’之程序流，且圖14至23描繪用於製造在圖2中所示之覆晶晶圓級封裝10’之另一程序流。
參考圖3，提供用於製造一電子封裝之方法30。在圖4中，可提供具有可釋離膠帶35之一模具載具33。例如，黏著劑箔可被使用作為可釋離膠帶35並且可例如藉由積層而於其上被施加至模具載具33。
在圖5中，晶粒1’經由可釋離膠帶35被黏合至模具載具33。較佳地，晶粒1’被面朝下放置在可釋離膠帶35上。亦即，晶粒1’被配置成使得其上之電接點被導引朝向模具載具33。晶粒1’及3’可依照標準半導體製造程序被製造。亦即，大致在一錠塊生長之後，其被切割成晶圓。晶圓之區域可經歷沈積、移除、圖案化及摻雜程序。一旦晶圓已經被處理，該晶圓一般會被安裝且被切割成個別晶粒。特定而言，晶粒3’被進一步處理且被提供作為覆晶組件18之部分。亦即，晶粒3’利用覆晶技術來處理，使得晶粒3’被耦合至覆晶基板11’以藉此形成覆晶組件18。
在圖6中，黏著劑15接著被施加至晶粒1’之一側邊。較佳地，黏著劑15被施加在之晶粒1’之側邊，該側邊係相對置於黏合至模具載具33’之晶粒1’之側邊，或更簡單地說，黏著劑15較佳地被施加至晶粒1’之背側。晶粒1’可藉由在晶粒1’及3’之間施加一黏著劑15(諸如一晶粒附著膜(DAF))而被黏合至晶粒3’。黏著劑15可例如透過積層、印刷或施配黏著劑而被施加。
方法30接著包含如圖7中所示在步驟21中提供具有晶粒3’耦合至覆晶基板11’之一覆晶組件18，而且在步驟23中黏附晶粒3’至晶粒1’。如上面參考圖6所述，由於 晶粒1’之背側已經具有黏著劑15被施加於其上，因此晶粒3’可經由先前所提供的黏著劑15而被黏合至晶粒1’。以此方式，覆晶組件18藉由晶粒1’及3’之黏附而被黏合至模具載具33。若有必要，黏著劑15可藉由添加能量來予以固化。例如，可添加化學、熱或紫外光(UV)來固化黏著劑15。
方法30進一步包含如圖8中所示於步驟25中形成圍繞晶粒1’及3’之包封化合物37。包封化合物7’大致上由塑膠材料組成，但若有需要亦可使用其他材料，諸如陶瓷及金屬及矽或玻璃。特定而言，熱固性模製化合物係一種基於環氧樹脂之塑膠材料。這些類型之化合物在過去已被用於電子封裝應用。熱塑性塑膠(諸如一高純度氟聚合物)係另一種可被使用作為包封化合物7’的塑膠材料。應注意，覆晶基板11’之一曝露側可能會保持未由包封化合物7’所覆蓋。為了不以包封化合物7’來覆蓋覆晶基板11’，可在一壓縮模製工具中使用一頂部箔或可採用射出成型技術。另一個可行性係在模製之後將附著的模具化合物向下研磨至基板接點。
在圖9中，在包封化合物37已經被形成之後，便釋放模具載具33。作為釋放模具載具33之部分，黏著劑35亦可被移除，而且可施加及建構一介電層39。施加介電層39可例如藉由旋轉塗覆及光微影或藉由積層及雷射結構化來執行。介電層39亦可於稍後來施加，或可以與TEV鑽鑿同時地被建構。
方法30進一步包含如圖10中所示在步驟27中從電子封裝之一第一側鑽鑿一組穿包封物通孔(TEV)19至定位在電子封裝之一第二側上的覆晶基板11’。TEV 19藉由鑽鑿穿過包封化合物7’及可能存在的介電材料(若未事先結構化，如圖10中所示)之孔而形成，接著用導電材料填充鑽孔，如在圖11中所示。TEV孔之鑽鑿可例如用一機械鑽頭、一雷射或透過化學蝕刻來執行。在執行鑽鑿時，在覆晶基板11’上可使用通孔擋止件以對鑽鑿提供一停止點。
方法30接著包含如圖11中所示在步驟29中以導電材料填充TEV 19及在步驟31中施加重分佈層17，藉此將晶粒1’上之一組接點電連接至電子封裝10’之一第一側上之TEV 19。步驟29中以導電材料填充TEV 19及步驟31中施加重分佈層17可在不同部分來執行，或可在單一步驟中同時地發生。重分佈層17電連接TEV 19與焊料球位置，並且亦可提供晶載連接及在一給定平面中多個晶片之間之連接。
在圖12中，一焊料擋止件或背側保護(BSP)(諸如保護層16)可被施加在重分佈層17之頂部上，藉此例如賦予電子封裝10’一致的黑背側，以保護重分佈層17並且保護TEV 19。此焊料擋止件或BSP可利用一旋塗、積層、噴霧塗覆或印刷程序來施加。
最後，在圖13中，焊料球13’被施加或黏合至覆晶基板11’，且個別封裝(若還沒有分離)則可在此時予以分 離。焊料球13’可以係例如習知的焊料球、半球、聚合物核心球或平面柵格陣列(LGA)，且可經由例如焊接至其而被黏合。
此外，為了生產一更小、更有效封裝，覆晶晶圓級封裝10’允許在製造程序之間分離測試及預燒覆晶組件18。亦即，在繼續製造覆晶晶圓級封裝10’之前，覆晶組件18可被單獨地製造、測試及預燒。
參考圖14至23，其中展示一替代性程序流。在圖14中，提供具有可釋離膠帶35之一模具載具33。亦即，可釋離膠帶35被施加至模具載具33。例如，可使用一黏著劑箔作為可釋離膠帶35並且在其上層疊至模具載具33。
在圖15中，覆晶組件18經由先前施加的可釋離膠帶35被黏合至模具載具33。更特定言之，覆晶基板11’經由可釋離膠帶35被黏合至模具載具33。
類似於在此之前所述之程序流，在圖16中，晶粒1’接著經由黏著劑15附著至晶粒3’。黏著劑15被施加至晶粒3’之一側邊，或者係晶粒1’。較佳地，黏著劑15被施加至晶粒3’之側邊，該側邊係相對置於黏合至覆晶基板11’之晶粒3’的側邊，或更簡單地說，黏著劑15較佳地被施加至晶粒3’之背側。晶粒1’可藉由在晶粒1’及3’之間施加黏著劑15(諸如一晶粒附著膜(DAF))而被黏合至晶粒3’。黏著劑15可例如透過積層、印刷或施配黏著劑而施加。晶粒1’及3’接著藉由先前施加的黏著劑15而黏合在一起。以此方式，晶粒1’經由晶粒1’及3’之黏附而被黏 合至模具載具33。若有必要，黏著劑15可藉由添加能量而予以固化。例如，可添加化學、熱或紫外光(UV)來固化黏著劑15。較佳地，晶粒1’及3’如圖所示被定位，使得各自接點係彼此相對置。
如圖17中所示，包封化合物7’形成在晶粒1’及3’上及周圍，而且模具載具33連同可移除黏著劑35被移除。包封化合物7’一般由塑膠材料組成，但若有需要亦可使用其他材料，諸如陶瓷及金屬。特定而言，熱固性模製化合物係一種基於環氧樹脂之塑膠材料。這些類型化合物在過去已被用於電子封裝應用。熱塑性塑膠(諸如高純度氟聚合物)係另一種可被使用作為包封化合物7’之塑膠材料。
在圖18中，晶粒1’之接點或所施加支柱可接著被曝露，這可藉由例如研磨包封化合物37直到支柱被曝露且包封化合物7’形成具有晶粒1’之表面之大致上平坦表面。或者，接點或所施加的支柱可藉由雷射鑽鑿穿過包封化合物7’而被曝露。作為另一選項，具有接點之晶粒1’的側邊可能會保留而未被包封化合物7’包覆。為了不以包封化合物7’覆蓋覆晶基板11’，在一壓縮模製工具中可使用一頂部箔或可採用射出成型技術。
在圖19中，介電層39被施加且至少部分地被結構化。施加介電層39可例如藉由旋轉塗覆或藉由積層及雷射結構化來執行。介電層39亦可在稍後被施加，或可以與TEV鑽鑿同時地被結構化。
在圖20中，TEV 19被鑽鑿，且在圖21中，其用導 電材料填充。TEV 19從電子封裝之一第一側鑽鑿至被定位在電子封裝之一第二側上之覆晶基板11’。TEV 19藉由鑽鑿穿過包封化合物7’及可能的介電層39之孔而形成，且接著用導電材料填充該鑽孔。鑽鑿TEV孔可例如藉由一機械鑽頭、一雷射或透過化學蝕刻來執行。在執行鑽鑿時，在覆晶基板11’上之通孔擋止件可用以對鑽鑿提供一停止點。
在圖21中，施加重分佈層17以將TEV 19電連接至晶粒1’。在步驟29中以導電材料填充TEV 19且在步驟31中施加重分佈層17係可在不同部分中執行，或可在一單一步驟同時地發生。重分佈層17將TEV 19與焊料球位置電連接，並且亦可提供晶載連接及在一給定平面中多個晶片之間的連接。
在圖22中，一焊料擋止件或背側保護(BSP)(諸如保護層16)可被施加在重分佈層17之頂部上，藉此賦予電子封裝10’例如一致的黑背側，以保護重分佈層17並且保護TEV 19。此焊料擋止件或BSP可利用一旋塗、積層或印刷程序來施加。
最後，在圖23中，焊料球13’被施加或黏合至覆晶基板11’，且若尚未分離，則可在此時分離個別封裝。如上所述，焊料焊料球13’可例如係習知的焊料球、半球、聚合物核心球或平面柵格陣列(LGA)而且可例如經由焊接至其而被黏合。
可依照上面的說明來配置額外晶粒。例如，如圖24 中所示，覆晶晶圓級封裝240可被構造成使得晶粒41及43與晶粒3’堆疊在一起。以此方式，複數個晶粒可被引入至此一電子封裝。特定而言，多個晶粒可被黏合至其中而不是經由黏著劑15黏附單一晶粒至晶粒3’。
本發明能以特定形式來實施而不違背其精神或基本特性。所說明的實施例在所有方面僅係說明性而非限制性。因此，本發明之範圍藉由隨附申請專利範圍所指示而不是藉由上述的說明。所有落入申請專利範圍之文意及等效範圍內的改變都將被含括在其範疇內。
1’‧‧‧晶粒
3’‧‧‧晶粒
7’‧‧‧包封化合物
9’‧‧‧凸塊-底部填充層
10’‧‧‧覆晶晶圓級封裝
11’‧‧‧覆晶基板
13’‧‧‧焊料球
15‧‧‧黏著劑
16‧‧‧保護層
17‧‧‧重分佈層
18‧‧‧覆晶組件
19‧‧‧穿包封物通孔

Claims (21)

  1. 一種電子封裝，包括：一覆晶組件，其具有耦合至一覆晶基板的一第一晶粒；堆疊在該第一晶粒上之一第二晶粒；形成於該第一晶粒與該第二晶粒周圍之一包封化合物；一組穿過該包封化合物至該覆晶基板之穿包封物通孔(TEV)，其提供從該電子封裝之第一側至該電子封裝之第二側的一組電連接件；及一重分佈層，其將該第二晶粒上之一組接點電連接至該電子封裝之第一側上的該組TEV。
  2. 如申請專利範圍第1項之電子封裝，其進一步包括堆疊在該覆晶組件之該第一晶粒上的一組額外晶粒。
  3. 如申請專利範圍第1項之電子封裝，其中該第一晶粒之一組接點係配置成與該第二晶粒之該組接點相對置。
  4. 如申請專利範圍第1項之電子封裝，其中該重分佈層係一薄膜層。
  5. 如申請專利範圍第1項之電子封裝，其進一步包括覆蓋該重分佈層及該等TEV的一保護層。
  6. 如申請專利範圍第1項之電子封裝，其進一步包括黏合至該覆晶基板的焊料球。
  7. 如申請專利範圍第1項之電子封裝，其中在該第 二晶粒上之該組接點及該電子封裝之該第一側的一表面之間的距離係小於大約20微米。
  8. 如申請專利範圍第1項之電子封裝，其進一步包括在該第二晶粒與該重分佈層之間之一介電層。
  9. 一種用於製造電子封裝之方法，該方法包括：提供一覆晶組件，其具有耦合至一覆晶基板的一第一晶粒；將該第一晶粒黏附至一第二晶粒；於該第一晶粒與該第二晶粒周圍形成一包封化合物；鑽鑿一組穿包封物通孔(TEV)，係從該電子封裝之一第一側鑽鑿至定位在該電子封裝之一第二側上之該覆晶基板；以一導電材料填充該組TEV；且施加一重分佈層，其將該第二晶粒上之一組接點電連接至該電子封裝之該第一側上的該組TEV。
  10. 如申請專利範圍第9項之方法，其進一步包括施加覆蓋該重分佈層及該等TEV的一保護層。
  11. 如申請專利範圍第9項之方法，其進一步包括將焊料球黏附至該覆晶基板。
  12. 如申請專利範圍第9項之方法，其進一步包括分開地測試及預燒該覆晶組件。
  13. 如申請專利範圍第9項之方法，其進一步包括：以一可釋離黏著劑將第二晶粒黏附至一模具載具；且將該模具載具從該第二晶粒移除。
  14. 如申請專利範圍第9項之方法，其進一步包括：以一可釋離黏著劑將覆晶組件黏附至一模具載具；且將該模具載具從該覆晶組件移除。
  15. 如申請專利範圍第14項之方法，其進一步包括將一組支柱耦合在該第二晶粒上之該組接點上。
  16. 如申請專利範圍第13項之方法，其中該等支柱包括銅。
  17. 如申請專利範圍第14項之方法，其進一步包括：於該第二晶粒之上形成該包封化合物；及曝露該等支柱。
  18. 如申請專利範圍第17項之方法，其中曝露該等支柱包括研磨該包封化合物直到該等支柱被曝露，該包封化合物形成一實質上平坦表面。
  19. 如申請專利範圍第17項之方法，其中曝露該等支柱包括雷射鑽鑿該包封化合物。
  20. 一種記憶體裝置，包括：一覆晶組件，其具有耦合至一覆晶基板的一第一晶粒；堆疊在該第一晶粒上之一第二晶粒；形成於該第一晶粒與該第二晶粒周圍之一包封化合物；一組穿包封物通孔(TEV)，其提供從該電子封裝之第一側至該電子封裝之第二側穿過該包封化合物至該覆晶基 板的一組電連接件；及一重分佈層，其將第二晶粒上之一組接點電連接至該電子封裝之該第一側上的該組TEV，其中由該第一晶粒及該第二晶粒組成之群組中的至少一者包含記憶體功能。
  21. 一種電子封裝，包括：一第一電子封裝；及一第二電子封裝，其包括：一覆晶組件，其具有耦合至一覆晶基板的一第一晶粒；堆疊在該第一晶粒上之一第二晶粒；形成於該第一晶粒與該第二晶粒周圍之一包封化合物；一組穿包封物通孔(TEV)，其提供從該電子封裝之第一側至該電子封裝之第二側穿過該包封化合物至該覆晶基板的一組電連接件；及一重分佈層，其將第二晶粒上之一組接點電連接至該電子封裝之該第一側上的該組TEV，其中該第一電子封裝係與該第二電子封裝堆疊在一起以形成一堆疊封裝(PoP)電子封裝。
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