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TWI585910B - 扇出型背對背晶片堆疊封裝構造及其製造方法 - Google Patents

扇出型背對背晶片堆疊封裝構造及其製造方法 Download PDF

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Publication number
TWI585910B
TWI585910B TW105104146A TW105104146A TWI585910B TW I585910 B TWI585910 B TW I585910B TW 105104146 A TW105104146 A TW 105104146A TW 105104146 A TW105104146 A TW 105104146A TW I585910 B TWI585910 B TW I585910B
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Taiwan
Prior art keywords
wafer
layer
active surface
active
fan
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TW105104146A
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English (en)
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TW201729360A (zh
Inventor
洪菁蔚
范文正
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力成科技股份有限公司
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Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW105104146A priority Critical patent/TWI585910B/zh
Priority to US15/277,349 priority patent/US20170229426A1/en
Application granted granted Critical
Publication of TWI585910B publication Critical patent/TWI585910B/zh
Publication of TW201729360A publication Critical patent/TW201729360A/zh

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Description

扇出型背對背晶片堆疊封裝構造及其製造方法
本發明係有關於半導體晶片封裝領域，特別係有關於一種扇出型背對背晶片堆疊封裝構造及其製造方法。
由於半導體封裝材料的熱膨脹係數的不匹配，來自熱應力造成的封裝翹曲將是一個嚴峻的課題。習知晶片堆疊封裝構造係將多個熱膨脹係數較小的半導體晶片3D堆疊方式設置於熱膨脹係數較大的印刷線路板，導致封裝翹曲問題更為嚴重。
近來有人提出扇出式晶圓級封裝構造(fan-out wafer level package,FOWLP)與扇出式面板等級封裝構造(fan-out panel level package,FOPLP)，以晶圓承載系統(Wafer Support System,WSS)或面板承載系統(Panel Support System,PSS)等暫時載板作為封裝製程中的晶片承載件，以重配置線路層作為晶片之訊號延伸，在最終封裝產品再予以移除暫時載板，藉此可以省略基板而更加的封裝薄化，並且線路可以更加的微間距與密集化。雖然可以省略基板結構進而減少了基板對於封裝翹曲問題的影響，但是模封厚度的降低與基板/面板等級的大面積模封，這會產生了在封裝製程中在移除暫時載板之步驟之後至鋸切單離步驟之前的製程 封裝翹曲問題。
為了解決上述之問題，本發明之主要目的係在於提供一種扇出型背對背晶片堆疊封裝構造及其製造方法，實現了無基板多晶片背對背堆疊的結構平衡(structure balance)與降低封裝翹曲的薄型封裝型態。
本發明之次一目的係在於提供一種扇出型背對背晶片堆疊封裝構造及其製造方法，具有一次模封(one time molding)、一次雙面電鍍重配置線路層(one time double side RDL plating)之優點，以達到減少扇出型封裝之製程步驟。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種扇出型背對背晶片堆疊封裝構造，其係包含一第一晶片、一第二晶片、一封膠層、複數個模封導通孔、一第一重配置線路層以及一第二重配置線路層。該第一晶片係具有一第一主動面、一第一背面以及複數個第一側面，該第一主動面係設置有複數個第一銲墊。該第二晶片係具有一第二主動面、一第二背面以及複數個第二側面，該第二主動面係設置有複數個第二銲墊，該第二晶片係堆疊在該第一晶片上，該第一背面與該第二背面之間形成有一晶片貼附層。該封膠層係同時包覆該第一晶片之該些第一側面與該第二晶片之該些第二側面，該封膠層之厚度係不大於該第一晶片與該第二晶片之堆疊高度，以顯露該第一主動面與該第二主動面，該封膠層係具有一由該第一主動 面擴張之第一周邊表面與一由該第二主動面擴張之第二周邊表面。該些模封導通孔係形成於該封膠層中，每一模封導通孔係具有一第一端部與一第二端部，該些第一端部係顯露在該第一周邊表面，該些第二端部係顯露在該第二周邊表面。該第一重配置線路層係形成在該第一主動面上並延伸至該第一周邊表面，以連接該些第一銲墊至對應之該些第一端部。該第二重配置線路層係形成在該第二主動面上並延伸至該第二周邊表面，以連接該些第二銲墊至對應之該些第二端部。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述扇出型背對背晶片堆疊封裝構造中，該些模封導通孔係可為半圓錐狀。
在前述扇出型背對背晶片堆疊封裝構造中，係可另包含一第一保護層與一第二保護層，該第一保護層係可形成於該第一主動面與該第一周邊表面上，以覆蓋該第一重配置線路層，該第二保護層係可形成於該第二主動面與該第二周邊表面上，以覆蓋該第二重配置線路層，故該第一保護層與該第二保護層係可分別保護該第一重配置線路層與該第二重配置線路層，使得該第一重配置線路層與該第二重配置線路層之線路不外露。
在前述扇出型背對背晶片堆疊封裝構造中，係可另包含複數個銲球，其係設置於該第二重配置線路層上或設置於該第一重配置線路層上，故該些銲球係不需要接合於基板。
在前述扇出型背對背晶片堆疊封裝構造中，可另包含一第三晶片及一第四晶片。該第三晶片係具有一第三主動面、一第三背面以及複數個第三側面，該第三主動面係設置有複數個第三銲墊；該第四晶片係具有一第四主動面、一第四背面以及複數個第四側面，該第四主動面係設置有複數個第四銲墊，該第四晶片係堆疊在該第三晶片上，該第三背面與該第四背面之間形成有一第二晶片貼附層；其中，該第一重配置線路層係更形成在該第三主動面上並延伸至該第一周邊表面，以連接該些第三銲墊至對應之該些第一端部，該第二重配置線路層係更形成在該第四主動面上並延伸至該第二周邊表面，以連接該些第四銲墊至對應之該些第二端部。
在前述扇出型背對背晶片堆疊封裝構造中，該第一晶片與該第二晶片係可為實質相同，並使該晶片貼附層位於該封膠層之中間層，藉以達到應力平衡。藉由上述的技術手段，本發明可藉由背對背堆疊之晶片組合在單一封裝構造中，使得該晶片堆疊封裝構造具有更薄的封裝厚度、更穩定的抗翹曲能力與抵抗線路線路的特性。
T1‧‧‧封膠層之厚度
T2‧‧‧第一晶片與第二晶片之堆疊高度
10‧‧‧暫時載板
11‧‧‧載體平面
20‧‧‧切割刀具
30‧‧‧晶圓
100‧‧‧晶片堆疊封裝構造
110‧‧‧第一晶片
111‧‧‧第一主動面
112‧‧‧第一背面
113‧‧‧第一側面
114‧‧‧第一銲墊
120‧‧‧第二晶片
121‧‧‧第二主動面
122‧‧‧第二背面
123‧‧‧第二側面
124‧‧‧第二銲墊
130‧‧‧封膠層
131‧‧‧第一周邊表面
132‧‧‧第二周邊表面
133‧‧‧外周緣
140‧‧‧模封導通孔
141‧‧‧第一端部
142‧‧‧第二端部
150‧‧‧第一重配置線路層
160‧‧‧第二重配置線路層
170‧‧‧晶片貼附層
181‧‧‧第一保護層
182‧‧‧第二保護層
190‧‧‧銲球
200‧‧‧晶片堆疊封裝構造
210‧‧‧第三晶片
211‧‧‧第三主動面
212‧‧‧第三背面
213‧‧‧第三側面
214‧‧‧第三銲墊
220‧‧‧第四晶片
221‧‧‧第四主動面
222‧‧‧第四背面
223‧‧‧第四側面
224‧‧‧第四銲墊
271‧‧‧第二晶片貼附層
第1圖：依據本發明之第一具體實施例，一種扇出型背對背晶片堆疊封裝構造之截面示意圖。
第2圖：依據本發明之第一具體實施例，繪示供該扇出型背對背晶 片堆疊封裝構造中晶片使用之一晶圓示意圖。
第3A至3I圖：依據本發明之第一具體實施例，繪示該扇出型背對背晶片堆疊封裝構造之製作方法中各主要步驟之元件截面示意圖。
第4圖：依據本發明之第二具體實施例，另一種扇出型背對背晶片堆疊封裝構造之截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種扇出型背對背晶片堆疊封裝構造100舉例說明於第1圖之截面示意圖。第2圖係繪示供該扇出型背對背晶片堆疊封裝構造中晶片使用之一晶圓示意圖。一種扇出型背對背晶片堆疊封裝構造100係包含一第一晶片110、一第二晶片120、一封膠層130、複數個模封導通孔140、一第一重配置線路層150以及一第二重配置線路層160。
請參閱第1圖，該第一晶片110係具有一第一主動面111、一第一背面112以及複數個第一側面113，該第一主動面111 係設置有複數個第一銲墊114。該第一晶片110之基材係為半導體材料，並在該第一主動面111製作出積體電路。而該些第一銲墊114係為積體電路之連接端點。通常該第一背面112係為平行於該第一主動面111之相對表面。該些第一側面113係垂直於該第一主動面111與該第一背面112。
該第二晶片120係具有一第二主動面121、一第二背面122以及複數個第二側面123，該第二主動面121係設置有複數個第二銲墊124，該第二晶片120係堆疊在該第一晶片110上，該第一背面112與該第二背面122之間形成有一晶片貼附層170。該第二晶片120之基材係為半導體材料，並在該第二主動面121製作出積體電路。而該些第二銲墊124係為積體電路之連接端點。通常該第二背面122係為平行於該第二主動面121之相對表面。該些第二側面123係垂直於該第二主動面121與該第二背面122。較佳地，該第一晶片110與該第二晶片120係可為實質相同，並使該晶片貼附層170位於該封膠層130之中間層，藉以達到應力平衡，以抵抗封裝翹曲。如第2圖所示，該第一晶片110與該第二晶片120係可取自於同一晶圓30或相同的晶圓的已知良好晶粒。
該封膠層130係同時包覆該第一晶片110之該些第一側面113與該第二晶片120之該些第二側面123，該封膠層130之厚度T1係不大於該第一晶片110與該第二晶片120之堆疊高度T2，以顯露該第一主動面111與該第二主動面121。換言之，該封膠層130不會覆蓋至該第一主動面111與該第二主動面121。在本實施例 中，該封膠層130之厚度T1係等於該第一晶片110與該第二晶片120之堆疊高度T2。並且該封膠層130係具有一由該第一主動面111擴張之第一周邊表面131與一由該第二主動面121擴張之第二周邊表面132。該封膠層130可為用於密封晶片之模封熱固化複合材料，主成份可為環氧樹脂(Epoxy Resin)、含矽樹脂(Silicon Resin)或聚醯亞胺樹脂(Polyimide Resin)…等。該第一主動面111與該第一周邊表面131係可為共平面或可有一模封高度差。該第二主動面121與該第二周邊表面132係可為共平面或有一模封高度差。
該些模封導通孔140係形成於該封膠層130中，每一模封導通孔140係具有一第一端部141與一第二端部142，該些第一端部141係顯露在該第一周邊表面131，該些第二端部142係顯露在該第二周邊表面132。在本實施例中，該些模封導通孔140係可為半圓錐狀。較佳地，該第一端部141之面積係可大於該第二端部142之面積。該些模封導通孔140內為導電材料，可填滿或是形成於孔壁。因此，該些模封導通孔140係可以取代貫穿晶片之矽穿孔結構。
該第一重配置線路層150係形成在該第一主動面111上並延伸至該第一周邊表面131，以連接在該第一主動面111上之該些第一銲墊114至對應之該些第一端部141。該第二重配置線路層160係形成在該第二主動面121上並延伸至該第二周邊表面132，以連接該些第二銲墊124至對應之該些第二端部142。因此，藉由該些模封導通孔140電性連接該第一重配置線路層150與該第二重配置線路層160，以使得該晶片堆疊封裝構造100為雙面電 性導通。該第一重配置線路層150與該第二重配置線路層160係不同於習知基板之線路層，而是利用半導體沉積、電鍍與蝕刻設備予以製作。該第一重配置線路層150與該第二重配置線路層160之結構係可為多層式金屬層，例如鈦/銅/銅(Ti/Cu/Cu)、鈦/銅/銅/鎳/金(Ti/Cu/Cu/Ni/Au)等。
更具體地，該扇出型背對背晶片堆疊封裝構造100係可另包含一第一保護層181與一第二保護層182，該第一保護層181係可形成於該第一主動面111與該第一周邊表面131上，以覆蓋該第一重配置線路層150。該第二保護層182係可形成於該第二主動面121與該第二周邊表面132上，以覆蓋該第二重配置線路層160。該第一保護層181係依據該封膠層130、該第一晶片110與該第一重配置線路層150之表面外形而形成，該第一保護層181係可保護該第一重配置線路層150，使得該第一重配置線路層150之線路不外露。該第二保護層182係依據該封膠層130、該第二晶片120與該第二重配置線路層160之表面外形而形成，該第二保護層182係可保護該第二重配置線路層160，使得該第二重配置線路層160之線路不外露。。該第一保護層181與該第二保護層182之材質係可為例如聚亞醯胺(PI)之有機絕緣層，該第一保護層181與該第二保護層182之個別厚度係可約為5微米。此外，複數個銲球190係可設置於第二重配置線路層160上；在不同實施例中，該些銲球190係可設置於該第一重配置線路層150上。
因此，本發明之扇出型背對背晶片堆疊封裝構造係 可實現了無基板多晶片背對背堆疊的結構平衡(structure balance)與降低封裝翹曲的薄型封裝型態。
關於上述扇出型背對背晶片堆疊封裝構造100之製造方法係進一步說明如後，第3A至3I圖係繪示該扇出型背對背晶片堆疊封裝構造之製作方法中各主要步驟之元件截面示意圖。
首先，請參閱第3A圖，設置複數個第一晶片110在一暫時載板10之一載體平面11上，每一第一晶片110係具有一第一主動面111、一第一背面112以及複數個第一側面113，每一第一主動面111係設置有複數個第一銲墊114，該暫時載板10係為晶圓型態或面板型態，並具有可剝離之黏性。在本步驟中，具體地利用取放(pick and place)方式重定位(re-allocate)該些第一晶片110的位置並且該些第一晶片110之該些第一主動面111係朝下貼附於該暫時載板10。
之後，請參閱第3B圖，堆疊複數個第二晶片120在對應之該些第一晶片110上，每一第二晶片120係具有一第二主動面121、一第二背面122以及複數個第二側面123，每一第二主動面121係設置有複數個第二銲墊124，該些第一背面112與對應之該些第二背面122之間形成有一晶片貼附層170。在本步驟中，該些第二晶片120之該些第二主動面121朝上並將該些第二背面122貼附至對應之該些第一背面112。請再參閱第2圖，至少一晶圓30係鋸切成複數個晶片，以提供該些第一晶片110與該些第二晶片120。
之後，請參閱第3C圖，以一次模封(one time molding) 方式形成一封膠層130於該載體平面11上，該封膠層130係同時包覆該些第一晶片110之該些第一側面113與該些第二晶片120之該些第二側面123，該封膠層130之厚度T1係不大於該些第一晶片110與該些第二晶片120之堆疊高度T2，以顯露該些第一主動面111與該些第二主動面121，對應於每一晶片堆疊體，該封膠層130係具有一由該第一主動面111擴張之第一周邊表面131與一由該第二主動面121擴張之第二周邊表面132。上述「一次模封」係指一次的模封製程形成該封膠層130而使其為單層之一體結構。
之後，請參閱第3D圖，移除該暫時載板10，以顯露該些第一主動面111與該封膠層130之該些第一周邊表面131。其中一種移除該暫時載板10之移除方法係可為UV光照射以去除黏性。由於多個雙晶片背對背堆疊體結合在該封膠層130，並由該晶片貼附層170開始為上下結構對稱，故該封膠層130為應力結構平衡。即使在失去該暫時載板10之承載狀態下，晶圓型態或面板型態的該封膠層130在後續扇出型晶片封裝製程中亦不會產生無法作業的翹曲與變形。因此，後續的一次雙面電鍍重配置線路層(one time double side RDL plating)的操作為可行。
之後，請參閱第3E圖，以已知導通孔形成(via formation)技術形成複數個模封導通孔140於該封膠層130中，每一模封導通孔140係具有複數個第一端部141與複數個第二端部142，該些第一端部141係顯露在該第一周邊表面131，該些第二端部142係顯露在該第二周邊表面132。該些模封導通孔140之形成方 法係包含鑽孔與孔電鍍。。
之後，請參閱第3F圖，以一次雙面電鍍重配置線路層的方式形成一第一重配置線路層150與一第二重配置線路層160，該第一重配置線路層150係形成在該些第一主動面111上並延伸至該些第一周邊表面131，以連接該些第一銲墊114至對應之該些第一端部141，該第二重配置線路層160係形成在該些第二主動面121上並延伸至該些第二周邊表面132，以連接該些第二銲墊124至對應之該些第二端部142。在細部製程中，形成該第一重配置線路層150之晶種層與以及形成該第二重配置線路層160之晶種層與圖案化光阻係個別地形成於該封膠層130之不同表面，在將該封膠層130投置於電鍍槽內，以進行一次雙面電鍍，其過程中該封膠層130係可固定於雙面鏤空的夾持環。在電鍍之後再移除圖案化光阻與外露之晶種層。因此，本步驟係為重配置線路層的雙面形成。該第一重配置線路層150與該第二重配置線路層160的兩者結構係可為相同材質與相同厚度。
請參閱第3G圖，在形成該第一重配置線路層150與該第二重配置線路層160之步驟之後，可形成一第一保護層181與一第二保護層182，該第一保護層181係形成於該些第一主動面111與該些第一周邊表面131上，以覆蓋該第一重配置線路層150，該第二保護層182係形成於該第二主動面121與該第二周邊表面132上，以覆蓋該第二重配置線路層160。該第一保護層181與該第二保護層182之形成係可利用一次雙面沉積、或是多次逐面沉積。舉 例說明如後，該封膠層130係可固定於雙面鏤空的夾持環，在該封膠層130之上下不同表面各印刷形成一層之未固化保護層材料，在以旋塗方式降低未固化保護層材料的厚度，之後經過加熱同時雙面固化與單面曝光顯影，便可達到一次雙面沉積形成之該第一保護層181與該第二保護層182。該第一保護層181與該第二保護層182的兩者結構係可為相同材質與相同厚度。該第二保護層182之圖案開孔係顯露該第二重配置線路層160之外接墊。
請參閱第3H圖，在形成該第一重配置線路層150與該第二重配置線路層160之步驟之後，可另設置複數個銲球190於該第二重配置線路層160上。該些銲球190之形成方法係可為植球回焊或是銲料電鍍回焊，使其接合於該第二重配置線路層160之適當位置。
最後，請參閱第3I圖，單體化切割該封膠層130，以形成複數個扇出型背對背晶片堆疊封裝構造100。可利用一鋸輪之切割刀具20切割該封膠層130之切割道，由該第一周邊表面131貫穿至該第二周邊表面132，以切割出該些扇出型背對背晶片堆疊封裝構造100。通常單體化切割(singulation)方法係為對該封膠層130之鋸切，亦可為雷射切割或蝕刻或上述方法的可能組合。
依據本發明之第二具體實施例，另一種扇出型背對背晶片堆疊封裝構造200係舉例說明於第4圖之截面示意圖，其中對應於第一具體實施例相同名稱與功能之元件以第一具體實施例的元件圖號表示，並且不再贅述其細部相同結構。第二具體實施 例之製程步驟係可大致相同於第一具體實施例如第3A至3I圖所示之製程步驟。一種扇出型背對背晶片堆疊封裝構造200係包含一第一晶片110、一第二晶片120、一封膠層130、複數個模封導通孔140、一第一重配置線路層150以及一第二重配置線路層160，並具有如第一具體實施例所述的細部結構。
該扇出型背對背晶片堆疊封裝構造200係可另包含一第三晶片210及一第四晶片220。該第三晶片210係具有一第三主動面211、一第三背面212以及複數個第三側面213，該第三主動面211係設置有複數個第三銲墊214；該第四晶片220係具有一第四主動面221、一第四背面222以及複數個第四側面223，該第四主動面221係設置有複數個第四銲墊224，該第四晶片220係堆疊在該第三晶片210上，該第三背面212與該第四背面222之間形成有一第二晶片貼附層271；其中，該第一重配置線路層150係更形成在該第三主動面211上並延伸至該第一周邊表面131，以連接該些第三銲墊214至對應之該些第一端部141，該第二重配置線路層160係更形成在該第四主動面221上並延伸至該第二周邊表面132，以連接該些第四銲墊224至對應之該些第二端部142。藉此，達到無基板多晶片堆疊的並排型態在一封裝結構中。
請參閱第4圖，以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
T1‧‧‧封膠層之厚度
T2‧‧‧第一晶片與第二晶片之堆疊高度
100‧‧‧晶片堆疊封裝構造
110‧‧‧第一晶片
111‧‧‧第一主動面
112‧‧‧第一背面
113‧‧‧第一側面
114‧‧‧第一銲墊
120‧‧‧第二晶片
121‧‧‧第二主動面
122‧‧‧第二背面
123‧‧‧第二側面
124‧‧‧第二銲墊
130‧‧‧封膠層
131‧‧‧第一周邊表面
132‧‧‧第二周邊表面
133‧‧‧外周緣
140‧‧‧模封導通孔
141‧‧‧第一端部
142‧‧‧第二端部
150‧‧‧第一重配置線路層
160‧‧‧第二重配置線路層
170‧‧‧晶片貼附層
181‧‧‧第一保護層
182‧‧‧第二保護層
190‧‧‧銲球

Claims (10)

  1. 一種扇出型背對背晶片堆疊封裝構造，包含：一第一晶片，係具有一第一主動面、一第一背面以及複數個第一側面，該第一主動面係設置有複數個第一銲墊；一第二晶片，係具有一第二主動面、一第二背面以及複數個第二側面，該第二主動面係設置有複數個第二銲墊，該第二晶片係堆疊在該第一晶片上，該第一背面與該第二背面之間形成有一晶片貼附層，其中該第一晶片與該第二晶片係為實質相同，且該第一晶片的該些第一側面切齊於該第二晶片的該些第二側面；一封膠層，係同時包覆該第一晶片之該些第一側面與該第二晶片之該些第二側面，該封膠層之厚度係不大於該第一晶片與該第二晶片之堆疊高度，以顯露該第一主動面與該第二主動面，該封膠層係具有一由該第一主動面擴張之第一周邊表面與一由該第二主動面擴張之第二周邊表面；複數個模封導通孔，係形成於該封膠層中，每一模封導通孔係具有一第一端部與一第二端部，該些第一端部係顯露在該第一周邊表面，該些第二端部係顯露在該第二周邊表面；一第一重配置線路層，係形成在該第一主動面上並延伸至該第一周邊表面，以連接該些第一銲墊至對應之該些第一端部；以及一第二重配置線路層，係形成在該第二主動面上並延伸至該第二周邊表面，以連接該些第二銲墊至對應之該些第二端部。
  2. 如申請專利範圍第1項所述之扇出型背對背晶片堆疊封裝構造，其中該些模封導通孔係為半圓錐狀。
  3. 如申請專利範圍第1項所述之扇出型背對背晶片堆疊封裝構造，另包含：一第一保護層，係形成於該第一主動面與該第一周邊表面上，以覆蓋該第一重配置線路層；以及一第二保護層，係形成於該第二主動面與該第二周邊表面上，以覆蓋該第二重配置線路層。
  4. 如申請專利範圍第1項所述之扇出型背對背晶片堆疊封裝構造，另包含複數個銲球，係設置於該第二重配置線路層上或設置於該第一重配置線路層上。
  5. 如申請專利範圍第1項所述之扇出型背對背晶片堆疊封裝構造，另包含：一第三晶片，係具有一第三主動面、一第三背面以及複數個第三側面，該第三主動面係設置有複數個第三銲墊；以及一第四晶片，係具有一第四主動面、一第四背面以及複數個第四側面，該第四主動面係設置有複數個第四銲墊，該第四晶片係堆疊在該第三晶片上，該第三背面與該第四背面之間形成有一第二晶片貼附層；其中，該第一重配置線路層係更形成在該第三主動面上並延伸至該第一周邊表面，以連接該些第三銲墊至對應之該些第一端部，該第二重配置線路層係更形成在該第四主動面上並延伸至該第二周邊表面，以連接該些第四銲墊至對應之該些第二端部。
  6. 如申請專利範圍第1至5項任一項所述之扇出型背對背晶片堆疊封裝構造，其中該晶片貼附層位於該封膠層之厚度一半的位置。
  7. 一種扇出型背對背晶片堆疊封裝構造之製造方法，包含：設置複數個第一晶片在一暫時載板之一載體平面上，每一第一晶片係具有一第一主動面、一第一背面以及複數個第一側面，每一第一主動面係設置有複數個第一銲墊，該暫時載板係為晶圓型態或面板型態；堆疊複數個第二晶片在對應之該些第一晶片上，每一第二晶片係具有一第二主動面、一第二背面以及複數個第二側面，每一第二主動面係設置有複數個第二銲墊，該些第一背面與對應之該些第二背面之間形成有一晶片貼附層，其中該些第一晶片與該些第二晶片係為實質相同，且各該第一晶片的該些第一側面切齊於對應的該第二晶片的該些第二側面；形成一封膠層於該載體平面上，該封膠層係同時包覆該些第一晶片之該些第一側面與該些第二晶片之該些第二側面，該封膠層之厚度係不大於該些第一晶片與該些第二晶片之堆疊高度，以顯露該些第一主動面與該些第二主動面，對應於每一晶片堆疊體，該封膠層係具有一由該第一主動面擴張之第一周邊表面與一由該第二主動面擴張之第二周邊表面；移除該暫時載板，以顯露該些第一主動面與該封膠層之該些第一周邊表面； 形成複數個模封導通孔於該封膠層中，每一模封導通孔係具有複數個第一端部與複數個第二端部，該些第一端部係顯露在該第一周邊表面，該些第二端部係顯露在該第二周邊表面；形成一第一重配置線路層與一第二重配置線路層，該第一重配置線路層係形成在該些第一主動面上並延伸至該些第一周邊表面，以連接該些第一銲墊至對應之該些第一端部，該第二重配置線路層係形成在該些第二主動面上並延伸至該些第二周邊表面，以連接該些第二銲墊至對應之該些第二端部；以及單體化切割該封膠層，以形成複數個扇出型背對背晶片堆疊封裝構造。
  8. 如申請專利範圍第7項所述之扇出型背對背晶片堆疊封裝構造之製造方法，其中在形成該第一重配置線路層與該第二重配置線路層之步驟之後，另包含之步驟為：形成一第一保護層與一第二保護層，該第一保護層係形成於該些第一主動面與該些第一周邊表面上，以覆蓋該第一重配置線路層，該第二保護層係形成於該第二主動面與該第二周邊表面上，以覆蓋該第二重配置線路層；以及設置複數個銲球於該第二重配置線路層上。
  9. 如申請專利範圍第7項所述之扇出型背對背晶片堆疊封裝構造之製造方法，其中該些模封導通孔係為半圓錐狀。
  10. 如申請專利範圍第7、8或9項所述之扇出型背對背晶片堆疊封裝構造之製造方法，其中該晶片貼附層位於該封膠層之厚 度一半的位置。
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