KR960009107A - 반도체장치와 그 제조방법 - Google Patents
반도체장치와 그 제조방법 Download PDFInfo
- Publication number
- KR960009107A KR960009107A KR1019950023417A KR19950023417A KR960009107A KR 960009107 A KR960009107 A KR 960009107A KR 1019950023417 A KR1019950023417 A KR 1019950023417A KR 19950023417 A KR19950023417 A KR 19950023417A KR 960009107 A KR960009107 A KR 960009107A
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/161—Tapered edges
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- High Energy & Nuclear Physics (AREA)
- Plasma & Fusion (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/283,162 US5444007A (en) | 1994-08-03 | 1994-08-03 | Formation of trenches having different profiles |
US8/283162 | 1994-08-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960009107A true KR960009107A (ko) | 1996-03-22 |
KR100202277B1 KR100202277B1 (ko) | 1999-06-15 |
Family
ID=23084805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950023417A KR100202277B1 (ko) | 1994-08-03 | 1995-07-31 | 반도체장치와 그 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5444007A (ko) |
EP (2) | EP0696059B1 (ko) |
JP (1) | JP3426797B2 (ko) |
KR (1) | KR100202277B1 (ko) |
DE (1) | DE69534584T2 (ko) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07221041A (ja) * | 1994-01-28 | 1995-08-18 | Sony Corp | 半導体装置の製造方法 |
US5444007A (en) * | 1994-08-03 | 1995-08-22 | Kabushiki Kaisha Toshiba | Formation of trenches having different profiles |
JP2735041B2 (ja) * | 1995-07-28 | 1998-04-02 | 日本電気株式会社 | 半導体装置およびその製造方法 |
CA2197400C (en) * | 1997-02-12 | 2004-08-24 | Universite De Sherbrooke | Fabrication of sub-micron silicide structures on silicon using resistless electron beam lithography |
US6261938B1 (en) | 1997-02-12 | 2001-07-17 | Quantiscript, Inc. | Fabrication of sub-micron etch-resistant metal/semiconductor structures using resistless electron beam lithography |
JP3519579B2 (ja) * | 1997-09-09 | 2004-04-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US6103635A (en) * | 1997-10-28 | 2000-08-15 | Fairchild Semiconductor Corp. | Trench forming process and integrated circuit device including a trench |
US5998301A (en) * | 1997-12-18 | 1999-12-07 | Advanced Micro Devices, Inc. | Method and system for providing tapered shallow trench isolation structure profile |
US6133615A (en) * | 1998-04-13 | 2000-10-17 | Wisconsin Alumni Research Foundation | Photodiode arrays having minimized cross-talk between diodes |
IT1301729B1 (it) * | 1998-06-16 | 2000-07-07 | St Microelectronics Srl | Processo per il drogaggio selettivo di una fetta di materialesemiconduttore mediante impiantazione ionica. |
US6326300B1 (en) | 1998-09-21 | 2001-12-04 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method |
DE19845003C1 (de) * | 1998-09-30 | 2000-02-10 | Siemens Ag | Vertikaler Feldeffekttransistor mit innenliegendem ringförmigen Gate und Herstellverfahren |
KR100280516B1 (ko) * | 1998-11-04 | 2001-03-02 | 김영환 | 반도체 소자의 분리 구조 제조방법 및 반도체 소자 제조방법 |
US6331873B1 (en) | 1998-12-03 | 2001-12-18 | Massachusetts Institute Of Technology | High-precision blooming control structure formation for an image sensor |
US6287961B1 (en) | 1999-01-04 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6307247B1 (en) * | 1999-07-12 | 2001-10-23 | Robert Bruce Davies | Monolithic low dielectric constant platform for passive components and method |
KR100355034B1 (ko) | 1999-07-15 | 2002-10-05 | 삼성전자 주식회사 | 선택적 에피택셜 성장층을 가진 반도체 장치 및 그 소자분리방법 |
DE10115912A1 (de) * | 2001-03-30 | 2002-10-17 | Infineon Technologies Ag | Verfahren zur Herstellung einer Halbleiteranordnung und Verwendung einer Ionenstrahlanlage zur Durchführung des Verfahrens |
US20030064550A1 (en) * | 2001-09-28 | 2003-04-03 | Layman Paul Arthur | Method of ion implantation for achieving desired dopant concentration |
US6780730B2 (en) * | 2002-01-31 | 2004-08-24 | Infineon Technologies Ag | Reduction of negative bias temperature instability in narrow width PMOS using F2 implantation |
DE10219123B4 (de) * | 2002-04-29 | 2004-06-03 | Infineon Technologies Ag | Verfahren zur Strukturierung keramischer Schichten auf Halbleitersubstanzen mit unebener Topographie |
US6960510B2 (en) * | 2002-07-01 | 2005-11-01 | International Business Machines Corporation | Method of making sub-lithographic features |
KR100598035B1 (ko) * | 2004-02-24 | 2006-07-07 | 삼성전자주식회사 | 전하 전송 이미지 소자의 제조 방법 |
US7332737B2 (en) * | 2004-06-22 | 2008-02-19 | Micron Technology, Inc. | Isolation trench geometry for image sensors |
KR100675285B1 (ko) * | 2005-10-10 | 2007-01-29 | 삼성전자주식회사 | 수직 트랜지스터를 갖는 반도체소자 및 그 제조방법 |
KR100710187B1 (ko) * | 2005-11-24 | 2007-04-20 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US7825031B2 (en) * | 2007-09-14 | 2010-11-02 | Qimonda Ag | Method of fabricating a semiconductor device |
US8679929B2 (en) * | 2011-12-06 | 2014-03-25 | Texas Instruments Incorporated | On current in one-time-programmable memory cells |
KR102491093B1 (ko) | 2017-08-21 | 2023-01-20 | 삼성전자주식회사 | 패턴 형성 방법 |
KR102374697B1 (ko) * | 2017-09-07 | 2022-03-15 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
KR20210076920A (ko) * | 2018-10-19 | 2021-06-24 | 커먼웰쓰 사이언티픽 앤드 인더스트리얼 리서치 오가니제이션 | 다중 스텝 엣지 제조 |
US11201154B2 (en) | 2019-12-27 | 2021-12-14 | Micron Technology, Inc. | Methods of forming an apparatus including device structures including pillar structures, and related memory devices, and electronic systems |
Family Cites Families (29)
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US3769109A (en) * | 1972-04-19 | 1973-10-30 | Bell Telephone Labor Inc | PRODUCTION OF SiO{11 {11 TAPERED FILMS |
US3808068A (en) * | 1972-12-11 | 1974-04-30 | Bell Telephone Labor Inc | Differential etching of garnet materials |
DE2341154C2 (de) * | 1973-08-14 | 1975-06-26 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung einer Zweiphasen-Ladungsverschiebeanordnung |
US4044452A (en) * | 1976-10-06 | 1977-08-30 | International Business Machines Corporation | Process for making field effect and bipolar transistors on the same semiconductor chip |
US4232439A (en) * | 1976-11-30 | 1980-11-11 | Vlsi Technology Research Association | Masking technique usable in manufacturing semiconductor devices |
US4093503A (en) * | 1977-03-07 | 1978-06-06 | International Business Machines Corporation | Method for fabricating ultra-narrow metallic lines |
US4147564A (en) * | 1977-11-18 | 1979-04-03 | Sri International | Method of controlled surface texturization of crystalline semiconductor material |
US4268347A (en) * | 1979-01-26 | 1981-05-19 | Exxon Research & Engineering Co. | Low reflectivity surface formed by particle track etching |
US4377437A (en) * | 1981-05-22 | 1983-03-22 | Bell Telephone Laboratories, Incorporated | Device lithography by selective ion implantation |
US4495025A (en) * | 1984-04-06 | 1985-01-22 | Advanced Micro Devices, Inc. | Process for forming grooves having different depths using a single masking step |
US4719498A (en) * | 1984-05-18 | 1988-01-12 | Fujitsu Limited | Optoelectronic integrated circuit |
JPH0722145B2 (ja) * | 1984-07-31 | 1995-03-08 | 株式会社リコー | 半導体装置の製造方法 |
DE3682195D1 (de) * | 1985-09-27 | 1991-11-28 | Unisys Corp | Verfahren zur herstellung einer konischen kontaktoeffnung in polyimid. |
EP0218039B1 (de) * | 1985-09-30 | 1990-11-07 | Siemens Aktiengesellschaft | Verfahren zur Übertragung feinster Fotolackstrukturen |
NL8502765A (nl) * | 1985-10-10 | 1987-05-04 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4679311A (en) * | 1985-12-12 | 1987-07-14 | Allied Corporation | Method of fabricating self-aligned field-effect transistor having t-shaped gate electrode, sub-micron gate length and variable drain to gate spacing |
CA1218956A (en) * | 1986-01-28 | 1987-03-10 | Thomas Abraham | Process for plasma etching polysilicon to produce rounded profile islands |
US4652334A (en) * | 1986-03-06 | 1987-03-24 | General Motors Corporation | Method for patterning silicon dioxide with high resolution in three dimensions |
FR2610141B1 (fr) * | 1987-01-26 | 1990-01-19 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit |
US5298450A (en) * | 1987-12-10 | 1994-03-29 | Texas Instruments Incorporated | Process for simultaneously fabricating isolation structures for bipolar and CMOS circuits |
JPH0239429A (ja) * | 1988-07-28 | 1990-02-08 | Matsushita Electron Corp | 半導体装置の製造方法 |
US4978418A (en) * | 1988-08-18 | 1990-12-18 | The United States Of America As Represented By The United States Department Of Energy | Controlled ion implant damage profile for etching |
US5296392A (en) * | 1990-03-06 | 1994-03-22 | Digital Equipment Corporation | Method of forming trench isolated regions with sidewall doping |
US5130268A (en) * | 1991-04-05 | 1992-07-14 | Sgs-Thomson Microelectronics, Inc. | Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby |
JP3109059B2 (ja) * | 1991-07-23 | 2000-11-13 | ソニー株式会社 | ドライエッチング方法 |
JPH05144933A (ja) * | 1991-11-19 | 1993-06-11 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH05304169A (ja) * | 1992-04-28 | 1993-11-16 | Nec Corp | 半導体装置の製造方法 |
US5308786A (en) * | 1993-09-27 | 1994-05-03 | United Microelectronics Corporation | Trench isolation for both large and small areas by means of silicon nodules after metal etching |
US5444007A (en) * | 1994-08-03 | 1995-08-22 | Kabushiki Kaisha Toshiba | Formation of trenches having different profiles |
-
1994
- 1994-08-03 US US08/283,162 patent/US5444007A/en not_active Expired - Lifetime
-
1995
- 1995-06-07 US US08/467,541 patent/US5753961A/en not_active Expired - Fee Related
- 1995-07-27 JP JP19160695A patent/JP3426797B2/ja not_active Expired - Fee Related
- 1995-07-31 KR KR1019950023417A patent/KR100202277B1/ko not_active IP Right Cessation
- 1995-08-03 EP EP95112234A patent/EP0696059B1/en not_active Expired - Lifetime
- 1995-08-03 EP EP05007943A patent/EP1569265A3/en not_active Withdrawn
- 1995-08-03 DE DE69534584T patent/DE69534584T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5444007A (en) | 1995-08-22 |
EP1569265A2 (en) | 2005-08-31 |
EP0696059A3 (en) | 2001-08-01 |
EP0696059A2 (en) | 1996-02-07 |
JPH08172172A (ja) | 1996-07-02 |
EP1569265A3 (en) | 2008-06-04 |
JP3426797B2 (ja) | 2003-07-14 |
US5753961A (en) | 1998-05-19 |
DE69534584D1 (de) | 2005-12-15 |
DE69534584T2 (de) | 2006-07-20 |
KR100202277B1 (ko) | 1999-06-15 |
EP0696059B1 (en) | 2005-11-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
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