KR101814683B1 - A two-dimensional stretchable and bendable device - Google Patents

Abstract

In one aspect, the present invention provides tensionable, and optionally printable, components, such as semiconductor or electronic circuits, that can provide excellent performance even when tensioned, compressed, warped, or otherwise deformed, and And provide related methods for manufacturing or controlling such tensionable components. In some applications, the preferred stretchable semiconductors and electronic circuits are not only tensile but also flexible, and thus are capable of significant elongation, bending, bending, or other variations along one or more axes. In addition, the tensile semiconductors and electronic circuits of the present invention are applied to a wide variety of device configurations to provide fully flexible electronic and optical electronic devices.

Description

The present invention relates to a two-dimensional stretchable and bendable device,

The present invention relates to tensionable components and methods of making the same.

This application claims the benefit of U.S. Provisional Application No. 60 / 944,626, filed June 18, 2007, and U.S. Provisional Application No. 60 / 824,683, filed September 6, 2006.

Since the first demonstration of a printed transistor, the entire polymer, in 1994, a promising new class of electronic systems including flexible integrated electronic components on plastic substrates has received much attention. [Garnier, F., Hajlaoui, R., Yassar, A. and Srivastava P., Science, Vol. 265, pgs 1684-1686] Recently, research into materials has been directed toward the development of new materials capable of solution processing for conductors, dielectrics and semiconductor elements for flexible plastic electronic devices. However, advances in the field of flexible electronics are not only driven by the development of new materials capable of solution processing, but also by new geometries of device components, methods of processing efficient devices and component parts, and high resolution Lt; / RTI > patterning techniques. Such materials, device configurations and fabrication methods are expected to play a key role in the emerging new types of flexible integrated electronic devices, systems and circuits.

Several important advantages provided by flexible electronics technology are of interest to the field of flexible electronics. For example, the inherently flexible nature of these substrate materials enables them to be integrated into many forms that provide a number of useful device configurations that are not possible with breakable conventional silicon-based electronic devices. Further, the combination of the flexible materials and the flexible substrates with the solution process enables manufacturing by a printing technique capable of producing electronic devices on a large area substrate at a high speed, which is continuous and high-speed.

However, the design and manufacture of flexible electronic devices that exhibit excellent electronic performance presents many important challenges. First, well-developed methods for making conventional silicon-based electronic devices are not compatible with most flexible materials. For example, conventional high purity inorganic semiconductor components such as monocrystalline silicon or lowermanium semiconductors are typically treated by thin film growth at temperatures (> 1000 DEG C) that significantly exceed the melting point or decomposition temperature of most plastics materials. In addition, most inorganic semiconductors are essentially insoluble in convenient solvents that enable solution-based processing and delivery. Secondly, although many amorphous silicon, organic or hybrid organic-inorganic semiconductors can be integrated into flexible materials and are compatible and can be processed at relatively low temperatures, these materials can provide integrated electronic devices They do not have the electronic properties that they can provide. For example, thin film transistors with semiconductor elements made of these materials exhibit a smaller field effect mobility by about three orders of magnitude than complementary monocrystalline silicon-based elements. As a result of these limitations, flexible electronic devices are currently limited to certain applications that do not require high performance, such as switching elements for active matrix flat panel displays with non-emissive pixels and use in light emitting diodes.

BACKGROUND OF THE INVENTION Flexible electronic circuits are actively researched fields in a number of fields including electro-active surfaces of arbitrary shape such as flexible displays, electronic fibers and electronic skin. These circuits can not be sufficiently matched to the environment because the conductive parts can not be stretched in response to conformational changes. Therefore, such flexible circuits are prone to damage, electronic deterioration is prone to occur, and reliability may be degraded in violent and / or repeated shape changes. Flexible circuits require tensile and bendable interconnections that remain intact during the cycle through tension and relaxation.

Flexible and resilient conductors are typically made by inserting metal particles into an elastomer such as silicone. Such conductive rubbers are mechanically resilient and have electrical conductivity. Disadvantages of conductive rubbers include high electrical resistivity, significant resistance change when tensioned, thereby resulting in overall poor interconnect performance and reliability.

Gray et al. Discuss the fabrication of elastomeric electronic devices using microfabricated tortuous wires wrapped in a silicone elastomer capable of linear tensioning up to 54% while maintaining conductivity. In that study, the wires are shaped like a spiral spring. In contrast to straight wire broken at low strains (e.g., 2.4%), the twisted wires retained conductivity even at very high strains (e.g., 27.2%). Such wire geometry depends on the ability of the wire to be stretched by bending rather than by tension. The system suffers from limitations in its ability to precisely and controllably pattern different patterns in additional plates, thereby suffering from limitations in the ability to fit the system to different deformation and bending areas.

Studies have shown that elastically stretchable metal interconnects experience increased resistance to mechanical deformation. (Mandlik et al., 2006). Mandlik et al. Attempted to minimize this change in resistance by depositing a metal film on a finely patterned surface in the form of a pyramid. However, the research relies on a relief structure to create microcracks that give tensile potential to thin metal wires. The microcracks facilitate the elastic deformation of the metal through twisting and deformation out of plane. However, such metal cracks are incompatible with the thick metal film and can instead be compatible rather with a narrow range of metal films deposited on top of the patterned elastomer (e.g., less than 30 nm).

One method of imparting tensile potential to metal interconnects is to pre-strain the substrate (e.g., 15% to 25%) while applying a conductor (e.g., metal), and then spontaneously bend the pre- Thereby inducing a wave in the metal conductor interconnect. (2004), Jones et al. (2000), and Bowden et al. (1998)). Lacour et al. (2003) found that the spontaneous wrinkled gold stripe (Compared to a few percent of the gold film breakage strain on an elastic substrate) to produce gold (hereinafter referred to as " gold stripe "). However, the research has used a relatively thin layer of metal film (e.g., about 105 nm) and is relatively limited in that the system can potentially make electrical conductors that can be stretched by about 10% .

It is evident from the above that there is a need for device components and interconnects with improved tensile, electrical and related processes to quickly and reliably produce tensile interconnects having a variety of different configurations . Advances in the field of flexible electronics are expected to play a crucial role in a number of important emerging and established technologies. However, the success of this application of flexible electronic technology has led to the development of devices that exhibit excellent electronic, mechanical and optical properties in flexed, deformed and bent form, and novel materials for fabricating integrated electronic circuits, And on the continued development of commercially viable manufacturing routes. In particular, high performance, mechanically extensible materials and device configurations are required to exhibit useful electronic and mechanical properties in their tensile or contracted form.

The present invention provides tensionable devices and device components such as semiconductors and tensile electronic devices, and circuits.

Electronic devices and device parts that are tensionable, bendable, and conformable are required to make electronic devices suitable for printing on various curved surfaces. Shape-conforming devices have a variety of applications ranging from flexible displays and biological and physical sensors that can be matched from electronic fibers. Accordingly, embodiments of the present invention are flexible and bendable electronic devices, component parts of the device, and related methods for manufacturing flexible and bendable devices. Such flexibility and bendability can be achieved by providing an interconnect or semiconductor film having a wavy buckled geometry. Such a geometry provides a means to ensure that the system is tensionable and bendable without negatively impacting performance even under vigorous and repetitive tension and / or bending cycles. The methods may also be used to provide precise and accurate geometry construction capabilities (e.g., mechanical properties) such that the physical properties (e.g., tensile, bendability) of the components of the device and / or device can be tailored to the operating conditions of the system . Another aspect of the present invention are tensionable components having physical properties that are at least partially associated with deformation such that the parameter can be adjusted by application of a varying amount of deformation of the component.

The arrangement of the device components may be connected to one another by buckled components or interconnects to facilitate relative independent movement of the device components relative to one another. However, the local regions in the array may have different bending or tensile requirements compared to other regions. The devices and methods provided herein may be used, for example, as a buckling component that includes the dimensions, periodicity, amplitude, orientation, and total number of components or interconnects within a region, Facilitating the construction of a flexible system that may have localized deviations in the geometry of the interconnects. Creating multiple components or interconnects with controlled orientation facilitates tailoring the components or interconnections to the operating conditions of the device.

In one embodiment, the present invention is a tensionable component of an apparatus, the component comprising a first end, a second end and a central region located between the first end and the second end. The component is supported by a substrate, wherein a first end and a second end of the component are coupled to the substrate, and at least a portion of the central region of the component has a bent configuration. In one aspect, the central region of the component is not in physical contact with the substrate. In another aspect, the central region of the component is deformed. In one aspect, the deformation in the central region is less than 10%, between 0.1% and 5%, between 0.1% and 2%, or any sub-range thereof.

In one embodiment, the central portion of the tensionable component may be curved or arc-shaped. In one aspect, the curve has an amplitude of between about 100 nm and 1 mm. In one aspect, the number of distinct components or interconnecting coupling regions may be more than two, for example, three, four, or five. In this aspect, the central portion between the first component end and the second component end is in the form of a plurality of curved subregions so as to form a plurality of distinct curved subregions that do not physically contact the substrate It is actually subdivided. In such an arrangement, the amplitude and / or periodicity may be constant or may vary over the entire longitudinal length of the component or interconnect. The component itself may be in any form, such as a film, wire, or ribbon. When the component is a ribbon, the ribbon may have a thickness of between about 300 nm and 1 mm.

To facilitate positioning of additional component parts, the device components to which the ends of the components are electrically connected may be contact pads. In one aspect, an additional device component is in electrical contact with the contact pad.

The tensionable component can optionally be a metal, a semiconductor, an insulator, a piezoelectric, a ferroelectric, a magnetostrictive material, an electrostrictive material, a superconductor, a ferromagnetic material, lt; RTI ID = 0.0 > thermoelectric < / RTI > material.

In yet another aspect, the tensionable component includes a component of a device selected from the group consisting of an electronic device, an optical device, an opto-electronic device, a mechanical device, and a thermal device.

As mentioned, the substrate supporting the component parts can be any desired material depending on the device into which the component parts are integrated. In one embodiment, the substrate comprises an elastomeric material such as PDMS. The substrate may be reversibly deformable (e.g., PDMS), or may be irreversibly deformable (e.g., plastic). In an embodiment, the substrate itself is a layer or a coating.

In an embodiment, the devices can be further described based on their physical characteristics. For example, there are provided components and / or interconnects that are capable of withstanding up to 25% deformation while maintaining electrical contact and electrical conductivity with the components of the device. In this case, the meaning of "holding" indicates that the electrical conductivity decreases to less than 20%, less than 10%, or less than 5% while accommodating strain.

In another embodiment, the present invention provides a tensionable component or interconnect for forming electrical contact with components of a device. The component or interconnect has a first end, a second end, and a central portion located between the first end and the second end. The ends can be a substrate such as a flexible (e.g., stretchable) substrate, an elastomer substrate, a rigid substrate, a substrate other than an elastomer, or a substrate such as a substrate on which electronic devices, device components, Lt; / RTI > Each end of the component or interconnect may be attached to a different device component that is itself supported by the substrate. The central portion of the component or interconnect has a bent configuration and is not in physical contact with the substrate (e.g., not coupled). In one aspect, this bent configuration is a result of the central portion being under deformation. In this aspect, the bent configuration is such that if a force is applied in such a way as to separate the device components into one or more of the device components (or the substrate lying beneath), the electrical contact between the device components So that the curved portion of the component or interconnect is at least partially straightened and is entirely curved to accommodate the relative movement between the device components. The components or interconnects may optionally be electrically connected to the adjacent islands or contact pads by any one of a number of geometries such as bridges, flower shapes, and / or by multiple components or interconnects. . In one aspect, the device component is in electrical contact with the contact pad.

All of the tensionable components disclosed herein optionally further include adjustable device components of the electronic device. The adjustable component has at least one electronic property that selectively changes with the deformation of the central region provided by the bending configuration. For example, the electronic properties are optionally one or more of electron mobility, resonance frequency, conductance, and resistance. In one aspect, the adjustable device component includes a semiconductor channel of a transistor.

In one embodiment, when the adjustable component has at least one optical property that selectively varies with the level of deformation of the central region provided by the flexure configuration, the component is characterized by a strain coefficient optical coupling. Examples of strain modulus optical coupling include, but are not limited to, the refractive index of the adjustable device component or the angle of incidence of the electromagnetic radiation incident beam with respect to the surface of the central region of the tensionable component. In another embodiment, the adjustable device component comprises a waveguide, an optical modulator, an optical switch or an optical filter.

In another embodiment, the tensionable component is an adjustable device component of a device having a thermal conductivity that selectively varies with the level of deformation of the central region provided by the flexure configuration.

In another embodiment, the tensionable component is a thermal insulation component of the device, and the central region is not in physical contact with the substrate. In one aspect of this embodiment, the central region is not in thermal contact with the substrate, and the central region supports one or more of the device components, thereby supporting one or more devices The component parts provide thermal insulation from the substrate. A useful application for this aspect is for devices that are long wavelength imaging systems.

In yet another embodiment, the tensionable component is an actuator of a mechanical device, wherein the central region is curved and has an amplitude that can be modulated by compressing or stretching the tensionable component or by applying an electrical potential to the central region . Useful applications of this embodiment are mechanical devices selected from the group consisting of microelectromechanical devices, nanoelectromechanical devices, and microfluidic devices.

In one embodiment, multi-axial tension and bending is provided by incorporating any of the tensionable components disclosed herein into a device array having a plurality of components and three or more device components. In this embodiment, each component provides electrical contact between a pair of device components. Depending on the desired tension, bending and / or compression operating conditions, the device array may have a geometric configuration with a grid, a flower shape, a bridge, or any combination thereof (e.g., a grid in one area and a bridge in the other) Lt; / RTI > Further tension and bendability control is provided by the ability to connect neighboring device components to more than one component (e.g., multiple interconnects), such as two, three, or four components do. For example, a square or rectangular device component may be adjacent to four different device components. If each neighboring pair is connected to two interconnects, the device component will have eight interconnects extending from it.

In one embodiment, the device array has sets of component parts oriented in at least two different directions. For example, in a grid configuration, components may have two directions that are orthogonal or perpendicular to each other to provide the ability to be pulled in two directions. In other implementations, the device arrays may include components that are all aligned with respect to each other. This embodiment may be useful when the tension or bend is confined in a single direction (e.g., bending the electronics fabric to the cylinder surface). Additional bending and / or tensioning capabilities are provided by orienting the components in three or more directions, e.g., three or four directions. In one embodiment, additional control and stability is provided by having the components of the device array located in any number of different layers, such as two neighboring layers.

In one embodiment, the device array is capable of withstanding up to about 150% deformation without breaking. The deformation to be broken is maximized by customizing the number of interconnect geometries, orientation, amplitude, periodicity, and operating conditions (e.g., single axis to multiple axis tensile and / or bending).

The substrate on which the interconnect or device array is supported may have at least a curved portion such as a concave, convex, hemispherical, or a combination thereof. In one embodiment, the device in which the components are integrated may include one or more pullable: photodetector, display, light emitter, photovoltaic, sheet scanner, LED display, semiconductor laser, optical system, Transistors, or integrated circuits.

In yet another embodiment, the present invention relates to various methods for adjusting the properties of a tensionable component of a device. For example, the method of adjustment may comprise providing an apparatus having a tensionable component as disclosed herein. The tensionable component comprising: a first end; A second end; And a silver such as a component having a central region located between the first end and the second end and supported by the substrate. In particular, the first end and the second end of the component are coupled to the substrate, and at least a portion of the central region of the component has a curved configuration and is under a predetermined level of deformation. The level of deformation is modulated in the tensionable component by compressing, stretching and / or bending the tensionable component thereby adjusting the properties of the tensionable component of the device.

In one aspect, the properties are one or more of optical, electrical, and mechanical properties such as optical, mechanical, or electronically coupled strain parameters. Here, the magnitude of each property depends at least in part on the deformation. In another aspect, the property is selected from the group consisting of resonance frequency, electron mobility, resistance, conductance, index of refraction, thermal conductivity, and the angle of incidence of the electromagnetic radiation incident beam to the surface of the central region of the retractable component .

In one embodiment, a method of making a tensionable component of an apparatus is provided. In this embodiment, there is provided an elastomeric substrate having a receiving surface with a first level of deformation, said deformation optionally being zero, compressive or extensional. One or more device components are coupled to a receiving surface having said first level of deformation. A force is applied to the elastomeric substrate to produce a change in the level of deformation from the first level of deformation to a different second level of deformation. As long as a change in the level of deformation within the substrate from a first level to a second level causes the component to bend and thereby create one or more tensionable components, The way in which such changes are achieved is not particularly important. The tensionable components each have a first end coupled to the substrate and a second end and a central region provided in a bent configuration.

The coupling of the device components to the substrate may be by any suitable means. In one embodiment, the combining includes generating a pattern of regions that are not associated with the joined regions of the retractable component. Wherein the area to which the tensionable component is coupled is coupled to the elastomeric substrate and the unbonded area of the tensionable component is not coupled to the elastomeric substrate.

In another aspect, the unbonded areas correspond to the central areas of the tensionable components, and the step of applying the force to the elastomeric substrate is such that at least a portion of the central area of each of the tensionable components is not in physical contact with the substrate Thereby causing the central region to bend. In one aspect, applying the force to the elastomeric substrate causes the central regions to bend such that at least a portion of the central region of each of the tensionable components is not in physical contact with the substrate.

In one embodiment, any method for making a tensionable component includes applying a tensioning component onto the tensionable component, onto a receiving surface of the elastomeric substrate, or onto a receiving surface of the tensionable component and the receiving surface of the elastomeric substrate And forming a pattern.

In yet another embodiment, any methods or devices have an elastomeric substrate having a plurality of compliant regions and a plurality of rigid regions. Such a substrate provides rigidity in flexure to the soft region, which is lower than that of the rigid regions. Optionally the substrate has a first end and a second end of each of the tensionable components coupled to at least one of the rigid regions and a central region of each of the tensionable components coupled to at least one of the soft regions . The use of this type of substrate provides the ability to control the buckling of the components based on the pattern of softness of the underlying substrate.

In one embodiment, the force exerted on the elastomeric substrate is achieved mechanically. In one aspect of this embodiment, a first level of deformation, a second level of deformation, or all of these is accomplished by stretching or compressing the elastomeric substrate, by curing the elastomeric substrate, or by raising or lowering the temperature of the elastomeric substrate Or by thermally expanding or thermally induced contraction of the elastomeric substrate.

In another embodiment, the step of joining one or more of the device components to the receiving surface of the elastomeric substrate comprises the step of deforming the substrate from a deformation of the first level to a deformation of a second level different from the first level Level of force is applied to the elastomeric substrate. Optionally, the bonding is performed after applying a force to the elastomeric substrate that creates a change in the level of deformation of the substrate from a deformation of the first level to a second level of deformation that is different from the first level .

In one implementation, any first-level variant and second-level variant are equal to zero. In one aspect, any of the device components includes interconnects or electrodes.

In another embodiment, the present invention relates to various methods for making interconnections or buckling components that can form electrical contact with the components of the device. In one aspect, the pattern of engagement locations is applied to the elastomeric substrate surface, to the component parts or interconnections, or both. A force is applied to deform the interconnects or components that contact the substrate and the substrate. The pattern of bonding locations provides coupling between the specific component or interconnect locations and the substrate. (By removing the force) to relax the substrate, resulting in buckled components or interconnections. One or more changes in the size of the prestrain, the joint location patterning, the geometry, and the spacing create components or interconnections having different buckled or waved geometries. For example, a "out-of-phase" interconnect geometry is provided if the joining positions are staggered so that neighboring components or interconnects are coupled to the substrate at different locations. Coupling position patterning is by any means known in the art, such as by applying a curable photopolymer to the surface of the elastomeric substrate. The components or interconnects are selectively protected by encapsulating at least a portion of the components or interconnects in an encapsulation material, such as an elastomeric material. The buckled components or interconnects may have any pattern suitable for the application. In one embodiment, the pattern is a grid configuration, a flower configuration, a bridge configuration, or any combination thereof.

The methods and devices may have components of any dimension, such as a thickness in the range of tens of nanometers to about 1 millimeter, or a thickness greater than about 300 nanometers. In one aspect, the buckled component has an amplitude corresponding to a maximum vertical displacement of the interconnect from the substrate, and the amplitude is selected from a range between 100 nm and 1 mm. For component ribbons having length and width, said width, amplitude or said width and amplitude vary selectively along the length of the interconnect. One of the factors affecting the amplitude is the deformation applied to the elastomeric substrate before or after combining the components. Generally, the larger the strain, the greater the amplitude. In one embodiment, a force is applied to produce a deformation in the elastomeric substrate, said deformation being selected from the range between 20% and 100%.

In one embodiment, the component is an interconnect that is electrically connected to the device component. Any of the systems and processes provided herein may be used with a substrate that is capable of being stretched to about 100% without fracture of the component, capable of compressing to about 50%, or bending such that the radius of curvature is only 5 mm . The component may be a metal, a semiconductor including GaAs or Si, an insulator, a piezoelectric, a ferroelectric, a magnetostrictive material, an electrostrictive material, a superconductor, a ferromagnetic material, Or any other suitable material, such as a thermoelectric material. In one embodiment, the methods provide that the buckled components are printed and transferred from an elastomeric substrate, such as a stamp, to a device substrate, such as, for example, a curved device substrate.

Instead of creating pop-up or buckled components through application of forces or deformation to the elastomeric substrate, it is also possible to provide a component material, such as a receiving surface, A tensile and bendable interconnect can be made.

In one embodiment, a substrate having wave structures on the surface is smoothed, such as by spin-coating the polymer to partially embed the recess structures, to produce a tensionable and bendable component. . The partial embedding creates a smooth-wobbled substrate. The components are then deposited on the smoothly-wobbled substrate and patterned as desired. The components include, but are not limited to, metal structures. The component parts on the receiving surface substrate are mobilizable for subsequent casting of the polymer stamp to a substrate that is at least partially coated with the component parts. The component is transferred to the polymer substrate by removing the polymer stamp from the substrate to produce a tensionable and bendable component. In one embodiment, the interface between the component and the substrate is Au / Su-8 epoxy photoresist. The component may be a layered metal, for example Au / Al. The substrate may be stacked at the actual interface between the substrate and the metal, such as Au / Su-8, such as a glass layer supporting the Su-8 layer.

An alternative method for fabricating a pop-up component, such as a pop-up interconnect on the stamp surface, includes planarizing the curved substrate surface, contacting the components with the planarized surface, and Allowing the surface of the substrate to be relaxed to be restored to its curved geometry. In one embodiment, the method further provides spatial patterning of the bonding positions prior to contact as described herein. In this embodiment, the method is particularly suitable for transferring interconnects and device components to a corresponding second bend substrate surface. In one aspect, bonding means, such as an adhesive or bonding precursor, allow transfer of the interconnection between the second bend substrate and the interconnection system on the first bend substrate to the second substrate after the elastomeric stamp is removed Lt; / RTI >

In one aspect, any of the methods and apparatuses in accordance with the present invention have a stamp or elastomeric substrate that is PDMS with a linear elastic response for up to about 40% strain. Alternatively, the interconnections of the present invention are part of a pullable electrode, a pullable passive matrix LED display, or a photodetector array. In one embodiment, the present invention is directed to a tensionable electronic device having any one or more interconnections fabricated by the methods of the present invention. Wherein the electronic device is a tensionable or bendable electrode, a passive matrix LED, a solar cell, optical collector arrays, a biosensor, a chemical sensor, a photodiode array, or a semiconductor array. In one aspect, the device components electrically connected to the buckled interconnections are thin films, sensors, circuit elements, control elements, microprocessors, transducers, or combinations thereof. In one aspect, the interconnects are accessed by electrically connecting one end of the interconnect to the device components.

In one embodiment, the invention relates to structures and methods with wave-guided nanomembranes, such as wave-semiconducting nanomembranes. Such wave-enhanced nanomaterials facilitate the integration of flexibility within the device components themselves (as opposed to the flexibility of interconnections connecting device components). In one aspect, the present invention is directed to a method of manufacturing a biaxially tensile semiconductor film that transfers semiconductor nanomaterials from a first substrate to a second substrate. At this time, after the transfer, the deformed substrate is allowed to relax and be restored to its resting configuration. In one aspect, the thickness of the semiconductor material is between about 40 nm and 600 nm. The release of the force causing the two-dimensional deformation creates a nanofilm having a two-dimensional wave structure. In one aspect, the stress is generated by varying the temperature of the flexible substrate.

In one embodiment, the method includes providing a substrate having a receiving surface having a relief structure; Smoothing the relief structure by spin-coating the polymer to at least partially conformally coat the receiving surface; Casting a polymer stamp onto the spin-coated substrate; Removing the polymer stamp from the substrate to expose the polymer stamp having the relief structure; And depositing a device component on the polymer stamp surface having a relief structure, whereby a tension for use in a tensionable and bendable device is provided, It is possible to manufacture the components which are possible and bendable. In one aspect, the relief structures are wavy.

In one embodiment, the component comprises a metal, the metal by electrodeposition, or providing a shadow mask; Contacting the shadow mask with a waved surface; And evaporating the metal through the shadow mask to create a metal pattern corresponding to the shadow mask on the waved surface. The substrate with wave structures is selectively made by anisotropic etching of Si (100) or by embossing of Su-8. Optionally, the waved surface has a wavelength ranging from 50 nm to 1 mm; An amplitude ranging from 100 nm to 1 mm, and can be stretched without destruction to 100%. Optionally, the component is transferred to the device substrate. In one aspect, the device component includes an interconnect, the method further comprising providing additional device components and forming electrical contact between the one end of the interconnect and the additional device component .

In another aspect, the present invention provides a method of manufacturing an apparatus through heterogeneous integration of material levels and / or device level heterogeneous integration techniques. The method of the present invention for manufacturing an apparatus comprises the steps of: (i) providing, as a substrate, a substrate pre-patterned with one or more of the device components supported by the receiving surface of the substrate; And (ii) fabricating the plurality of printable semiconductor elements on the substrate by printing printable semiconductor elements over one or more structures provided on or on the receiving surface of the substrate. At this time, at least some of the printable semiconductor elements are arranged such that they are spatially aligned, electrically contacted, or both with one or more of the device components supported by the substrate. In one embodiment, each of the printable semiconductor elements has a length selected from the range of about 100 nm to about 1000 microns, a width selected from the range of about 100 nm to about 1000 microns, and a width of about 10 nm to about 1000 microns Lt; RTI ID = 0.0 > a < / RTI > range.

In another aspect, the present invention provides methods for fabricating multilevel device structures through material level heterogeneous integration and / or device level heterogeneous integration techniques. The method of the present invention for manufacturing an apparatus comprises the steps of: (i) providing, as a substrate, a substrate pre-patterned with one or more of the device components supported by the receiving surface of the substrate; (ii) assembling a first set of printable semiconductor elements onto the substrate by printing printable semiconductor elements over one or more structures provided on or on the receiving surface of the substrate, ; (iii) providing an intermediate layer having a receiving surface over the first set of printable semiconductor elements; And (iv) assembling a second set of printable semiconductor elements onto the intermediate layer by contact printing printable semiconductor elements over one or more structures provided on or on the receiving surface of the intermediate layer, Lt; / RTI > layer. In one embodiment, at least a portion of the printable semiconductor elements in the first device layer are spatially aligned, electrically contacted with at least a portion of the printable semiconductor elements in the second device layer, or both Respectively. A specific method of this aspect of the invention further comprises forming an electrical contact between at least a portion of the printable semiconductor elements in the first device layer and at least a portion of the printable semiconductor elements in the second device layer.

Useful contact printing methods for assembling, organizing and / or integrating printable semiconductor elements in these methods include dry transfer contact printing, microcontact or nanocontact printing, Microtransfer or nanotransfer printing, and self assembly assisted printing. It is advantageous in the present invention to use contact printing, since contact printing enables to assemble and integrate a plurality of printable semiconductors into a selected relative orientation and position with respect to each other. Further, in the present invention, contact printing is performed using various types of materials and structures including semiconductors (for example, inorganic semiconductors, single crystal semiconductors, organic semiconductors, carbon nanomaterials, etc.), dielectrics and conductors To assemble, and to integrate < / RTI > Alternatively, the contact printing methods of the present invention provide for transfer and assembly in which the printable semiconductor elements are precisely matched to pre-selected relative positions and spatial orientations for one or more pre-patterned device components on the device substrate . Contact printing can also be accomplished using conventional hard or semi-rigid substrates such as glass, ceramics, and metals and flexible substrates such as flexible substrates, bendable substrates, shapeable substrates, conformable substrates, , And / or substrates with attractive physical and mechanical properties for certain applications, such as, for example, stretchable substrates. The contact printing assembly of printable semiconductor structures may be compatible with, for example, a low temperature process (e.g., 298K or less). This property enables the present optical system to be implemented using a range of substrate materials including those that are degraded or degraded at high temperatures, such as polymer and plastic substrates. The contact printing transfer, assembly, and integration of device elements is cost-effective and has high throughput, such as roll-to-roll printing and flexographic printing methods and systems. It is advantageous because it can be applied through printing techniques.

In certain embodiments of these methods of manufacturing devices, at least a portion of the printable semiconductor elements comprises heterogeneous semiconductor elements. A range of heterogeneous semiconductor elements are useful in the present invention. In one embodiment, or in one embodiment, the heterogeneous semiconductor elements comprise an inorganic semiconductor structure; And a material selected from the group consisting of an inorganic semiconductor having a composition different from that of the inorganic semiconductor structure, an inorganic semiconductor having a doping different from the inorganic semiconductor structure, a carbon nanomaterial or a film thereof, an organic semiconductor, a dielectric material, One or more structures. For example, in one embodiment, the heterogeneous semiconductor elements may be single crystal silicon, Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO , ZnSe, ZnTe, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AIGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, SiGe and GaInAsP Lt; RTI ID = 0.0 > semiconductor < / RTI > For example, in one embodiment, the hetero semiconductor elements comprise a dielectric material, a conductor, or an inorganic semiconductor structure combined with both a dielectric material and a conductor.

In addition, useful hetero semiconductor elements include printable device components and printable devices. In one embodiment, for example, the printable semiconductor elements may be used in electronic devices, arrays of electronic devices, optical devices, electro-optical devices, microfluidic devices, microelectromechanical systems, nanoelectromechanical systems, sensors, A microprocessor, and a memory device. ≪ RTI ID = 0.0 > [0002] < / RTI >

In certain methods, at least a portion of the heterogeneous semiconductor elements are selected from the group consisting of a diode, a transistor, a photovoltaic cell, a light emitting diode, a laser, a PN junction, a thin film transistor, a high electron mobility transistor, a photodiode, One or more printable semiconductor devices selected from the group consisting of an effect transistor, a metal-semiconductor field effect transistor, a photodetector, a logic gate device, and a vertical-cavity surface-emitting laser. In one embodiment, for example, at least a portion of the printable semiconductor devices are assembled onto the substrate through contact printing such that electrical contact is made between the printable semiconductor devices and electrodes pre- do.

The methods of the present invention include multiple steps of assembling printable semiconductor elements onto a substrate or structure (s) such as device component structures, interlayer structures and / or planarization or encapsulation layers provided thereon, and And may optionally further include iteratively. In one embodiment, for example, the method of the present invention further comprises the steps of providing additional printable semiconductor elements onto semiconductor elements provided on the receiving surface of the substrate, or onto the receiving elements of the substrate, Further comprising assembling the additional printable semiconductor elements onto the substrate by contact printing provided over the elements or on one or more intermediate structures.

The multi-layer device structure fabricated by these methods may comprise a plurality of device layers separated by one or more interlayers. Wherein the device layers comprise printable semiconductor elements. In some embodiments, for example, the device layers have thicknesses less than or equal to 1 micron, and the intermediate layers have thicknesses less than or equal to 1.5 microns. In some embodiments, the methods of the present aspect further comprise forming an electrical contact between the printable semiconductors provided in different device layers.

A specific method of this aspect includes the steps of: (i) providing an intermediate layer on top of printable semiconductor elements printed on one or more structures provided on or on the receiving surface of the substrate; And (ii) fabricating additional printable semiconductor elements by contact printing of printable semiconductor elements on the receiving surface of the intermediate layer. For example, in one embodiment, at least a portion of the additional printable semiconductor elements provided on the receiving surface of the intermediate layer are spatially aligned, electrically contacted with the printable semiconductor elements provided on the receiving surface of the substrate, Both are positioned to be achieved. The methods of this aspect may alternatively include the steps of: (i) patterning one or more openings in the interlayer, thereby forming a printable semiconductor element (s) on the receiving surface of the substrate or on one or more structures provided on the receiving surface Exposing one or more regions of the substrate; And (ii) a plurality of semiconductor elements disposed between the semiconductor elements provided on the receiving surface of the intermediate layer and the printable semiconductor elements provided on the receiving surface of the substrate or over one or more structures provided on the receiving surface And forming the electrical contact.

The methods of the present invention may include a number of optional processing steps. One method of the present invention further comprises providing an adhesive layer on the receiving surface. Here, the printable semiconductor elements are printed on the adhesive layer. One method of the present invention further comprises providing an encapsulating layer or planarizing layer over the printable semiconductor elements printed on or on the receiving surface of the substrate provided over the receiving surface . One method of the present invention includes the steps of providing one or more printable semiconductor elements printed on one or more structures provided on or above the receiving surface of the substrate or a receiving surface of the substrate via one or more Or more of the conductive thin films. The methods of the present invention include: Polymer substrates, plastic substrates, stretchable substrates; Rigid substrates; But is not limited to, a range of substrates including semiconductor wafers and contoured substrates.

The present invention also includes devices and systems manufactured using these methods. The devices and systems of the present invention may be used in various applications such as electronic devices, optical devices, electro-optical devices, microfluidic devices, microelectromechanical systems, nanoelectromechanical systems, But are not limited to, sensors, integrated circuits, microprocessors, and memory devices.

In another embodiment, the present invention is a two-dimensional stretchable and bendable device. In this aspect, the apparatus includes a substrate having a contact surface. Wherein a component is coupled to at least a portion of the substrate contacting surface, and wherein the component has at least one relief structure area and at least one substantially flat area. Wherein the relief structure region has a region separated from the substrate, and the substantially flat region is at least partially bonded to the substrate. In one aspect, the at least one relief structure region has a two-dimensional pattern of relief structures on the substrate, such as a wave pattern having a plurality of contact regions contacting the substrate contact region.

In order to facilitate coupling the component to the substrate, any one or both of the component or substrate receiving surfaces may have patterned regions, such as a pattern of activated regions. "Active areas" include patterns of adhesive locations on the substrate contact surface or on the component parts; A selected pattern of physical parameters of the substrate or component selected from one or more of thickness, modulus, temperature, composition of the substrate or component each having a spatial variation; Chemical modification of the substrate surface; And an area adjacent to free edges of the component on the substrate contact surface; And / or < / RTI > means for providing buckling. ≪ RTI ID = 0.0 > A common theme of each of these parameters is that they provide a mechanism for facilitating the coupling between the component and the substrate or for creating a spatially controlled buckling of the component. For example, by placing the substantially flat area or a portion of the relief structure area in the active substrate area, the component can be controllably buckled to provide a tensionable component.

Any of the methods and apparatus disclosed herein may be applied to a variety of electronic devices including but not limited to metal, semiconductor, insulator, piezoelectric, ferroelectric, magnetostrictive, electrostrictive, superconductor, ferromagnetic, And a component selected from the group consisting of one or more of the materials that are thermoelectric materials. Any of the methods and apparatuses disclosed herein are optionally for an apparatus selected from the group consisting of an electronic device, an optical device, an opto-electronic device, a mechanical device, and a thermal device.

In one aspect, any two-dimensionally stretchable and bendable devices may be substantially (but not necessarily) substantially rectangular, including an island for receiving device components, such as interconnecting relief structures that electrically connect at least two islands And has a flat area.

In one embodiment, any substrate contact or receiving surface may be flat, substantially planar, have a relief structure, have a curved portion, have a wavy portion, or be elastomeric, such as a PDMS substrate or substrate layer to be.

Shape-conforming devices have a variety of applications ranging from flexible displays and biological and physical sensors that can be matched from electronic fibers

도 29는 2층의 버클링된 GaAs 리본 어레이를 갖는 샘플의 사진이다. 본 구조는 순차 적층(layer by layer) 방식으로 제조된다. GaAs 리본의 제 1 층(60%의 사전 변형과, W_act = 10 ㎛, 그리고 W_in = 400 ㎛로 정의된 버클링된 기하 구조)은 PDMS 내에 내장된다. 버클링된 리본들의 제 2 층은 50%의 사전 변형과 W_act = 10 ㎛, 그리고 W_in = 300 ㎛를 이용하여 이 기판의 표면 위에 형성된다.
*도 30은 PDMS의 표면들 위와 매트릭스 내의 버클링된 리본들의 구부림을 나타낸다. A-C는 오목하거나(A), 편평하거나(B) 또는 볼록한(C)의 표면들을 갖는 PDMS 위에 있는 버클링된 GaAs 리본들의 낮은 배율(왼쪽 위쪽 프레임) 및 고배율(오른쪽 프레임), 그리고 개략도(왼쪽 아래 프레임)의 광학 현미경 이미지들이다. c에 있는 스케일바는 a 및 b에도 적용된다. d는 (왼쪽) 구부리기 전의 그리고 (오른쪽) 구부린 후의 PDMS 내에 내장된 버클링된 리본들의 이미지들이다. 오른쪽 이미지에 있는 스케일바는 왼쪽 이미지들에도 적용된다. 버클링된 상기 리본들은 60%의 사전 변형과 W_act = 10 ㎛, 그리고 W_in = 400 ㎛로 형성되었다.
도 31은 인장 가능한 금속-반도체-금속 광 감지기(MSM PDs: metal-semiconductor-metal photodetectors)를 특성화한 것이다. A는 기하 구조를 개념적으로 도시한 것(위), 동등한 회로(중간), 및 인장하기 전과 인장된 동안의 버클링된 PD의 광학 이미지(아래)이다. B는 상이한 출력 세기를 갖는 IR 램프에 의하여 조사된 버클링된 PD로부터 기록된 전류(I)-전압(V) 곡선들이다. 일정한 휘도로 조사된 PD가 상이한 정도로 인장되거나(C) 또는 압축되었을 때(D)의 I-V 특성들이다.
도 32는 반구형 엘라스토머 전사 '스탬프'가 통상의 웨이퍼로부터 상호 연결된 Si CMOS '칩렛(chiplet)'들을 리프트오프(liftoff) 시키고, 그 후 그들의 기하 구조를 반구형 모양으로 전환할 수 있음을 나타낸다. 상기 칩렛들 사이의 '팝-업' 상호 접속부들은 이러한 평면으로부터 곡면으로의 전환과 관련된 변형들을 수용한다.
도 33은 상호 접속된 CMOS 칩렛들을 반구형 스탬프로부터, 그에 매치되는 반구형 장치 기판으로 전사하는 것을 나타낸다. 광 경화성 접착층이 상기 CMOS를 장치 기판에 결합하며, 상기 표면을 평탄화한다.
도 34는 반구형 스탬프와 양립 가능한 고정물(fixturing), 액츄에이터 및 시각화 시스템을 갖는 프린터 장치를 나타낸다.
도 35는 반구형 스탬프 위의, '팝업' 리본 상호 접속부들에 의하여 전기적으로 연결되는 단결정 실리콘 아일랜드들의 압축 가능한 어레이를 나타낸다.
도 36은 ∼ 2 cm의 곡률 반경을 갖는 반구형 스탬프의 표면 위로 '링크된' 상호 접속된 단결정 실리콘 아일랜드 어레이의 광학 이미지이다.
도 37은 반구형 스탬프들에 대하여 사용될 수 있는 다양한 실리콘 엘라스토머에 대한 응력/변형 곡선들이다. 20% 미만의 변형에 대하여 선형이며, 완전히 탄성인 응답들이 중요하다.
도 38은 초기에 0.57 mm의 균일한 두께를 갖는 반구형 스탬프에서의 구형으로부터 평면으로의 변환을 유한 요소 모델링한 것이다.
도 39는 탄성 지지체 위의 2차원의 "웨이브진" 반도체 나노막을 제조하기 위한 단계들을 개념적으로 나타낸 것이다.
도 40의 (a 내지 f)는 실리콘 나노막들을 형성하는 과정에서 다양한 단계들에서의 2D 웨이브진 구조물들의 광학 현미경 사진들이다. 삽입 사진들은 2차원 파워 스펙트럼들을 보여 준다. (g)는 완전히 발전된 구조물의 저배욜 이미지이다. 이 샘플에 대하여 실리콘의 두께는 100 nm이고, 측방향 치수는 ca. 4×4 mm²이고, 기판은 PDMS이고, 열적으로 유발된 사전 변형은 3.8%이다. (h)는 프레임 (a 내지 f)에 대응되는 단파장의 플롯이고, (i)는 프레임 (g)의 다양한 지점에서 평가된 장파장의 히스토그램이다.
도 41은 PDMS 위의 2D 웨이브진 Si 나노막의 (a) AFM 이미지이고 (b 내지 d) SEM 이미지들(경사 각도 60°)이다. 상기 실리콘의 두께는 100 nm이고, 열적 사전 변형은 3.8%이다. 이들 이미지에서는 상기 웨이브 패턴의 고도로 주기적인 성질, Si에 식각된 구멍들 근처의 PDMS와 Si의 가장자리에서 볼 수 있는 밀접한 접촉에 의하여 증명되는 바와 같은 Si와 PDMS 사이의 우수한 결합, 및 웨이브 구조물들과 이들 구멍들의 위치들 사이의 상호 무관련성이 흥미롭다.
도 42의 (a)는 3.8%의 열적 사전 변형으로 형성되고 PDMS 위에 다양한 두께(55, 100, 260, 320 nm)를 갖는 2D 웨이브진 Si 나노막들의 광학 현미경 사진들이고, (b)는 Si 두께에 대한 단파장과 진폭의 의존성을 나타낸다.
도 43의 (a)는 세 개의 상이한 방향들에서 적용된, 상이한 일축성 변형들 하에서의 2D 웨이브진 Si 나노막들의 광학 현미경 사진들이다. 이들 샘플들은 PDMS 위의 100 nm의 두께를 갖고, 3.8%의 열적 사전 변형으로 형성되는 Si 막들로 구성된다. 상기 이미지들은 인장하기 전의 릴랙스된 상태(최상부 프레임들), 인장한 후에 릴랙스된 상태(최하부 프레임들), 그리고 일축성으로 적용된 인장 변형이 1.8%일 때(위에서 두 번째 프레임), 및 3.8%일 때(아래에서 두 번째 프레임) 수집되었다. (b)는 상이한 세 방향으로 적용된 변형에 대한 단파장의 의존성을 나타낸다.
도 44는 2D 웨이브진 Si 나노막의 상이한 영역들의 AFM 이미지들로서, 상기 막의 가장자리 근처의 영역(상부 프레임), 이 가장자리 영역으로부터 약간 떨어진 영역(가운데 프레임), 및 상기 막의 중앙 근처의 영역(하부 프레임)의 1D 웨이브진 기하학적인 특성을 보여준다. 본 샘플은 PDMS 위의 100 nm의 두께를 갖는, 3.8%의 열적 사전 변형으로 형성된 Si 막으로 구성된다.
도 45는 1000 ㎛의 길이와 100, 200, 500, 및 1000 ㎛의 폭들을 갖는 2D 웨이브진 Si 나노막들의 광학 현미경 사진들이다. 이들 막들은 모두 100 nm의 두께를 가지며, 동일한 PDMS 기판 위에, (a) 2.3% 및 (b) 4.8%의 열적 사전 변형으로 형성되었다. (c)는 유사 막들에 있어서 사전 변형에 대한 가장자리 효과 길이의 의존성을 나타낸다.
도 46은 (a) 원형, (b) 타원형, (c) 육각형, 및 (d) 삼각형의 상이한 모양들을 갖는 2D 웨이브진 Si 나노막들의 광학 현미경 사진들이다. 이들 막들은 모두 100 nm의 두께를 갖고, PDMS 위에 4.8%의 열적 사전 변형으로 형성되었다.
*도 47은 상호 접속된 편평한 아일랜드들의 어레이에 2D 인장 가능성을 부여하기 위하여 가장자리 효과들을 이용하도록 설계된 모양들을 갖는 Si 나노막들의 웨이브진 구조들을 보여주는 광학 현미경 사진들이다. 여기에 도시된 두 경우들 모두에 있어서, 상기 Si는 100 nm 두께를 갖고, 정사각형들은 100×100 ㎛이고, 리본 접속부들은 30×150 ㎛ 라인들이다. 사전 변형은 (a, e) 2.3%, 그리고 (c, g) 15%이다. (a, c, e, g)의 리본들과 정사각형들을 보여주는 선택된 영역들의 SEM 이미지들(경사 각도 75°)은 각각 (b, d, f, h)에 보여진다. 고배율 SEM 이미지들의 삽입 사진들은 b 및 d에서 웨이브들의 상승된 영역들을 보여준다.
도 48은 PDMS 기판 웨이브 상의 2D 웨이브 Si 나노막 (100 nm 두께, 4×5 mm², 및 3.8% 열적 사전 변형) 샘플의 사진이고(상부 프레임), 그리고 (i) 가장자리에서의 1D 웨이브들, (ii) 더 안쪽 영역에서의 헤링본(herringbone) 웨이브들, 그리고 (iii) 중앙에서의 무질서한 헤링본 웨이브들이다. 스케일 바는 50 ㎛이다.
도 49는 헤링본 웨이브 구조물들에서 특성 길이들(characteristic lengths)을 나타내는 개략도이다.
도 50은 Si 변형을 헤링본 및 1D 웨이브들에서 적용된 열적 사전 변형의 함수로 나타낸 것이다. Si 변형은 ε_Si=(L-λ)/λ에 의하여 실험적으로 측정되었고, 여기서 L 및 λ는 AFM 표면 프로파일에서 표면 및 수평 거리이다.
도 51은 인장 시험(∼ε_st = 4.0%)의 사이클들 후의 헤링본 웨이브들의 광학 현미경 이미지들이다. 상기 테스트 샘플은 100 nm 두께의 Si 막과 3.8% 이축성(biaxial) 열적 사전 변형으로 준비되었다. 헤링본 웨이브들은 15회까지의 인장 테스트 사이클 후에도 막의 크랙에 기인하는 일부 결함들을 제외하고는 최초와 거의 유사한 구조를 갖도록 복원되었다.
도 52는 일축성 인장 변형의 적용에 따른 헤링본 웨이브들의 '펼쳐짐(unfolding)'을 개략적으로 도시한 것이다. 압축성 변형 ε_cp는 인장 변형 ε_st과 관련된 포아송 효과(Poisson effect)에 기인한다.
도 53은 이축성 인장 테스트로서의 가열 및 냉각 과정 동안 헤링본 웨이브들의 모폴로지 변화의 광학 현미경 이미지들이다. 테스트 샘플은 100 nm 두께의 Si 막과 2.9% 이축성 열적 사전 변형으로 준비되었다.
*도 54는 구조화되어 웨이브진 마스터 위에 증착하고, 이어서 상기 마스터 위에 스탬프를 캐스트(cast)하고, 상기 스탬프를 경화시키고, 그리고 그에 의하여 해제와 함께 상기 전극들을 마스터로 전사함으로써 웨이브지고 인장가능한 전극들을 제조하는 한 방법을 요약한다.
도 55는 도 54의 방법과 조합된 도 4의 방법들에 의하여 제조된 웨이브진 PDMS 위의 인장 가능한 금속 전극들(Au, 300 nm 두께)의 이미지를 제공한다. 아래쪽 패널은 상기 인장 가능하고 웨이브진 금속 전극들의 전기 저항 측정 데이터를 적용된 인장 변형(30%까지)의 함수로서 나타낸 그래프이다.
도 56은 플렉서블하고 인장가능한 iLED 스트립-광원을 제조하기 위한 본 방법의 응용 실시예이다. (a)는 상기 장치가 크게 구부릴 수 있음을 나타내는 마이크로 사진이고, 이 실시예에서는 구부림 반경이 0.85 cm이다. (b)는 웨이브진 PDMS 기판 위의 인장 가능한 금속의 단면(위쪽 패널, 스케일바는 40 ㎛)과 평면(아래쪽 패널, 스케일바는 3 mm)을 제공한다. 상기 금속은 물리적 성질의 심각한 열화 없이 약 30% 인장 가능하다. (c)는 ((b)에 나타낸) PDMS 위의 사인파로 웨이브진 금속 상호 접속부들의 진폭(원, 오른쪽 축)과 파장(정사각형, 왼쪽 축)에 대한 국부적인 변형의 영향을 나타낸 그래프이다. 변형이 증가함에 따라 이에 대응하여 금속의 파장이 증가하고 진폭이 감소한다.
도 57은 이종의 3차원 전자 장치를 위한 인쇄된 반도체 나노 물질들에 기반한 접근을 개략적으로 나타낸 것이다. 상기 공정은 소스 기판들 위에 개별적으로 형성된 나노튜브류, 나노와이어류, 나노리본류 또는 다른 활성 나노 물질들의 집합을 공통 장치 기판 위로 반복적으로 전사 인쇄하여 극초박형의 다층 적층 기하 구조를 갖는 상호 접속된 전자 장치를 생성하는 것을 수반한다.
도 58의 (A)는 반도체를 위해 인쇄된 실리콘 나노리본들을 사용하는 단결정 실리콘 금속 산화물 전계 효과 트랜지스터들(MOSFETs: metal oxide field effect transistors)의 어레이의 3차원 다층 적층체의 광학 현미경 사진이다. 이 이미지의 (1st라고 표시된) 아래쪽, (2nd라고 표시된) 중간, 그리고 (3rd라고 표시된) 위쪽 부분은 장치의 하나, 둘 또는 세 층들을 갖는 영역들에 각각 대응된다. (B)는 개략적인 단면도(위) 및 사시도(아래)이다. S, D 및 G는 각각 소스, 드레인, 및 게이트 전극(모두 금색으로 나타냄)을 가리킨다. 밝고 어두운 청색 영역들은 실리콘 리본들의 도핑되고 도핑되지 않은 영역들에 대응되고; 자주색 층은 SiO₂ 게이트 유전체이다. (C)는 (A) 및 (B)에 나타낸 것과 같은 장치 기판 위에 공초점 현미경(confocal microscopy)에 의해 수집된 3차원 이미지들이다(왼쪽 프레임: 평면도; 오른쪽 프레임: 사시도). 상기 층들은 식별의 편리를 위해 색채화되었다(금색: 상부층; 적색: 중간층; 청색: 하부층; 실리콘: 회색). (D)는 각 층에 있는 Si MOSFET의 전류-전압 특성으로서, 우수한 성능(470±30 cm²/Vs의 이동도)과 성질들의 양호한 균일성을 보인다. 채널 길이와 폭은 각각 19 및 200 ㎛이다.
도 59의 (A)는 3층으로 적층된 GaN 나노리본 HEMT들, Si 나노리본 MOSFET들 및 SWNT 네트워크 TFT들을 포함하는 3차원적인 이종 집적된 전자 장치의 광학 현미경 사진이다. (B)는 공초점 현미경에 의하여 수집된 3차원 이미지이다. 층들은 식별의 편의를 위해 색채화되었다(금색: 상부층, Si MOSFET들; 적색: 중간층, SWNT TFT들; 청색: 하부층). (C)는 상기 제 1 층 위의 GaN 소자들(채널 길이, 폭 및 게이트 폭은 각각 20, 170, 및 5 ㎛), 제 2 층 위의 SWNT 소자들(채널 길이 및 폭은 각각 50, 및 200 ㎛), 및 제 3 층 위의 Si 소자들(채널 길이 및 폭은 각각 19 및 200 ㎛)의 전기적 특성들이다. (D)는 각 층의 소자들(검은 정사각형: Si MOSFET들; 적색 원: SWNT TFT들; 녹색 삼각형: GaN HEMT들)의 정규화된 트랜스컨덕턴스(transconductance)(g_m/g_0m)를 플라스틱 기판의 구부림 반경의 함수로 나타낸 것이다(왼쪽). 구부려진 시스템 및 프로빙 장치의 이미지이다(오른쪽).
도 60의 (A)는 폴리이미드 기판 위의 3D 실리콘 NMOS 인버터들의 인쇄된 어레이의 이미지이다. 상기 인버터들은 상이한 두 수준 상에 있고 전기적 비아(via) 구조물에 의하여 상호접속된 MOSFET들(채널 길이는 4 ㎛, 부하-구동부(load-to-driver) 폭 비율은 6.7, 및 구동부 폭은 200 ㎛)로 구성된다. 오른쪽 위쪽의 이미지는 왼쪽 프레임의 적색 상자로 표시된 영역의 확대도를 제공한다. 오른쪽 아래의 그래프는 통상의 인버터의 전달 특성을 나타낸다. (B)는 p 채널 SWNT TFT(채널 길이와 폭이 각각 30 및 200 ㎛)와 n 채널 Si MOSFET(채널 길이와 폭이 각각 75 및 50 ㎛)을 이용하는 인쇄된 상보적인 인버터의 전달 특성이다. 삽입된 사진은 인버터의 광학 현미경 사진(왼쪽)과 회로의 개념도(오른쪽)이다. (C)는 어두움으로부터 850 nm의 적외선 광원으로 11 μW까지 상이한 수준에서의 Si MOSFET(채널 길이와 폭은 각각 9 및 200 ㎛)과 집적된 GaAs MSM(채널 길이와 폭은 각각 10 및 100 ㎛)의 전류-전압 응답이다. 삽입 사진은 광학 이미지와 회로도를 나타낸다.
도 61은 ∼1 ㎛까지 인쇄 정합(registration)이 가능한, 자동화된 전사-인쇄용 스테이지의 이미지이다.
도 62의 (A)는 폴리이미드 기판 위에 Si MOSFET들 및 GaN HEMT가 3차원적으로 이종 집적된 어레이의 광학 현미경 사진이다. 오른쪽 삽입도는 개략 단면도이다. 전극들(금색), SiO₂(PEO; 자주색), Si(밝은 청색: 도핑되지 않은 부분; 어두운 청색: 도핑된 부분), GaN(어두운 녹색: 오믹 콘택들; 밝은 녹색: 채널), 폴리이미드(PI: 갈색) 및 폴리우레탄(PU; 황갈색)이 모두 도시된다. (B)는 통상의 Si MOSFET(채널 길이 및 폭은 각각 19 및 200 ㎛)과 GaN HEMT(채널 길이, 폭 및 게이트 폭은 각각 20, 170 ㎛ 및 5 ㎛)의 전류-전압 특성들을 나타낸다. 왼쪽 프레임들에 있는 Si 및 GaN에 대한 데이터들은 각각 V_dd = 0.1V 및 V_dd = 2V에서 측정되었다.
도 63의 (A)는 폴리이미드 기판 위에 Si MOSFET들 및 SWNT TFT가 3차원적으로 이종 집적된 어레이의 광학 현미경 사진이다. 오른쪽 삽입도는 개략 단면도이다. 전극들(금색), 에폭시(청록색), SiO₂(PEO; 자주색), Si(밝은 청색: 도핑되지 않은 부분; 어두운 청색: 도핑된 부분), SWNT(회색), 폴리이미드(PI: 갈색) 및 경화된 폴리이미드(황갈색)이 모두 도시된다. (B)는 통상의 SWNT TFT(채널 길이 및 폭은 각각 75 및 200 ㎛)와 Si MOSFET(채널 길이 및 폭은 각각 19 및 200 ㎛)의 전류-전압 특성들을 나타낸다. 왼쪽 프레임들에 있는 SWNT 및 Si에 대한 데이터들은 각각 V_dd = -0.5V 및 V_dd = 0.1V에서 측정되었다.
도 64의 (A)는 폴리이미드 기판 위에 Si MOSFET들, SWNT TFT 및 GaN HEMT가 3차원적으로 이종 집적된 어레이의 단면 개략도이다. (B)는 여러 Si MOSFET들(채널폭 = 200 ㎛, 흑색선: 채널길이 = 9 ㎛, 적색: 14 ㎛, 녹색: 19 ㎛, 청색: 24 ㎛)에 대한 전달 특성들, 유효 이동도 및 온/오프 비율을 나타낸다. (C)는 SWNT TFT들(채널폭 = 200 ㎛, 흑색선: 채널길이 = 25 ㎛, 적색: 50 ㎛, 녹색: 75 ㎛, 청색: 100 ㎛)이다. 그리고 (D)는 GaN HEMT들(채널 길이, 폭, 및 게이트 폭은 각각 20 ㎛, 170 ㎛, 및 5 ㎛)에 대한 전달 특성들, 트랜스컨덕턴스들, 및 온/오프 비율을 나타낸다.
도 65의 (A)는 실리콘 웨이퍼 기판 상에 제조된 SWNT-Si CMOS 인버터의 개략적인 단면 구조이다. (B)는 CMOS 인버터를 형성하는 n-채널 Si MOSFET과 p-채널 SWNT TFT의 전달 및 I-V 특성들이다. (C)는 인버터의 계산된 전달 특성들과 Si 및 SWNT 트랜지스터들의 I-V 특성들이다.
도 66의 (A)는 폴리이미드 기판 위에 제조된 GaAs MSM-Si MOSFET IR 감지기의 개념적인 단면 구조와 개략적인 회로도이다. (B)는 3V 공급에 대한 GaAs MSM IR 감지기(L = 10 ㎛, W = 100 ㎛)의 전류-전압 특성과 Si MOSFET(L = 9 ㎛, W = 200 ㎛)의 전달 및 I-V 특성들이다. (C)는 3V 공급에 대한 GaAs MSM의 계산된 IV 특성과 Si MOSFET과 집적된 GaAs MSM의 I-V 응답이다.
도 67은 변형 가능한 기판에 부분적으로 접착된 광학적 미세 구조의 제어된 버클링을 통해 제조된 광학 장치(도파관 어레이)를 개념적으로 나타낸다.
도 68은 변형 가능한 기판에 부분적으로 접착된 전도성 미세 구조의 제어된 버클링을 통해 제조된 기계적 장치(예를 들면, 가속도/압력 센서)를 개념적으로 나타낸다.
도 69는 변형 가능한 기판에 부분적으로 접착된 내열성 미세 구조의 제어된 버클링을 통해 제조된 열적 장치(미세 볼로미터: microbolometer)를 개념적으로 나타낸다.Figure 1 summarizes one method of making a waved or buckled, stretchable metal interconnect. (a) is a flow chart summary, and (b) shows flowchart steps.
Figure 2 is a photograph of a tensionable, waved / buckled electrical interconnect formed by being recovered from a rigid substrate onto a pre-deformed and stretchable PDMS rubber substrate and then releasing deformation to induce buckling.
Figure 3 summarizes one method of manufacturing electrodes that can be rolled through a deposition on an elastomeric substrate of a wave structure.
Figure 4 provides one method for making a smooth waxed elastomeric substrate. (a) is a flow chart summary, and (b) shows flowchart steps.
Figure 5 provides an image of a smoothly wobbled PDMS substrate produced by the methods outlined in Figures 3-4. The interconnects shown are 22.6% tensile and have a thickness of about 900 nm (700 nm Al / 200 nm Au), a wavelength of about 38 microns, and an amplitude of about 15.6 microns (distance from peak to valley) .
Figure 6a is a commercially available lens-phase array with cusps (from Edmund Optics). Figure 6b is a photo-curable epoxy spin-coated to make a smoothly wobbled substrate. Fig. 6c is a PDMS stamp cast on the substrate from Fig. 6b to produce a woven elastomeric stamp with a smooth structure.
Figures 7A-7C are tensile electrodes deposited over a smoothly waxed elastomeric substrate through a shadow mask by evaporation. The electrodes maintain conductivity and connectivity while being stretched to ~ 10% due to tension. The scale bar is about 0.1 mm. 7A is a cross-section of a wave on an elastomeric substrate. Figure 7b is a micrograph showing the plane of the electrode evaporated and deposited on the waxed elastomer substrate. The focal plane is above the peak of the wave angular bend. Figure 7c is a micrograph showing the plane of the electrode evaporated and deposited on the waxed elastomer substrate. The focal plane is above the wave valley.
Figure 8 is a schematic illustration of a process for manufacturing a stretchable passive matrix LED display using tensionable electrodes.
Figure 9 shows the mechanical tensile potential of a passive matrix LED display with waved electrodes.
Figure 10 shows inorganic light diode arrays distributed over a lens with a hemispherical curvature. It shows various lens shapes and angles.
Fig. 11 shows that a tensile possibility is required when the flat sheet is rounded around the spherical surface.
FIG. 12 summarizes one method for fabricating tensile and buckled semiconductor arrays that can conform to spherical curved surfaces.
Figure 13 is an optical microscope image of buckling and tensionable silicon arrays with single connection grid configurations A and B, multiple connection (e.g., dual) grid configuration C, and flower connection configuration D to be. The tensionable interconnects may electrically connect the photodiode, the light collecting / photo sensing elements, and other component parts, for example, in contact pad areas. These systems can be matched to surfaces. The configurations shown in Figs. 13A to 13D are above the PDMS substrate.
Figure 14 is electron microscope images of buckling and tensionable silicon arrays in a grid configuration. The buckling and tensionable silicon arrays can support device components and can conform to a curved surface. The scale bar is 200 탆 for A and 50 탆 for B.
15 is an electron microscope image of buckling and tensionable silicon arrays in a grid configuration with neighboring contact pads connected to each other by a plurality of (e.g., two) interconnects. The buckling and tensionable silicon arrays can support device components and can conform to a curved surface. The scale bar is 200 탆 for A and 50 탆 for B.
16 is electron microscope images of buckling and stretchable silicon arrays in a floral configuration. The buckling and tensionable silicon arrays can support device components and can conform to a curved surface. The scale bar is 200 탆 for A and 50 탆 for B.
17 is electron microscope images of buckling and stretchable silicon arrays in a bridge configuration. The buckling and tensionable silicon arrays can support device components and can conform to a curved surface. The scale bar is 200 탆 for A and 50 탆 for B.
18 is a photograph of photodiodes having a grid array configuration on a tensile and buckling silicon array on PDMS.
Figure 19 demonstrates the reversible behavior of the tensionable interconnects during tension and relaxation. The system is relaxed on panel 1. The system is tensioned on panels 2, 3 and 4 as indicated by the tensile arrows. In panel 4, the maximum tension is about 10%, resulting in a substantially flat interconnect for the interconnects aligned in the direction of the tensile force. The system is released in panels 5 to 8, and panel 8 has the same geometry and configuration as shown in panel 1. The scale bar is 0.2 mm.
20 is a "bubble stamp" or "balloon stamp" device capable of conformal contact to flat substrates as well as substrates having curvature.
Another device that can match both the spherically curved surface and the flat surface in Figure 21 is a tensile spherical-molded stamp. The stamp is cast on a curved surface (concave lens in this example) and removed. The stamp is tensioned to substantially flatten its surface to which the interconnects are to be transferred.
22 shows buckled silicon arrays that can be stretched during a tension cycle on "bubble" or "balloon" stamps. In this embodiment, the interconnect between adjacent contact pads includes two wave-wise interconnects (Si thickness 290 nm). Tensile testing utilizes bubble expansion to provide tensile in several directions. The rightmost panel is fully tensioned and the bottom two panels show that when the tension is removed, the interconnects are relaxed back to the pre-tensioned configuration shown on the left panel above.
Figure 23 shows silicon printed over glass lenses coated with an adhesive (PDMS or SU-8) through a balloon stamp.
Figure 24 summarizes process steps for fabricating 3D buckled shapes within semiconductor nanoribbons. A shows the preparation of a UVO mask and its use to pattern surface chemistry on a PDMS substrate. B shows buckling GaAs ribbons and embeds them in the PDMS. C represents the response of the buckled GaAs to tension and compression. D is a SEM image of a sample formed using the procedures in a and b. The pre-strain used to make this sample was 60%, and the W_act= 10 [mu] m, and W_in= 400 m.
25 shows the results of a pre-strain of 33.7% on (A) W_act = 10 [mu] m, and W_in= 190 [mu] m; And (B) W_act = 100 mu m, and W_in= 100 < RTI ID = 0.0 > pm. ≪ / RTI > Both samples represent buckling of deactivated regions resulting from the ribbon being desorbed from the PDMS. Sine waves with small peaks are W_act= 100 [mu] m. A comparison of these two samples showed that W_actIs selected to be smaller than the threshold value, it is possible to avoid formation of a structure of a small wave.
Figure 26 is a side view after microtoming of the buckling GaAs ribbon embedded within the PDMS. This image shows that the PDMS completely fills the gap between the ribbons and the underlying substrates. In this case, the buckles have a pre-strain of 60% and W_act = 10 [mu] m, and W_in= 300 [mu] m. The PDMS prepolymer cast on the surface of these buckled ribbons is cured in an oven at 65 DEG C for 4 hours.
27 is an optical microphotograph of side profiles of buckled (A and D) GaAs and (B, C) Si ribbons. A has different pre-strains (11.3%, 25.5%, 33.7% and 56.0% (top to bottom)) and W_act = 10 [mu] m, and W_inLt; RTI ID = 0.0 > = 190 < / RTI > ε_pre= 33.7% and 56.0% are mathematically predicted interconnection geometry. B is pre-deformed to 50%, W_act = 15 [mu] m, and W_in= 350, 300, 250, 250, 300, and 350 [mu] m (left to right). This image was taken with the sample tilted 45 °. C is 50% pre-strained and has adhesive locations W_act = 15 [mu] m, and W_in= 250 [mu] m) on the PDMS substrate patterned with lines parallel to the Si substrate. This image was taken with the sample tilted at 75 °. D is 60% pre-deformed and W_act = 10 [mu] m and different W_in= 100, 200, 300, and 400 [mu] m (top to bottom).
28 shows tension and compression of buckled GaAs ribbons embedded within a PDMS. A is an image of a single buckling ribbon tensioned at different levels of tensile strain (% of the amount). Nearly 50% destruction occurs. B is an image of a single buckling ribbon compressed at different levels of compression strain (% negative). For compressive strains greater than ~ -15%, the wave geometries of the wave with small, short periods appear at the peak of the buckling. C is an image of a single buckling ribbon compressed with different levels of compression deformation. In these cases, the buckles have a pre-strain of 60% and W_act = 10 [mu] m, and W_in= 400 占 퐉 (A, B) and W_act = 10 [mu] m, and W_in= 300 mu m (C). The red lines and arrows on each panel indicate the same positions on the same ribbons to emphasize mechanical deformation. The inserts provide an enlarged view of the portion marked with a white box and clearly show the occurrence of cracks in the high compression strains. Numbers corresponding to the tensile and compressive degrees were calculated according to the following equation.

29 is a photograph of a sample with a two layer buckling GaAs ribbon array. The structure is fabricated in a layer by layer manner. A first layer of GaAs ribbon (60% pre-strain and W_act = 10 [mu] m, and W_in= 400 [mu] m) is embedded within the PDMS. The second layer of buckled ribbons has a pre-strain of 50% and W_act = 10 [mu] m, and W_in= 300 [micro] m.
Figure 30 shows the bending of the buckled ribbons on the surfaces of the PDMS and in the matrix. AC is a low magnification (upper left frame) and a higher magnification (right frame) of buckled GaAs ribbons on a PDMS with concave or flat (A), flat (B) or convex (C) Frames). ≪ / RTI > The scale bars in c apply to a and b. d is the image of the buckled ribbons embedded in the PDMS before (left) bending and (right) bending. The scale bar in the right image applies to the left images as well. The buckled ribbons have a pre-strain of 60% and W_act= 10 [mu] m, and W_in= 400 탆.
Figure 31 is a characterization of a metal-semiconductor-metal photodetectors (MSM PDs) that are stretchable metal-semiconductor-metal photodetectors. A is a conceptual illustration of the geometry (above), an equivalent circuit (middle), and an optical image of the buckled PD (below) before and after tension. B are current (I) -voltage (V) curves recorded from a buckled PD illuminated by an IR lamp having different output intensities. The I-V characteristics of (D) when PD irradiated with a constant brightness are stretched to different degrees (C) or compressed (D).
Figure 32 illustrates that a hemispherical elastomeric transfer ' stamp ' can lift off Si CMOS 'chiplets' interconnected from conventional wafers and then convert their geometry into a hemispherical shape. The " pop-up " interconnections between the chippets accept transformations related to this planar to curved transition.
Figure 33 illustrates transfer of interconnected CMOS chips from a hemispherical stamp to a hemispherical device substrate that matches it. A photocurable adhesive layer couples the CMOS to the device substrate, and the surface is planarized.
Figure 34 shows a printer apparatus having a hemispherical stamp and a compatible fixturing, actuator and visualization system.
35 shows a compressible array of single crystal silicon islands electrically connected by " pop-up " ribbon interconnects, above a hemispherical stamp.
Figure 36 is an optical image of an interconnected monocrystalline silicon island array 'linked' over the surface of a hemispherical stamp having a radius of curvature of ~ 2 cm.
Figure 37 is stress / strain curves for various silicone elastomers that can be used for hemispherical stamps. Responses that are linear and completely elastic for strains less than 20% are important.
Figure 38 is a finite element modeling of spherical to planar transformation in a hemispherical stamp initially having a uniform thickness of 0.57 mm.
39 is a conceptual illustration of steps for fabricating a two-dimensional "waved" semiconductor nanomembrane on an elastic support.
40 (a) to (f) are optical microscope photographs of 2D wave structures at various stages in the process of forming silicon nanofibers. Insert images show two-dimensional power spectra. (g) is an image of a fully developed structure. For this sample, the thickness of silicon is 100 nm and the lateral dimension is ca. 4 × 4 mm², The substrate is PDMS, and the thermally induced pre-strain is 3.8%. (h) is a plot of a short wavelength corresponding to the frames (a to f), and (i) is a histogram of a long wavelength evaluated at various points of the frame (g).
41 is (a) AFM image (b to d) and SEM images (tilt angle 60 [deg.]) Of a 2D wave-wise Si nanomembrane over PDMS. The thickness of the silicon is 100 nm and the thermal pre-strain is 3.8%. These images illustrate the highly periodic nature of the wave pattern, a good bond between Si and PDMS as evidenced by close contact visible at the edges of PDMS and Si near the Si etched holes, The mutual irrelevance between the locations of these holes is interesting.
Figure 42 (a) is optical micrographs of 2D wave-grown Si nanofibers formed with a 3.8% thermal pre-strain and having various thicknesses (55, 100, 260, 320 nm) on PDMS, And the dependence of amplitude on the short wavelength.
Figure 43 (a) is optical micrographs of 2D wave-wise Si nanofibers under different uniaxial strains, applied in three different directions. These samples have a thickness of 100 nm on the PDMS and consist of Si films formed with a 3.8% thermal pre-strain. The images are shown in the relaxed state (top frames) before stretching, in the relaxed state after the stretch (bottom frames), and when the uniaxially applied tensile strain is 1.8% (second frame above) When it was collected (second frame from below). (b) show the dependence of the short wavelength on the strain applied in three different directions.
44 shows AFM images of different areas of the 2D wave-wise Si nanofibers, in which an area (upper frame) near the edge of the film, an area slightly spaced from this edge area (middle frame), and an area near the center of the film 1D wave geometric characteristics of the wave. This sample consists of a Si film formed with a 3.8% thermal pre-strain, with a thickness of 100 nm on the PDMS.
Figure 45 is optical micrographs of 2D wave-grown Si nanofibers having a length of 1000 [mu] m and widths of 100, 200, 500, and 1000 [mu] m. These films all have a thickness of 100 nm and were formed on the same PDMS substrate by (a) 2.3% and (b) 4.8% thermal pre-strain. (c) shows the dependence of the edge effect length on the pre-strain in the similar films.
Figure 46 is optical micrographs of 2D waveguide Si nanofilms having different shapes of (a) circular, (b) elliptical, (c) hexagonal, and (d) triangular. All of these films had a thickness of 100 nm and were formed with 4.8% thermal pre-strain on PDMS.
Figure 47 is an optical micrograph showing the waved structures of Si nanofilms with shapes designed to use edge effects to give 2D tensile potential to an array of interconnected flat islands. In both of the cases shown here, the Si has a thickness of 100 nm, the squares are 100 x 100 mu m, and the ribbon connections are 30 x 150 mu m lines. Pre-transformation is (a, e) 2.3% and (c, g) 15%. SEM images (tilt angles of 75 °) of the selected regions showing the ribbons and squares of (a, c, e, g) are shown at (b, d, f, h), respectively. Insert images of high magnification SEM images show elevated areas of the waves at b and d.
Figure 48 shows a 2D wave Si nano-film on a PDMS substrate wave (100 nm thick, 4 x 5 mm²(Upper frame) and (1) 1D waves at the edge, (ii) herringbone waves in the further inner region, and (iii) Chaotic herringbone waves. The scale bar is 50 탆.
Figure 49 is a schematic diagram illustrating characteristic lengths in herringbone wave structures.
Figure 50 shows the Si strain as a function of thermal pre-strain applied in herringbone and 1D waves. The Si strain is ε_Si= (L-lambda) / lambda, where L and lambda are the surface and horizontal distance in the AFM surface profile.
Figure 51 shows the tensile test (~_st = 4.0%) of the herringbone waves after the cycles. The test sample was prepared with a Si film of 100 nm thickness and a 3.8% biaxial thermal pre-strain. Herringbone waves were restored to have a structure similar to the original, except for some defects due to film cracks, after up to 15 tensile test cycles.
Figure 52 schematically illustrates the " unfolding " of herringbone waves according to the application of a uniaxial tensile strain. Compressive strain ε_cpLt; RTI ID = 0.0 >_st(Poisson effect). ≪ / RTI >
Figure 53 is optical microscope images of the morphological changes of herringbone waves during the heating and cooling process as a biaxial tensile test. The test samples were prepared with a 100 nm thick Si film and a 2.9% biaxial thermal pre-strain.
Figure 54 illustrates a method of fabricating wired and tensionable electrodes by structuring and depositing onto a waved master, then casting the stamp onto the master, curing the stamp, and thereby transferring the electrodes to the master with release, One method of manufacturing is summarized.
Figure 55 provides images of the stretchable metal electrodes (Au, 300 nm thick) on the waved PDMS fabricated by the methods of Figure 4 in combination with the method of Figure 54. The bottom panel is a graph showing the electrical resistance measurement data of the tensile and wavy metal electrodes as a function of the applied tensile strain (up to 30%).
56 is an application example of the present method for manufacturing a flexible and stretchable iLED strip-light source. (a) is a microphotograph showing that the device can be significantly bent, and in this embodiment the bending radius is 0.85 cm. (b) provides a cross-section (top panel, 40 μm scale bar) and plane (bottom panel, 3 mm scale bar) of the stretchable metal on the wafers PDMS substrate. The metal is about 30% tensile without significant deterioration of physical properties. (c) is a graph showing the effect of local deformation on the amplitude (circle, right axis) and wavelength (square, left axis) of the sine wave-wised metal interconnects (shown in (b)). As the deformation increases, the wavelength of the metal increases and the amplitude decreases.
Figure 57 is a schematic representation of an approach based on printed semiconductor nanomaterials for heterogeneous three-dimensional electronic devices. The process may include repeatedly transferring and printing a collection of nanotubes, nanowires, nanoribbons, or other active nanomaterials individually formed over the source substrates onto a common device substrate to form interconnected electrons having ultra-thin multi-layer stack geometry ≪ / RTI > device.
Figure 58 (A) is an optical microphotograph of a three-dimensional multi-layer stack of single crystal silicon metal oxide field effect transistors (MOSFETs) using silicon nanoribbons printed for semiconductors. The bottom portion (labeled 1st), the middle portion (labeled 2nd), and the top portion (labeled 3rd) of this image correspond to regions having one, two, or three layers of the device, respectively. (B) are a schematic sectional view (upper) and a perspective view (lower). S, D, and G indicate source, drain, and gate electrodes (all shown in gold). Bright and dark blue regions correspond to doped and undoped regions of the silicon ribbons; The purple layer is SiO₂ Gate dielectric. (C) are three-dimensional images (left frame: top view, right frame: perspective view) collected by confocal microscopy on a device substrate as shown in (A) and (B). The layers were colored for the convenience of identification (gold: top layer; red: interlayer; blue: bottom layer; silicone: gray). (D) is the current-voltage characteristic of the Si MOSFET in each layer, and has excellent performance (470 ± 30 cm²/ Vs) and good uniformity of properties. The channel length and width are 19 and 200 탆, respectively.
59 (A) is an optical microphotograph of a three-dimensional heterogeneous electronic device including GaN nanoribbon HEMTs stacked in three layers, Si nanoribbon MOSFETs, and SWNT network TFTs. (B) is a three-dimensional image collected by a confocal microscope. Layers were colored for ease of identification (gold: top layer, Si MOSFETs; red: middle layer, SWNT TFTs; blue: bottom layer). (Channel length, width, and gate width of 20, 170, and 5 占 퐉, respectively), SWNT elements on the second layer (channel length and width of 50, 200 탆), and the Si characteristics of the third layer (channel length and width are 19 and 200 탆, respectively). (D) shows the normalized transconductance (g) of each layer (black square: Si MOSFETs; red circle: SWNT TFTs; green triangle: GaN HEMTs)_m/ g_0m) As a function of the bending radius of the plastic substrate (left). The image of the bent system and probing device (right).
Figure 60 (A) is an image of a printed array of 3D silicon NMOS inverters on a polyimide substrate. The inverters have MOSFETs (channel length is 4 [mu] m, load-to-driver width ratio is 6.7, and driver width is 200 [mu] m) on two different levels and interconnected by an electrical via structure ). The upper right image provides an enlarged view of the area indicated by the red box in the left frame. The lower right graph shows the transfer characteristics of a typical inverter. (B) are transfer characteristics of printed complementary inverters using p-channel SWNT TFTs (channel length and width of 30 and 200 μm respectively) and n-channel Si MOSFETs (channel length and width of 75 and 50 μm respectively). The inserted image is an optical microscope photo (left) and a circuit schematic (right). (C) shows a GaAs MSM (channel length and width of 10 and 100 μm, respectively) and Si MOSFETs (channel length and width of 9 and 200 μm, respectively) at different levels up to 11 μW with an infrared light source of 850 nm from dark, Lt; / RTI > The inset shows an optical image and a circuit diagram.
Figure 61 is an image of an automated transfer-printing stage capable of printing registration up to ~ 1 占 퐉.
62 (A) is an optical microscope photograph of an array in which Si MOSFETs and GaN HEMTs are three-dimensionally integrated on a polyimide substrate. The right inset is a schematic cross section. Electrodes (gold), SiO₂(PEO), Si (light blue: undoped part; dark blue: doped part), GaN (dark green: ohmic contacts; light green: channel), polyimide (PI: brown) PU; tan) are all shown. (B) show the current-voltage characteristics of conventional Si MOSFETs (channel length and width are 19 and 200 μm respectively) and GaN HEMTs (channel length, width and gate width are 20, 170 μm and 5 μm, respectively). The data for Si and GaN in the left frames are V_dd = 0.1 V and V_dd = 2V.
63 (A) is an optical microscope photograph of an array in which Si MOSFETs and SWNT TFTs are three-dimensionally integrated on a polyimide substrate. The right inset is a schematic cross section. Electrodes (gold), epoxy (cyan), SiO₂(PEO; purple), Si (light blue: undoped portion; dark blue: doped portion), SWNT (gray), polyimide (PI: brown) and cured polyimide (tan) are all shown. (B) show current-voltage characteristics of a conventional SWNT TFT (channel length and width are 75 and 200 μm respectively) and Si MOSFET (channel length and width are 19 and 200 μm respectively). The data for SWNT and Si in the left frames are V_dd= -0.5 V and V_dd= 0.1V.
64 (A) is a cross-sectional schematic view of an array in which Si MOSFETs, SWNT TFTs and GaN HEMTs are three-dimensionally integrated on a polyimide substrate. (B) shows the transfer characteristics, effective mobility, and on-off characteristics for various Si MOSFETs (channel width = 200 탆, black line: channel length = 9 탆, red: 14 탆, green: 19 탆, / Off ratio. (C) is SWNT TFTs (channel width = 200 mu m, black line: channel length = 25 mu m, red: 50 mu m, green: 75 mu m, and blue: 100 mu m). And (D) represent transfer characteristics, transconductances, and on / off ratio for GaN HEMTs (channel length, width, and gate width are 20 μm, 170 μm, and 5 μm, respectively).
65 (A) is a schematic sectional structure of a SWNT-Si CMOS inverter fabricated on a silicon wafer substrate. (B) are the transfer and I-V characteristics of an n-channel Si MOSFET and a p-channel SWNT TFT forming a CMOS inverter. (C) are the calculated transfer characteristics of the inverter and the I-V characteristics of the Si and SWNT transistors.
Figure 66 (A) is a conceptual cross-sectional schematic and schematic circuit diagram of a GaAs MSM-Si MOSFET IR detector fabricated on a polyimide substrate. (B) are the current-voltage characteristics of the GaAs MSM IR detector (L = 10 μm, W = 100 μm) for the 3 V supply and the transfer and I-V characteristics of the Si MOSFET (L = 9 μm, W = 200 μm). (C) is the calculated IV characteristics of the GaAs MSM versus the 3V supply and the I-V response of the GaAs MSM integrated with the Si MOSFET.
67 conceptually illustrates an optical device (a waveguide array) fabricated through controlled buckling of optical microstructures partially adhered to a deformable substrate.
68 conceptually illustrates a mechanical device (e.g., an acceleration / pressure sensor) fabricated through controlled buckling of a conductive microstructure partially adhered to a deformable substrate.
Figure 69 conceptually illustrates a thermal device (microbolometer) manufactured through controlled buckling of a heat resistant microstructure partially adhered to a deformable substrate.

"Stretchable" refers to the ability of a material, structure, device, or device component to be deformed without destruction. In a typical embodiment, a tensile material, structure, device, or device component is capable of withstanding deformation greater than about 0.5% without destroying, preferably capable of withstanding deformation greater than about 1% in some applications, And more preferably more than about 3% in some applications.

"Component" is widely used to refer to a material or individual components used in a device. "Interconnect" refers to an electrically conductive material that can form an electrical connection between a component and / or a component as an example of a component. In particular, the interconnects may form electrical contact between components that are separated and / or movable relative to each other. The interconnects are made of a suitable material depending on the specification, operation and application of the desired device. For applications requiring high conductivity, conventional interconnect metals may be used including, but not limited to, silver, gold, aluminum, and alloys thereof. Suitable conductive materials may include semiconductors such as silicon, indium tin oxide, or GaAs.

"Semiconductor" refers to any material that is an insulator at very low temperatures but has significant electrical conductivity at temperatures of about 300 Kelvin. In the detailed description of the present invention, the term semiconductor is intended to be used consistent with the use of the term in the art of microelectronics and electronic devices. Semiconductors useful in the present invention include element semiconductors such as silicon, lowermanium, and diamond and Group IV compound semiconductors such as SiC and SiGe, AlSb, AlAs, AlIn, BN, GaSb, GaAs, GaN , GaP, InSb, InAs, InN , and the III-V group semiconductor such as InP, Al _x Ga _{1 -} the Group III-V ternary semiconductor alloy, such as _{x as, CsSe, CdS, CdTe} , ZnO, ZnSe, ZnS II-VI semiconductors such as ZnTe, I-VII semiconductors such as CuCl, IV-VI semiconductors such as PbS, PbTe and SnS, layered semiconductors such as PbI ₂ , MoS ₂ and GaSe, CuO and it may include a compound semiconductor such as an oxide semiconductor, such as Cu ₂ O. The term semiconductor is intended to include both intrinsic semiconductors and extrinsic sources doped with one or more selected materials, including semiconductors with p-type doping materials and n-type doping materials, to provide advantageous electronic properties useful in a given application or device. Including extrinsic semiconductors. The term semiconductor includes complex materials comprising a mixture of semiconductors and / or dopants. Specific semiconductor materials useful in some applications of the present invention include Si, Ge, SiC, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, GaSb, InP, InAs, InSb, ZnO, ZnSe, ZnTe But are not limited to, CdS, CdSe, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, PbS, PbSe, PbTe, AlGaAs, AlInAs, AlInP, GaAsP, GaInAs, GaInP, AlGaAsSb, AlGaInP, . Porous silicon semiconductor materials are useful for applications of the present invention in the field of sensors and light emitting materials such as light emitting diodes (LEDs) and solid state lasers. The impurities of the semiconductor materials are atoms, elements, ions and / or molecules that are not the semiconductor material (s) themselves or any of the dopants provided in the semiconductor material. Impurities include, but are not limited to, metals, including oxygen, carbon, and heavy metals, which are present in semiconductor materials and are undesirable materials that adversely affect the electronic properties of semiconductor materials. Heavy metal impurities include, but are not limited to, the family of elements between copper and lead on the periodic table, calcium, sodium, and all their ions, compounds, and / or complexes.

"Semiconductor element" and "semiconductor structure" are used synonymously in this specification to refer to any semiconductor material, composition or structure broadly and include high quality monocrystalline and polycrystalline semiconductors Such as semiconductor materials, doped semiconductor materials, organic and inorganic semiconductors, and one or more additional semiconductor constructing materials and / or dielectric layers or materials and / or conductive layers or materials manufactured through a high temperature process ≪ / RTI > includes explicitly compound semiconductor materials and structures with non-semiconductor constituent materials.

"Stretchable" interconnections may be formed from a variety of materials, such as tensile, bending and / or compressing in one or more directions without adversely affecting electrical connection to the device components or electrical conduction from the device components. Are used herein to broadly refer to interconnects that are capable of withstanding deformations and forces. Thus, the tensile interconnection may be formed of a relatively brittle material, such as GaAs, and the geometry of the interconnect may expose it to considerable deforming forces (e.g., tensile, bending, compressing) It can remain so as to continue to function. In a typical embodiment, the tensionable interconnect can withstand strains greater than about 1%, 10%, or about 30% without breaking. In one embodiment, the deformation is created by tensioning the underlying elastomeric substrate to which at least a portion of the interconnect is coupled.

"Device component" is used to broadly refer to an individual component within an electrical, optical, mechanical, or thermal device. The components may include one or more photodiodes, LEDs, TFTs, electrodes, semiconductors, other light-focusing / sensing components, transistors, integrated circuits, contact pads capable of accommodating device components, , Control elements, microprocessors, transducers, and combinations thereof. The device components may be connected to one or more contact pads as is known in the art, such as, for example, metal evaporation, wire bonding, application of solid or conductive pastes. An electrical apparatus generally refers to an apparatus that includes a plurality of device components and includes a large area electronic device, a printed wire substrate, an integrated circuit, an array of device components, biological and / or chemical sensors, physical sensors (E.g., temperature, light, radiation, etc.), solar cells or photovoltaic arrays, display arrays, optical collectors, systems and displays.

"Substrate" refers to an object having a surface capable of supporting a device component or a component including an interconnect. An "coupled" interconnect to the substrate is a portion of the interconnect that is in physical contact with the substrate, which portion is substantially non-movable relative to the substrate surface to which it is coupled. In contrast, unbonded portions are capable of substantial movement relative to the substrate. The unbonded portion of the interconnect generally corresponds to the portion having a "bend configuration" such as by deformation-induced interconnect bend.

A component forming a "conformal contact" with the substrate maintains a three-dimensional relief structure while covering the substrate, wherein the relief pattern of the three-dimensional relief structure is dominated by a pattern of relief structures Points to components.

In the context of this Detailed Description, the term "bent configuration" refers to a structure having a curved shape caused by the application of force. In the present invention, the bending structures may have one or more of a folded region, a convex region, a concave region, and any combination thereof. The bending structures useful in the present invention may be provided, for example, in a coiled, corrugated, buckled and / or wavy (i.e., wavy) configuration.

The bending structures, such as the tensionable bending interconnections, may be coupled to the flexible substrate, such as a polymer and / or an elastic substrate, in a deformed manner. In some embodiments, a flexure structure, such as a curved ribbon structure, may provide a deformation of less than or equal to about 30%, or a deformation less than or equal to about 10%, in some preferred embodiments less than about 5% Small or the same strain, and less than or equal to about 1% strain. In some embodiments, the bending structure, such as a bent ribbon structure, has a strain selected from the range of about 0.5% to about 30%, a strain selected from the range of about 0.5% to about 10%, a range of about 0.5% to about 5% ≪ / RTI > Optionally, the tensionable crimp interconnections may be coupled to the substrate, which is a substrate of the device component, including a substrate that is not itself flexible. The substrate itself may be flat, substantially flat, curved, sharp edges, or any combination thereof. Tensile, curved interconnections may be used to transfer to any one or more of these complex substrate surface shapes.

"Thermal contact" refers to the ability of two materials to conduct substantial heat transfer from a high temperature material to a low temperature material, such as conduction. The bent structures placed on the substrate may be in contact with other regions that are not in thermal contact with regions (e.g., junction regions) that are in thermal contact with the substrate (e.g., insulated and / or physically spaced from the substrate Regions). ≪ / RTI >

The interconnects may have any number of geometries or shapes as long as they facilitate bending or tensioning of the geometries or shapes without damaging the interconnect. The geometry of a typical interconnect may be described as being "buckled" or "wavy ". In one aspect, such a geometry is characterized in that a change in the dimensions of the underlying substrate is applied to the interconnects by a buckle (not shown) because portions of the interconnect are coupled to the substrate and regions between the joined portions are not coupled. (e. g., strain) to the interconnection by applying a force to the deformable substrate underlying it to generate buckles or waves. Thus, the individual interconnections can be defined by the ends coupled to the substrate and the curved central portion, which is not coupled to the substrate, between the ends. "Curved" or "buckled" refers to relatively complex shapes, such as by interconnections having one or more additional bonding regions in the central portion. "Arc-shaped" refers to a general sinusoidal shape with amplitude, where the amplitude corresponds to the maximum separation distance between the interconnect and the substrate surface.

The interconnects may have any cross-sectional shape. One form of the interconnect is a ribbon-like interconnect. "Ribbon" refers to a substantially rectangular-shaped cross-section having a thickness and a width. The specific dimensions depend on the conductivity through the desired interconnect, the composition of the interconnect, and the number of interconnects that electrically connect neighboring device components. For example, the interconnections in the bridge configuration that connect neighboring components can have different dimensions from a single interconnect connecting neighboring components. Thus, the dimensions may be in a range of widths between about 10 [mu] m and 1 cm, and thicknesses in the range of between about 0.001 and 0.1, such as between about 50 nm and 1, or a thickness of about 0.01 As long as a suitable electrical conductivity, such as a ratio of the width to the width, is produced.

"Elastomeric" refers to a polymeric material that can be at least partially restored to its original state without substantial permanent deformation after being stretched or deformed. Elastomeric materials are generally resistant to deformations of elasticity. Exemplary elastomeric materials useful in the present invention include, but are not limited to, composite materials or mixtures of elastomers and elastomers, and resilient polymers and copolymers. In some methods, the elastomeric substrate is prestrained through a mechanism that provides for the expansion of the elastic substrate along one or more principle axes. For example, prestraining can be provided by stretching the elastic substrate along the first axes, including extension in the radial direction, to convert the hemispherical surface to a flat surface. Optionally, the elastic substrate can be stretched along a plurality of axes, for example, along a first axis and a second axis, which are positioned perpendicular to each other. The means for pre-deforming the elastic substrates through a mechanism that provides extension of the elastic substrate may include bending, rolling, flexing, flattening, expanding, or otherwise . The pre-deforming means includes a pre-deformation provided by raising the temperature of the elastic substrate and thereby providing thermal expansion of the elastic substrate. The elastomers useful in the present invention may be selected from the group consisting of thermoplastic elastomers, styrenic materials, olefinic materials, polyolefins, polyurethane thermoplastic elastomers, polyamides, synthetic rubbers, PDMS, polybutadiene, polyisobutylene, poly (Styrene-butadiene-styrene), polyurethanes, polychloroprene, and silicone.

The strain is defined as ε = ΔL / L for a change in length from L (resting period) to L + ΔL (force applied state). Here,? L is the distance displaced from the resting period. The axial deflection refers to the force applied to the axis of the substrate to produce the displacement [Delta] L. Deformation is also produced by forces acting in different directions, such as bending force, compressive force, shear force, and any combination thereof. Deformation or compression may be produced by stretching the curved surface to a flat surface or vice versa. The "level of strain" refers to the magnitude of the strain and can range from negative (corresponding to compression) to zero (relaxed state) to positive (corresponding to stretch or tension).

"Young's modulus" refers to the mechanical properties of a material, device or layer and refers to the ratio of stress to strain for a given material. The zero modulus can be provided by the following expression.

&Quot; (2) "

Where E is the zero modulus, L ₀ is the equilibrium length, L is the change in length under the applied stress, F is the applied force and A is the applied force area. In addition, the Young's modulus can also be expressed as terms of Lame constants through the following equation (3).

&Quot; (3) "

Where lambda and mu are Lame constants. A high (or "high modulus") and a low (or "low modulus") zero or zero modulus is a relative description of the magnitude of the zero modulus in a given material, layer, or device. In the present invention, it is preferred that the high Young modulus is about 10 times larger in some applications than in the low Young modulus, more preferably about 100 times larger in other applications, and in still other applications And even more preferably about 1000 times larger. Complex surface shapes are obtained by polymerizing an elastomer having a spontaneously changing Young's modulus and / or by laminating an elastomer having multiple layers to various locations having different elasticities.

Compression is used here in a similar manner to deformation, but specifically refers to forces acting to reduce the characteristic length or volume of the substrate to be? L <

"Fracturing" or "fracture" refers to a physical breakdown in the interconnect that causes the interconnect portion to be unable to conduct substantial electrical conduction.

"Pattern of bond sites" means that the supporting means are applied spatially to the supporting substrate surface and / or to the interconnects so that the supported interconnects have bonding regions and non-bonding regions with the substrate . For example, an end of which is bonded to the substrate, and a central portion of which is not bonded. Additional shape adjustment is possible by providing additional engagement locations in the central portion such that the unbonded region can be divided into two distinct central portions. The bonding means may include adhesives, bonding precursors, welding, photolithography, photopolymerizable polymers. Generally, bonding locations can be patterned by a variety of techniques and have relatively low adhesion to surface-activated (W _act ) areas that can provide strong adhesion between the substrate and the structure (e.g., interconnects) Can be expressed in terms of weak surface-deactivated (W _in ) areas. The substrate is bonded to the patterned lines can be represented as a term of dimension of W and W _{in act.} These variables affect the geometry of the interconnect with the size of pre-transformation ε _pre .

"Spatial variation" refers to a parameter having a varying size along a surface and provides a two-dimensional control of the component relief structures thereby providing spatial control over the bendability of the device or device components Lt; / RTI &gt;

"Carbon nanomaterial" refers to a class of structures containing carbon atoms and has at least one dimension between 1 nanometer and 1 micron. In one embodiment, at least one dimension of the carbon nanomaterial is between 2 nm and 1000 nm. Carbon nanomaterials can be used for single walled nanotubes (SWNTs), multiwalled nanotubes (MWNTs), graphite, graphene, carbon fibers, carbon films, carbon whiskers, And diamonds, and all derivatives thereof.

"Spatially aligned" refers to positions and / or orientations defined relative to each other of two or more structures. Spatially aligned structures are preselected for each other, for example, preselected to within 1 micron, preferably pre-selected for less than 500 nanometers for some applications, and less than 50 nanometers for some applications More preferably selected positions and / or orientations.

"Heterogeneous semiconductor elements" are multi-component component structures that include semiconductors combined with one or more other materials or structures. Other materials or structures in the context of this description may include materials and / or structures having different chemical compositions and / or physical states (e.g., crystalline, semi-crystalline or amorphous) And different elements, molecules, and complexes, agglomerates, and particles thereof. The hetero semiconductor elements useful in this aspect of the invention include other semiconductor materials combined with an inorganic semiconductor structure, the other semiconductor materials including doped semiconductors (e.g., N-type and P-type dopants) Carbon nanomaterials or films thereof, dielectric materials and / or structures, and conductive materials and / or structures. The heterogeneous semiconductor elements of the present invention include structures having a spatially homogeneous composition such as uniformly doped semiconductor structures, and may be formed as a semiconductor structure having a dopant with a spatially varying concentration in one-dimensional, two-dimensional or three- And spatially heterogeneous compositions (i. E., Spatially heterogeneous dopant distribution in the semiconductor element) structures.

The invention may be better understood by the following non-limiting embodiments. All references cited herein are incorporated herein by reference to the extent not inconsistent with what is disclosed herein. Although the description herein includes many specific details, they should not be construed as limiting the scope of the invention, but merely as exemplifications of some of the presently preferred embodiments of the invention. Accordingly, the scope of the present invention should be determined by the appended claims and their equivalents, rather than by the given embodiments.

One of the methods for fabricating buckled or wired interconnections is outlined generally in FIG. A metal structure 10 (such as a metal structure to be interconnected) is provided on the substrate 20. The metal structures and / or substrate surfaces that are in contact are selectively treated with photolithography or with a shadow mask to reduce adhesion. A separation part (crack) 25 is introduced between the structure 10 and the substrate 20 by micromachining, etching and / or mechanical scribing. The metal structure 10 is recovered as a compliant elastomeric stamp 30. Subsequent deformation of the stamp 30 creates a wavy or buckled geometry 40 in the metal structure 10. The generation of the buckles is provided by stamp 30 which is deformed when the metal structure 10 is withdrawn and subsequently releases the applied tension, or by compressing the stamp 30 after the metal structure is recovered do.

One embodiment of a buckled or woven metal structure produced by the method summarized in FIG. 1 is shown in FIG. 2 is a photograph of a tensionable, waved / buckled electrical interconnect 40. The interconnects 40 are formed by withdrawing from the rigid substrate onto the pre-deformed and stretchable PDMS rubber substrate 30, and then releasing the deformation and thereby causing buckling.

A method for creating electrodes and / or interconnects that can be waved and stretched is provided in Fig. As shown in Figure 3 (a), the waved structures 22 are prepared on the substrate 20, such as, for example, by micromachining processes. The substrate 20 having a surface with the wave-like structures 22 serves as a master for molding the elastomeric stamps 30 with the corresponding wobbled surface 32. The metal structures 10 are deposited on the waved surface 32 by, for example, evaporation and / or electrodeposition through a shadow mask.

Figure 4 provides a method for making a smoothly waxed elastomeric substrate. The etching of the anisotropic Si (1 0 0) provides the substrate 20 with sharp edges 24 (Fig. 4 (b) - top panel). The spin of the PR smoothes the valleys with the sharp edges by depositing the PR 26 in the valleys 24 with the sharp edges of the substrate 20. [ An elastomeric stamp (34) is cast onto the substrate (20). The stamp 34 has recessed structures with sharp edges. A second elastomeric stamp 36 is cast on the stamp 34 to produce a stamp having peaks with sharp edges. Stamp 36 is embossed with Su-8 (50) and cured as appropriate. The spin PR 26 smoothes the valleys with sharp edges of (50). The elastomeric substrate 30 is cast on (50) with smooth valleys. The substrate 30 is exposed to reveal a wavy and smooth surface 32.

54 illustrates a method for manufacturing electrodes that can be waved and stretched by depositing onto a waved master, then casting the stamp onto the master, and curing the stamp, thereby transferring the electrodes to the master with release . Figure 55 shows images of stretchable metal electrodes (Au, 300 nm thick) on a wavy PDMS fabricated by combining the methods shown in Figure 4 with the methods shown in Figure 54. The interface 112 is shown between the metal structure 10 and the substrate 20. The interface 112 may include a material that facilitates removal of the metal structures 10 by the stamp 30 shown in the lower panel. Briefly, one method utilizes the following: Spin on a thin coating of SU-8 10 so that the glass surface is completely covered on a pre-cleaned 2 "x 3" glass slide. Slide / SU-8 is contacted with a PDMS stamp with the desired wavefront surface structure (smooth valleys and sharp peaks) and pressure is slowly applied to remove all air bubbles. The stamp / mold structure is flash cured for 30 seconds against the front side under a UV lamp, and turned over for a further 40 seconds against the back side. After curing, baking is carried out on a hot plate at 65 ° C for 5 minutes. After baking, allow the sample to cool to room temperature and then peel off the SU-8 mold from the PDMS master. The SU-8 will now have a wavy surface embossing structure with valleys with sharp edges. To smooth these valleys, a portion of SU-8 2 is mixed with a portion of the more dilute SU-8 and spun for 90 seconds at high RPM. Cure by exposure to UV light for 20 seconds, and post-baked at 65 占 폚 for 3 minutes. Once cooled, metal lines or contacts are deposited through electrodeposition, photolithography, and evaporation through an etch / lift-off, and / or shadow mask. The metal on SU-8 is treated with MPTMS for 1 hour, and then an elastomeric substrate is cast thereon. When PDMS is removed, it has a wave-like surface relief structure with valleys and valleys smoothed together with the transferred metal structures. Figure 55 is a photograph of a waved and stretchable electrode made by the process outlined in Figure 54; Figure 55 also provides measured electrical resistance data of the tensile and wavy metal electrodes as a function of applied tensile strain (up to 30%).

An embodiment of a smoothly waved PDMS substrate 30 made by the method summarized in FIG. 4 is provided in FIG. The device components 60 may be supported on a nonwoven area (e.g., a substantially flat area) of the wobbled substrate 30 and connected to the interconnect 10 as desired.

An embodiment in which a smoothing layer is spin-coated in a valley or recessed structure having sharp edges is shown in FIG. The substrate 34 (Figure 6a) with sharp edges is smoothed by spin-coating the photocurable epoxy 26 to produce a smoothly wobbled substrate. An elastomeric (e.g., PDMS) stamp 30 having a smoothly waved surface 32 is obtained by casting a PDMS stamp onto the substrate of Figure 6b and then removing the stamp 30 from the substrate 34 Loses.

Figure 7 is a photograph of a tensionable electrode. 7A is a cross-sectional photograph of an elastomeric substrate 30 having a waved surface 32. Fig. Figure 7b is a micrograph taken from above of an electrode made by evaporation of metal (10) on the waxed elastomer substrate surface (32). The focal plane of the image is above the peaks of the wave-like embossed structure. In FIG. 7C, the focal plane is above the valley of the corrugated wave structure and the metal interconnect 10 is in electrical contact with the electrode 250. The stretchable electrode is deposited by evaporation through a shadow mask on a smoothly waxed elastomer substrate. In this embodiment, the electrode 250 maintains conductivity and connectivity through the interconnects 10 during tension up to about 10% in tension.

The methods and apparatuses disclosed herein can be used to manufacture a variety of electronic devices, including, for example, a pullable passive matrix LED display (see FIG. 8). Waveguided electrodes (e.g., interconnects 10 and contact pad 70) are patterned over the two elastomeric substrates 30. The device components 60 (ILED pixels in this case) are patterned on the contact pads 70 on the wobbled electrodes by transfer printing. The two substrates 30 are suitably assembled so that the interconnections 10 run in different directions (vertically in this embodiment). The 2-D mechanical tensile potential of this passive matrix LED display is shown in FIG. The display can be uniaxially and biaxially stretched, as well as being capable of substantial bending without breakage. Such multi-axial bending provides the ability to produce curved electronic devices and also to mold electronic devices on curved surfaces to integrate them into smart electronic fabrics or displays.

One embodiment of such a curved electronic device is provided in Fig. Figure 10 shows an "artificial eye" comprising an array of inorganic light diodes distributed over a lens that forms the spherical surface. Four different views of the artificial array are shown. The requirements for stretchable planar electronic devices are conceptually illustrated in FIG. The sheet must be tensioned in two or more directions to wrap the flat sheet around the surface of the sphere.

12 is a manufacturing method for manufacturing a tensile buckled semiconductor array that can match a curved surface. The thin Si elements are fabricated by selective deposition of Au or Ti / Au on the substrate as shown in the "mother wafer" in panel (i). Si is pre-deformed and bonded to a UVO-treated PDMS (panel (ii)) (labeled L + DELTA L). The pre-distortion is provided in two directions as shown. The bonding may be by any means known in the art, for example, an adhesive applied to the Si element, to the substrate, or both. The joining means are configured such that the Si is bonded to other regions that remain in contact with the substrate (after deformation) and that are not in physical contact with the substrate (e.g., Or regions that are relatively weakly bonded or unbonded relative to the adhesion force at the other end of the substrate. The pre-strained substrate is removed from the wafer substrate to expose a flat grid of semiconductor arrays (panel (iii)). While the substrate is relaxed from L + DELTA L to L, the device components 60 (e.g., semiconductor Si contact pads) remain coupled to the substrate 30 while the interconnects 10 Is buckled in a bent configuration in the weakly bonded regions (see panel (iv)). Thus, the buckling interconnections 10 impart tensile potential to the entire array and are particularly useful for the assembly of other components 60 of the component 60 without damaging the electrical contact between the components 60. [ Thereby providing the ability to conform to a curved surface or a bendable surface.

13 shows a grid configuration (lower left panel) with a single grid configuration 140 (upper two panels), a plurality of connected interconnects 160, and a floral configuration 150 ) &Lt; / RTI &gt; of a buckling and tensionable silicone array. In each of these embodiments, interconnect 10 is buckled at a central portion, and the ends of the interconnect are attached to contact pad 70. The interconnects and the contact pad 70 are supported on the PDMS substrate 30. Close-up views of the geometries of many different interconnects are further provided in Figures 14-17. Fig. 14 provides electron microscope images showing a basic buckling or wave-wise interconnect 10 having a central portion 90 with a first end 100 and a second end 110. Fig. The central portion has a curved configuration. The ends 100 and 110 are connected to the device components and in this case to the contact pads 70, which can form electrical contact with the device components. The interconnects 10 and contact pads 70 are supported on a substrate 30, such as an elastomeric PDMS substrate.

15 is an electron microscope image of neighboring device components (e.g., contact pad 70) interconnected by a plurality (two) of interconnections 160. FIG. 15, it can be seen that neighboring device components 70 can be interconnected by one or more interconnections 10 to provide additional flexibility to the electronic device. For example, a device component or contact pad 70 having a relatively large footprint is selectively connected to other device components by multiple interconnects.

16 is an electron microscope image of the interconnections of the flower configuration 150. FIG. The flower configuration has interconnections oriented with three or more longitudinal directions, as opposed to a grid configuration. In the present embodiment, there are four distinct directions so that device components, such as contact pads 70, can contact diagonally adjacent device components. In the present embodiment, the interconnect 10 is electrically connected to device components (not shown), thereby dividing the central region 90 into two non-engagement regions 92 each having a bending configuration, And has an optional coupling region 102 between the interconnecting end 100 and the end 110.

17 is an electron microscope image of interconnection arrangements arranged in a bridge configuration (130). In the bridge configuration, three or more interconnect ends extend out of the bridge central portion peak 120. For example, two interconnects that intersect in the unbonded region lead to a peak 120 where the four interconnect ends extend therefrom. In a situation where device components are staggered, the peak 120 may have three ends extending therefrom. In the case of multiple interconnection connections between device components, more than four ends can extend from the peak 120.

While many of the figures provided herein show device components that are contact pads 70, the methods and apparatuses claimed herein are not suitable for use with a number of device configurations (e. G., &Lt; RTI ID = 0.0 &gt; Parts can be connected. For example, Figure 18 is a photodiode connected to another photodiode in an array configuration by buckling interconnections 10 supported on an elastomeric substrate 30 as a device component 60.

Figure 19 depicts the one-dimensional tensile behavior of a buckled silicon array. Panel (i) is a picture of a buckled silicon array without strain applied. A tensile force is applied (as indicated by the arrows above panel (i)) to stretch the array in one direction. As shown in panels (2) - (4), the buckled interconnections become flat. When the tensioning force is released in the panel 5, the array returns to its buckling configuration (see panels 6 to 8). A comparison of panel 1 and panel 8 shows that the buckle configuration before and after tensioning is the same, indicating that the process is reversible.

Buckled arrays of device components can be easily transferred to curved surfaces, including hard or inelastic curved surfaces. One embodiment of an apparatus and method for facilitating mating contact with curved surfaces is provided by the bubble or balloon stamp 400 of FIG. In this embodiment, the elastomeric substrate 30, which is a PDMS film of about 20 um thickness, is secured to the housing chamber 300 providing a chamber volume 310 defined by the housing chamber and the substrate wall facing inward. Applying a positive pressure (e.g., a pressure within the chamber 300 that is higher than the external pressure) creates a convex (200) substrate surface that can achieve conformal contact with the receiving substrate in a concave form. In contrast, the negative pressure creates a concave surface 210 that can make consistent contact with the receiving substrate in a convex form. The spatial manipulation of the local elasticity of the substrate (e.g., zero modulus) allows for the creation of complexly curved geometries. The lower left panel of FIG. 20 shows one of the means for adjusting the pressure in the housing volume 310 by a syringe that introduces gas into or removes gas from the chamber 310. The images on the right side of the figure are the different curvatures of the reacting PDMS film as increasing the level of positive pressure. Any methods and apparatus for providing interconnections that are buckled on an elastomeric substrate may be used with devices for transfer printing to a curved substrate.

Other means for creating buckled interconnects or pop-up interconnections on a curved surface are summarized in FIG. A thin elastomeric film is cast onto the shaped surface to create an elastomeric substrate having at least a curved portion. The substrate can be tensioned to flatten the surface such that the substrate can conform to both the curved surface and the flat surface. The interconnection is applied over the flat stamp and with the release of the tension force the substrate surface relaxes back into the bent geometry and a deformation is created in the interconnection which is accommodated by the pop- do.

An embodiment of "two-dimensionally" stretching a silicon array buckled by the apparatus shown in Fig. 20 is provided in Fig. In this embodiment, the interconnections comprise a plurality of buckled interconnection connections in a grid configuration. The interconnects are made of Si with a thickness of 290 nm. An initially flat, buckled silicon array (upper left image) is placed in the housing and a positive pressure is applied to inflate the array into a bubble or balloon configuration (e.g., a curved surface). The maximum expansion is shown in the rightmost image, and then the positive pressure is removed.

Similar to the results for uniaxial stretching of a flat substrate, this "bending" tension is reversible. The array can be transferred to the curved surface by any means known in the art at any stage of the swelling to maximize coherent contact with the curved surface. An example of silicon printing by balloon stamps on glass lenses coated with adhesives (elastomer substrate or SU-8) is shown in Fig. The lenses may be convex or concave. In this example, R = 19.62 mm and 9.33 mm, respectively.

Example 1: Controlled buckling structures in semiconductor nanoribbons and application examples in tensionable electronic devices

Control over the composition, shape, spatial location and / or geometry of semiconductor nanostructures is important for almost all applications of these materials. Although there are methods for defining the material composition, diameter, length, and positions of nanowires and nanoribbons, there are relatively few approaches for controlling their two- and three-dimensional (2D and 3D) configurations. A mechanical strategy for creating 3D forms of a given class that would otherwise have been difficult to produce in nanoribbons is provided herein. This embodiment involves using a combination of lithographically patterned surface chemistry to provide spatial control over the bonding position and elastic deformation of the support substrate to induce well controlled localized displacements. Precisely engineered buckling geometries are produced in this way in nano-ribbons of GaAs and Si, and these configurations can be quantitatively described in mechanical analysis models. As one application example, certain structures may be used in an electronic device having an extremely high level of tensionability (up to 100%), compressibility (up to 25%) and bendability (up to 5 mm radius of curvature) (And optical electronic devices).

The nanoribbons and wires in the 2D and 3D configurations are controlled during their growth to have specific geometries, such as coils, rings, and branched layouts. Or after their growth, by joining these elements to stretched elastomeric substrate or tube-shaped (or helical) structures using built-in residual stresses in the layered system, for example, a structure such as a sine wave Respectively. Semiconductor nanoribbons with wavy geometries are somewhat interesting because they enable high-performance, stretchable electronic systems for potential applications such as spherical curved focal plane arrays, intelligent rubber surgical gloves, and adaptive structure health monitors. This approach, in which the electronic devices themselves are tensionable, is different, complementary, or alternative to the same applications that use rigid device islands with tensionable metal interconnects. The wave nanoribbons described above have two main disadvantages: (i) they have almost no control over the geometry or phase of the wave, with fixed frequencies and amplitudes defined by the modulus of the material and the thickness of the ribbons; (Ii) the maximum deformations that they can accommodate are limited by non-optimal wave geometries obtained by this process in the range of 20-30%. The procedures introduced herein utilize lithographically defined surface adhesion locations with elastic deformation of the support substrate to achieve buckling configurations with deterministic control over their configuration. For any selected set of individual nanoribbons of large scale organized arrays of such structures, periodic or aperiodic designs are possible. Special geometries designed for tensile electronic devices enable a strain range of up to 150% even in fragile materials such as GaAs, which is 10 times more than previously reported, consistent with the mechanical analysis model Big.

Figure 24 shows the steps in this procedure. Fabrication begins with the fabrication of a mask for patterning surface chemical adhesion sites on a poly (dimethylsiloxane) (PDMS) elastomer substrate. The present process involves passing a deep UV (240-260 nm) through a photomask with a special type of amplitude photomask (made via step i), called UVO mask, in mating contact with the PDMS Step. The UVO mask has recessed features in the transparent region to produce patterned areas of ozone near the surface of the PDMS upon exposure to UV. Said ozone is a highly polar and reactive surface (i.e., an activated surface (not shown)) in which unmodified, -CH ₃ and -H terminated groups overwhelm hydrophobic surfaces with -OH and -O-Si-O- ). Unexposed areas retain unmodified surface chemistry (i.e., deactivated surfaces). The procedures introduced here involve exposure over PDMS substrates (thickness ~ 4 mm) under uniaxial large pre-strain (ε _pre = ΔL / L for length changes from L to L + ΔL) (Step ii). For a mask with simple, periodic line patterns, the activated and deactivated strips (indicated by the lines marked "activated surface") in step (iii) , The distance between neighboring activated bands) is expressed as W _act and W _in in step (i), respectively. The activated regions can bind strongly and irreversibly with other materials that expose -OH or -Si-O groups to the surface. As outlined below, these patterned adhesion locations are used to create well-defined 3D geometries within the nanoribbons. Optionally, a pattern of similar adhesive bonding locations is provided by similarly patterning interconnects prior to contacting the substrate.

In this embodiment, the nanoribbons are composed of both monocrystalline Si and GaAs. Silicon ribbons are fabricated from SOI (silicon-on-insulator) wafers using the procedures described above (Khang et al. Science 311, 208-212 (2006)). The GaAs ribbons were formed by Si-doped n-type GaAs (120 nm; carrier concentration of 4 x 10 ¹⁷ cm ³ ) formed on a (100) SI-GaAs wafer by molecular-beam epitaxy (MBE) Semi-insulating GaAs (SI-GaAs; 150 nm) and AlAs (200 nm). The ribbons are defined by chemically etching the epilayers in an aqueous etchant of H ₃ PO ₄ and H ₂ O ₂ using lines of photoresist patterned along the (0 1 1) crystal orientation, such as an etch mask. After removing the photoresist, the wafer was dipped in an ethanol solution of HF (ethanol: 49% HF aqueous solution at a ratio of 2: 1 by volume) to remove the AlAs layer, thereby obtaining a wafer having a width determined by the photoresist ) Of the GaAs (n-GaAs / SI-GaAs) having a thickness of about 100 mu m). The addition of ethanol to the HF solution reduces the probability of cracks in the ribbons that are prone to breakage due to the action of capillary forces during drying. A low surface tension (compared to water) may minimize the disorder caused by drying in the spatial arrangement of the GaAs ribbons. In the final step, a thin film of SiO ₂ (~ 30 nm) is deposited to provide the necessary -Si-OH surface chemistry to bond to the activated region of the PDMS.

The processed SOI or GaAs wafers were laminated on a UVO treated and pre-stretched PDMS substrate (ribbons oriented parallel to the direction of predisplash), baked in an oven at 90 &lt; 0 &gt; C for several minutes, The wafer transferred to the surface of the wafer is removed (step (iv)). Heating is achieved by a combination of a strong contact between the activated region of the PDMS and a native SiO ₂ layer on Si ribbons or a deposited SiO ₂ layer on the GaAs ribbons (ie, -O-Si- O-). &Lt; / RTI &gt; A relatively weak van der Waals force couples the ribbons to the inactivated surface areas of the PDMS. Relaxing the strain in the PDMS creates buckling through the ribbons being physically separated from the deactivated regions of the PDMS (step (v)). The ribbons remain bound to the PDMS due to strong chemical bonds in the activated regions. The resulting 3D ribbon geometry (i.e., the spatially varying pattern of buckling) depends on the size of the pre-strain and the patterns of surface activation (e.g., the shapes and dimensions of W _in and W _act ) . (Similar results can be achieved through the patterned joining locations on the ribbons). In the case of a simple line pattern, W _in and pre-distortion determine the width and amplitude of the buckling. Sinusoidal waves with much smaller wavelengths and amplitudes than the buckling were formed in the same ribbons due to the mechanical instability of the type that produced 'waveguide' silicon when W _act was> 100 μm. (See Figure 25, images of samples formed for different W _act ). As a final step of the fabrication, the 3D ribbon structures can be encapsulated within the PDMS by casting and curing a liquid prepolymer (see FIG. 24, step (vi)). The liquid flows due to low viscosity and low surface energy to fill the gap formed between the ribbons and the substrate (see FIG. 26).

Figure 24 (d) shows an image of a tilted-view scanning electron microscope (SEM) of GaAs ribbons buckled over PDMS. In this case, ε _pre = 60%, and W _act = 10 mu m, and W _in = 400 mu m. The image shows uniform and periodic buckling in which all the ribbons in the array have coherent phases with a common geometry. The anchoring points are well matched to the lithographically defined attachment locations. The inset picture is a SEM image of the combined area. The width is ~ 10 μm, which corresponds to W _act . The images show that the surface of the PDMS is also flat at the bonding locations. This behavior, which is significantly different from previously reported strongly coupled wave structures, is that in the case described here, PDMS induces displacement but is not closely involved in the buckling process (i.e., No effect on the structure). In this sense, PDMS represents a soft, non-destructive tool that can manipulate the ribbons through forces applied to attachment locations.

Figure 27 (a) shows a side-view optical micrograph of buckled ribbons having different ε _pre (W _act = 10 μm, W _in = 190 μm) formed on the PDMS. The heights (e.g., "amplitude") of the buckles increase with? _Pre . Ribbons in the deactivated regions were not completely isolated at low ε _pre (see samples formed for ε _pre = 11.3% and 25.5%). At high [epsilon] _preps , the ribbons (thickness h) separate from the PDMS to form buckling rings having vertical displacement profiles that are characterized by the following equation.

here,

It is determined by the nonlinear analysis of the buckles formed on the uniform thin film. The maximum tensile strain in the ribbons is approximately &lt; RTI ID = 0.0 &gt;

The width of the buckles is 2L ₁ and the periodicity is 2L ₂ . Since the amplitude h ² π ² / (12L ₁ ² ) is much smaller than _εpre (ie,> 10% in the report) for h <1 μm, the amplitude depends on the mechanical properties of the ribbons , Zero modulus, etc.) and is primarily determined by the layout and pre-strain of the bonding locations. This conclusion implies the general applicability of this approach: ribbons made of any material will be formed with similar buckling geometries. These predictions are consistent with the results obtained for the Si and GaAs ribbons used herein. The calculated profiles plotted in dashed lines in Figure 27 (a) for 33.7% and 56.0% pre-strain are in good agreement with the observations in GaAs ribbons. In addition, the parameters (including periodicity, width and amplitude) of the buckling shown in Figure 27 (a) are consistent with analytical calculations except at low ε _pre (Tables 1 and 2). An interesting result in this study is that the maximum tensile strain is small (eg, ~ 1.2%) for large ε _pre (eg, 56.0%) in ribbons. As discussed further below, this scaling enables tensile potential for breakable materials such as GaAs.

The lithographically defined bonding locations have more complex geometries than simple grid or grid patterns associated with the structures of FIG. For example, buckling with different widths and amplitudes can be formed in the individual ribbons. As an example, FIG. 27 (b) shows a case where W _act = 15 μm and W _in = 350, 300, 250, 250, 300 and 350 μm and 50% pre-warped buckled Si ribbons (width and thickness of 50 μm and 290 nm). The image clearly shows the change in amplitude and width of neighboring buckles in each ribbon. The buckled ribbons may be formed to have different phases relative to the different ribbons. Fig. 27 (c) provides an embodiment of a Si system designed to vary linearly with distance, with the phase of buckling being perpendicular to the lengths of the ribbons. The UVO masks used for these samples have W _act and W _in = 15 and 250 占 퐉, respectively. The angle between the PDMS stamp and the active strips on the Si ribbons is 30 [deg.]. Many other possibilities can easily be achieved since the bonding positions can be lithographically easily controlled, for example part of which is shown in Figs. 13-17.

As shown in Fig. 27 (d),? _Pre = 60%, _Wact = 10 [mu] m and GaAs ribbons buckled on PDMS with different W _in are important aspects for application in tensionable electronic devices. The profiles agree well with the analytical solution according to the mechanics but show cracking due to GaAs cracking at W _in = 100 μm (and smaller). The breakdown is due to a tensile strain (~2.5% in this case) exceeding the yield point (~ 2%) of GaAs. Thus, an optimized configuration for robustness against tension and compression can be achieved by choosing W _in (>> W _act ) proportional to ε _pre . In this situation, up to 100% or greater pre-strain can be accommodated. This type of tensile capability has been demonstrated by applying a force to the PDMS support. The variation of the end-to-end distance of the segments of the ribbons provides means for quantifying tensile and compressibility in accordance with the following equation.

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및

보다 더 작은

에 각각 대응된다. W_act = 10 ㎛, W_in = 400 ㎛ 및 ε_pre = 60%인 PDMS 위의 버클링된 리본들은 60%의 인장 가능성과 30%까지의 압축 가능성을 보여준다. 리본들은 PDMS 내에 내장(embed)됨으로써 상기 구조물들을 기계적으로 보호되고, 또한 연속적이고도 가역적인 반응을 생성해 낼 수 있다. 그러나, 기계적으로는 약간 변화된다. 특히, 상기 인장 가능성과 압축 가능성은 각각 ∼51.4%(도 28a) 및 ∼18.7%(도 28b)로 감소한다. 상기 리본들의 상부 위의 PDMS 매트릭스는 버클링들의 피크들을 약간 편평하게 하는데, 이는 경화로 인하여 그 하부에 놓인 PDMS가 수축함에 부분적으로 기인한다. 큰 압축 변형 하에 있는 이들 영역에서는 작은 주기의 웨이브들이 형성되는데, 앞서 설명한 웨이브진 리본 구조물들을 생성하는 유형의 자발적인 역학에 기인한다. 도 28b에 나타낸 바와 같이 기계적인 결함은 이들 영역에서 시작하는 경향이 있고, 그에 의하여 압축 가능성을 감소시킨다. W_act = 10 ㎛, 및 W_in = 300 ㎛로 버클링된 구조물들은 이런 유형의 거동을 피하였다. 이러한 샘플들은 도 28a에 나타낸 것보다 약간 더 낮은 인장 가능성을 보였지만, 짧은 파장의 웨이브들이 없다는 것이 압축 가능성을 ∼26%까지 증가시켰다. 전체적으로, 패터닝된 표면 화학 접착 위치들을 갖는 사전-인장된 PDMS 기판들 위에 형성된 버클링들을 포함하는 단결정 GaAs 나노리본들은 50%보다 더 큰 인장 가능성과 25%보다 더 큰 압축 가능성을 보여주는데, 이는 100%에 육박하는 실물 크기의 (full scale) 변형 범위에 대응된다. 이러한 수치들은 ε_pre와 W_in을 증가시킴으로써, 또한 PDMS보다 더 높은 신장이 가능한 기판 물질을 이용함으로써 더 개선된다. 더욱 정교한 시스템을 위해서, 이러한 제조 과정들은 버클링된 리본들의 다중층을 갖는 샘플들을 생성하기 위해서 반복될 수 있다(도 29 참조).here,

Represents the maximum / minimum length before fracture,

Represents the length in the relaxed state. Kidney and compression

Larger than

And

Smaller than

Respectively. W _act = 10 [mu] m, W _in = 400 [mu] m and [epsilon _pre] = 60% show tensile potentials of 60% and compressibility up to 30%. Ribbons can be embedded in the PDMS to mechanically protect the structures and produce a continuous and reversible reaction. However, it is slightly changed mechanically. In particular, the tensile and compressibility decreases to ~51.4% (Figure 28a) and ~ 18.7% (Figure 28b), respectively. The PDMS matrix on top of the ribbons makes the peaks of the buckling slightly flat, which is partly due to the shrinkage of the underlying PDMS due to curing. In these regions under large compressive deformation, small periodic waves are formed, which is due to the spontaneous dynamics of the type of generating the wave-tight ribbon structures described above. Mechanical defects tend to start in these areas, as shown in Figure 28B, thereby reducing the possibility of compression. W _act = 10 [mu] m, and W _in = 300 [mu] m avoided this type of behavior. These samples showed slightly lower tensile potential than that shown in Figure 28A, but the absence of short wavelength waves increased the compressibility to ~ 26%. Overall, single crystal GaAs nanoribbons, including buckles formed on pre-stretched PDMS substrates with patterned surface chemical adhesion sites, exhibit a tensile potential of greater than 50% and greater than 25% To a full scale deformation range close to &lt; RTI ID = 0.0 &gt; 0. &lt; / RTI &gt; These values are further improved by increasing &lt; RTI ID = 0.0 &gt;# _{pre &lt; / RTI} &gt; and W _in , as well as by using a substrate material that is capable of higher elongation than PDMS. For a more sophisticated system, these fabrication processes can be repeated to create samples with multiple layers of buckled ribbons (see FIG. 29).

A direct consequence of this high tensile / compressibility potential is a very high level of mechanical bendability. 30 (a) to 30 (c) are optical micrographs of a bent configuration showing such characteristics. The PDMS substrate (thickness ~ 4 mm) is bent into concave (radius ~ 5.7 mm), flat, and convex (radius ~ 6.1 mm) curved surfaces, respectively. The images show how the profiles have changed to accommodate surface deformations caused by bending (~ 20-25% in these cases). In fact, shapes were similar to those obtained at compression (~ 20%) and tension (~ 20%). Embedded systems exhibit a higher level of bendability due to the effects of intermediate mechanical planes. If the upper and lower layers of the PDMS had similar thicknesses, there was no change in buckling shapes during bending (Fig. 30d).

To demonstrate these mechanical properties in working electronic devices, a buckling GaAs ribbon having a profile similar to that shown in Figure 30 was used to form a thin gold electrode for the Schottky contact on the Si-GaAs surface of the ribbons To fabricate a metal semiconductor-metal photodetector. 31 (a) shows an equivalent circuit, and a plane optical microscope photograph, of the geometry of the MSM PD before and after stretching by 50%. When there was no light, there was almost no current flowing through the PD; The current increased as the irradiation amount was increased with an infrared beam (wavelength ~ 850 nm) (Fig. 31 (b)). The asymmetry of the current / voltage (IV) characteristics may be due to differences in the electrical properties of the contacts. 31 (c) (tension) and 31 (d) show the IVs measured at different tension and compression. The current increased until the PD was 44.4% pulled, and then decreased for additional pull. Since the intensity per unit area of the light source is constant, an increase in the current due to the tensile force causes the projected area (referred to as the effective surface area, S _eff ) of the buckled GaAs ribbon as the buckled GaAs ribbon becomes flat Increase in demand. Further tensioning of the PD can cause formation of defects on the surface and / or in the lattice of the GaAs ribbon, which leads to a reduction in current and eventually breaks the circuit open. Similarly, compression reduces S _eff and thus reduces current (FIG. 31 d). These results provide a fully extensible / compressible type optical sensor that is useful for a variety of applications, such as monitors, curved imaging arrays, and other devices, which are embedded within the PDMS matrix and can be worn by buckling GaAs ribbons Lt; / RTI &gt;

Consequently, this embodiment indicates that a soft elastomer having lithographically defined bonding locations is useful as a tool to create a certain class of 3D configurations in semiconductor nanoribbons. Tensionable electronic devices provide an example of many possible application areas of this type of structures. Simple PD devices demonstrate some capabilities.

The ability to separate high-level control of the structure and the high temperature process steps (e.g., the formation of ohmic contacts) from the buckling process and PDMS can be achieved by using more complex devices (e.g., transistors, It is possible. Well-controlled phases of buckling in neighboring ribbons provide an opportunity to electrically interconnect the various elements. In addition, although the experiments reported here used GaAs and Si nanoribbons, other materials (e.g., GaN, InP, and other semiconductors) and other structures (e.g., nanowires, It is compatible with this approach.

GaAs Ribbons: GaAs with customer-designed epitaxial layers were purchased from IQE Inc. of Bethlehem, PA. The GaAs ribbons were produced through photolithography and wet chemical etching. AZ photoresist (e.g., AZ 5214) was spin cast on the GaAs wafer at a rate of 5000 rpm for 30 seconds and then soft baked at 100 ° C for 1 minute. Exposure through a photomask with patterned lines oriented along the (0 1 1) crystallographic direction of GaAs and subsequent development produced line patterns within the photoresist. The photoresist residues were removed by mild O2 plasma (i.e., a descum process). The GaAs wafers were then anisotropically etched for 1 minute in an etchant (4 mL H ₃ PO ₄ (85 wt%), 52 mL H ₂ O ₂ (30 wt%), and 48 mL deionized water) It was cooled in an ice bath. AlAs layers was diluted in ethanol was dissolved in dichloromethane (21 vol diluted) HF solution (Fisher Chemicals ^®). The samples with released ribbons on a mother wafer were dried in a fume hood. The dried samples were coated with 30 nm SiO ₂ deposited by electron beam evaporation.

Silicon ribbons were prepared from silicon-on-insulator (SOI) wafers (Soitech, Inc., upper silicon 290 nm, buried oxide 400 nm, p-type). The wafer is patterned by conventional photolithography using AZ 5214 photoresist and etched with SF6 plasma (PlasmaTherm RIE, SF6 40 sccm, 50 mTorr, 100 W). After cleaning the photoresist with acetone, the buried oxide layer is etched with HF (49%).

Preparation of UVO masks: Fused quartz slides are cleaned in a piranha solution (at 60 ° C) for 15 minutes and thoroughly rinsed with sufficient water. The cleaned slides are blown dry with nitrogen and placed in a chamber of an electron beam evaporator to be sequentially coated with 5-nm Ti (as an adhesive layer) and 100-nm Au layers (as a mask layer for light-guiding). On this slide a negative photoresist, SU8 5, is spin cast at a speed of 3000 rpm for 30 seconds to yield a film of ~ 5 탆 thick. Soft bake, exposure to UV light, post bake, and development create patterns within the photoresist. A mild O2 plasma (i.e., a descum process) removes photoresist residues. The photoresist serves as a mask for etching Au and Ti using a gold etchant (i.e., an aqueous solution of I2 and KI) and a titanium etchant (i.e., a dilute solution of HCl).

PDMS stamps were prepared by pouring a prepolymer (A: B = 1: 10, Sylgard 184, Dow Corning) into a Petri dish followed by baking at 65 ° C for 4 hours Respectively. The resulting slabs of appropriate thickness and square shape were cut out of the cured pieces, rinsed with isopropyl alcohol, and blown dry. A specially designed stage was used to mechanically stretch the PDMS to the desired level of deformation. Through a short wavelength UV light UVO mask in contact positioned to (a low-pressure mercury lamp, BHK, 240 to 260 nm 173 μW / cm ²⁾ and the PDMS to the tension the substrates was irradiated for 5 minutes, the surface chemistry are patterned .

Formation and Embedding of Buckled GaAs Ribbons: GaAs wafers with SiO2-coated disbonded ribbons were laminated onto a stretched PDMS with patterned surface chemistry. Baked in an oven at 90 deg. C for 5 minutes, cooled to room temperature in air, and then slowly relaxed in the PDMS to form buckles along each ribbon. Embedding the buckled ribbons involves massive exposure of the UV light for 5 minutes followed by casting the liquid PDMS prepolymer to a thickness of ~ 4 mm. The sample was cured in an oven at 65 占 폚 for 4 hours or at room temperature for 36 hours to cure the prepolymer to obtain buckled ribbons embedded within the solid matrix of PDMS.

Characterization of buckled ribbons: The ribbons were imaged with an optical microscope with the sample tilted by ~ 90 ° (for unembedded samples) or ~ 30 ° (for embedded samples). The SEM images were recorded on a Philips XL30 field-emission scanning electron microscope after the samples were coated with a thin film of gold (~5 nm thick). To stretch and compress the resulting samples, the same stage was used as was used to pre-tension the PDMS stamps.

Manufacturing and Characterization of SMS PDs: The fabrication of the PDs started with a sample of the configuration shown in the bottom frame of Figure 24, b.

 A band of ~0.8 mm wide poly (ethylene terephthalate) (PET) sheet was placed slowly over the PDMS with its longitudinal axis perpendicular to the longitudinal axes of the ribbons. The SMS PD formed from the buckled GaAs ribbons by removing the PET strip and relaxing the pre-stretched PDMS stamp. [0064] The liquid PDMS prepolymer was cast onto the areas of the ribbon free of electrodes and then cured in an oven. The gold electrodes were extended beyond the upper PDMS (Agilent 4155C) so that the semiconductor parameter analyzer could irradiate. For the measurement of the photoreaction, the PDs were manipulated using a mechanical stage for tension and compression. IR (with a wavelength of 850 nm) IR The LED source provided illumination light.

Example 2: Transfer printing:

Our technical approach utilizes certain ideas embodied in printing methods based on the flat stamps described above. While these basic techniques provide a promising starting point, many fundamentally new features have to be introduced as described below in order to meet the challenges of the HARDI (Hemispherical Array Detector for Imaging) system.

32 and 33 illustrate a general strategy associated with transfer printing onto curved surfaces. The first set of steps (FIG. 32) is to create a thin, spherical curved surface, which is designed to lift the interconnected Si CMOS 'chiplets' off the planar surface of the wafer and then convert the geometry into a hemispherical shape. Involves the production and manipulation of an elastomeric stamp. The stamp for this process includes casting and curing the liquid prepolymer and depositing poly (dimethylsiloxane) (PDMS) onto the selected high quality optical elements (i. E., Matched pairs of convex and concave lenses) ). &Lt; / RTI &gt; The stamp has a molded circular rim. Pairing the molded groove (the dotted circle in FIG. 32) on this rim with the rigid circular retaining ring of the appropriate size to tension the element in the radial direction transforms the rectangular stamp into a stretched, flat sheet . Contacting the tensile stamp with a mother wafer supporting preformed and undercut etched, Si CMOS 'chipsets' with thin interconnections, and then stripping the stamps is done with these interconnected 'chipsets' Ink the element. The van der Waals interaction between the chippings and the soft elastomeric element provides sufficient adhesion for this process.

Removing the retaining ring results in the PDMS being relaxed and returning to its original hemispherical shape, thereby achieving the conversion of the chitlet array from planar to spherical. This conversion causes a compressive strain on the surface of the stamp. These variations are accommodated in the CMOS chip array by local delamination and lift-up of the interconnect (left bottom of FIG. 32). These 'pop-up' interconnects absorb deformation in such a way as to avoid damage to the chips or harmful changes induced by their deformation in their electrical properties. These two goals are achieved if the strain in the chippets is kept below -0.1%. The space required for the interconnects limits the maximum fill factor of the CMOS chips. However, photodetectors consume almost total pixel areas, thereby providing a direct path to an 80% fill factor target.

In the second set of steps (FIG. 33), the 'inked' hemispherical stamp is used to transfer the elements onto a final device substrate having a cavity of a matching type (see, for example, A glass substrate having a matching hemispherical cavity). This transfer process uses an ultraviolet (UV) curable photopolymer such as photocurable BCB (Dow Chemical) or polyurethane (Norland Optical Adhesive) as an adhesive. These materials are applied to the device substrate in the form of a thin (tens of microns thick) liquid film. With contact with the stamp, the liquid layer flows to match the relief structures associated with the chippings and pop-up interconnections. UV light through the transparent substrate cures the photopolymer and converts it to a solid form resulting in a smoothed, planarized top surface with removal of the stamp. The final integration to form a functional system involves deposition and patterning of electrodes and photodetector materials, and lithographic definition of bus lines to external control circuits.

The approaches of Figures 32 and 33 have several notable features. First, it utilizes state-of-the-art flat-panel electronics technology to enable reliable, cost-effective, high-performance operation on a hemispherical substrate. In particular, the chips consist of a set of silicon transistors processed with a 0.13 탆 design rule, resulting in local, pixel-level processing capabilities for the HARDI system. Conventional processes are used for SOI wafers to form these devices. The buried oxide provides a sacrificial layer (undercut etching with HF) to produce the chips to be printed. The interconnects consist of narrow and thin (~ 100 nm) metal lines.

A second feature is that the approach utilizes mechanical designs and elastomeric elements to enable a well controlled transition from planar to hemispherical. This control is then achieved with reversible, linear dynamics within the transcription stamps and comprehensive mechanical modeling, as outlined below. A third attractive aspect is that strategies for controlling adhesion and some basic configuration of the transfer process are documented in flat applications. In fact, the stages designed for planar printing applications can be modified for the process of Figures 32 and 33. [ Figure 34 shows a home-built printer with a visualization system integrated with a pneumatic actuator suitable for use in the present process.

These types of printer systems are used to demonstrate various aspects of the processes of Figures 32 and 33. Figure 35 shows images of a scanning electron microscope of the surface of an inked hemispherical stamp with an array of monocrystalline silicon islands interconnected with heavily doped silicon ribbons and square arrays. Figure 36 shows optical images. During the transition from planar to spherical, these ribbon interconnections popped up in the manner depicted in FIG. The key aspect of these types of interconnects reduces the need for direct processing on high resolution, curvilinear lithography or other types of hemispheres when combined with transfer of fully formed chips.

Fully computational modeling of the elastic mechanical response of the interaction with the hemispherical stamps, pop-up interconnects, and rigid device islands as well as material and general process strategies is performed. These calculations reveal the physics of the process at a level that facilitates engineering control and optimization. Simple estimates based on the linear elastic plate theory suggest that a level of deformation associated with the processes of Figure 32 can result in a 2-mm thick stamp and 10% or more of a spherical surface with a radius of 1 cm . Thus, for reliable engineering control, the stamp needs to be operated within a linear elastic range for deformation of up to twice this value, i. E., ~ 20%. Figure 37 shows the experimental stress / strain curves of several different PDMSs that we have experience at the level of bulk, planar stamp based printing. 184-PDMS appears to provide excellent starting materials because it provides a highly linear and elastic response up to ~ 40% strain.

These mechanical measurements, combined with the literature values of the ribbon pop-up interconnections and the chippings of the moduli and geometry, provide the information necessary for modeling. Two approaches to calculation are adopted. First, full-scale finite element modeling (FEM) is used to describe the details of geometry (eg, size, spacing, multi-layers) of devices and interconnects on a planar substrate. do. Different materials (e.g., stamps, silicon, interconnects) are described directly in the analysis. Lateral pressure is applied to deform the stamp and circuits over the desired hemispherical shape. The finite element analysis provides a strain distribution, and in particular provides maximum strain in devices and interconnects and non-uniform spacing between switched devices. The advantage of such an approach is that it can be used to capture both the geometry of the device and the details of the material, and thus to investigate the effects of other designs of the transfer printing process to reduce maximum deformation and non-uniformity. However, this approach is computationally complex, and thus time consuming, because of the extensive length scales and tens of thousands on the stamps involved in the modeling of the structure devices.

The second approach is a unit-cell model for devices (chipsets), analyzing their mechanical performance with loads. Each device can be represented by a unit cell, and its response to mechanical loads (e.g., bending and tension) is thoroughly studied through a finite element method. Each device is then replaced by unit cells connected by interconnects. This unit cell model is then incorporated into the finite element analysis to replace the detailed modeling of the devices and interconnects. Also, the farther from the edge of the sphere, the more uniform the unit-cells are and the variations are relatively uniform so that their performance can be represented by a coarse-level model. Near the edge of the sphere, the deformation is very uneven so that detailed modeling of the devices continues to be required. The advantage of such an approach is that it significantly reduces the computational effort. The full-scale finite element analysis in the first approach is used to identify this unit-cell model. Once identified, the unit-cell model provides a robust design tool because it is well suited to quickly investigate the design of different devices, interconnects and their intervals.

FIG. 38 shows a preliminary FEM result for stretching the hemispherical stamp into a planar geometry (and returning to its hemispherical shape relaxed) as outlined in FIG. The upper frame shows a cross-sectional view of a hemispherical stamp having a geometry as conceptually shown in Fig. These results show some spatial nonuniformity in the deformation of the stretched film, as evidenced by its non-uniform thickness. Treating the thickness profiles of the stamps through an appropriate selection of the structure in which the stamps are cast and cured can eliminate such non-uniformities. However, some non-uniform variations are acceptable because (i) the pop-up connections are inherently resistant to distortion, and (ii) the chips do not need to be perfectly centered at each pixel location: Will fill the pixel regions with a uniform back electrode that can make electrical contact with the chippers regardless of their location within the pixel region.

The modeling may determine the level of deformation in the Si CMOS chips. The systems should be designed such that the deformation of these chitets adheres to less than 0.1-0.2% in order to somehow avoid changes in electrical properties and mechanical failures due to breakage or delamination. This modeling facilitates the design of process conditions to avoid exposure of the chippings to stamps and deformation beyond this range.

Example 3: Biaxially stretchable "waved" silicon nanofibers

This embodiment introduces single crystal silicon in a biaxially stretchable form. The monocrystalline silicon consists of two dimensionally buckled or "waved" silicon nanomaterials on an elastomeric support. Manufacturing methods for these structures are described and various aspects of their geometry and responses to uniaxial and biaxial deformations according to various directions are provided. Mechanical interpretive models of these systems provide a framework for quantitatively understanding their behavior. These classes of materials provide a path to high-performance electronics with full, two-dimensional tensile potential.

Electronic devices that provide mechanical bendability are of interest in applications in information displays, x-ray imaging, photovoltaic devices, and other systems. The reversible stretchability is a much more technically challenging mechanical property that would allow different device possibilities to be realized that are different, but are not achievable with bendable electronic devices such as smart surgical gloves, electronic eye cameras, and personal health monitors . One approach to this type of electronic device is to interconnect the rigid device islands with tensionable wires to provide circuit level of tension to non-tensionable device components. In alternative strategies, certain structural forms of thin single crystal semiconductors and other electronic device materials enable tensile potential within the device itself. (Uniaxial) tensile properties in metal oxide semiconductor field effect transistors (MOSFETs), metal semiconductor field effect transistors (MESFETs), pn junction diodes, and Schottky diodes. Recent demonstrations have involved the use of buckled, one-dimensional "waved" geometries in silicon and gallium arsenide nanoribbons (thickness in the tens to hundreds of nanometers and micrometer range width) do. This example shows that nanofilms of similar materials can be formed into two-dimensional (2D) wavy geometries to provide full 2D stretchability. The manufacturing methods of such systems are described with detailed experimental characterization and analytical modeling of their mechanical response.

39 conceptually illustrates steps for forming a Si nanomaterial that is two-dimensionally stretchable on an elastomeric support. In this embodiment, the films are fabricated from SOI wafers (Soitec, Inc., p-type). The fabrication of these films is accomplished by defining an appropriate pattern of photoresist by photolithography and then removing the exposed silicon by reactive ion etching (PlasmaTherm RIE, SF ₆ 40 sccm, 50 mTorr, 100 W) (~ 2.5 [mu] m diameter, ~ 25 [mu] m pitch). This same step defines the overall lateral dimension of the film, which is in the range of 3-5 mm squares for the samples reported here. The thickness is between 55 and 320 nm. The etched samples were immersed in concentrated hydrofluoric acid (HF 49%) to remove the buried SiO ₂ layer (145-1000 nm thick); The photoresist was removed by washing in acetone. Polished silicon wafers were cast and cured with prepolymers of poly (dimethylsiloxane) (PDMS) to produce a flat elastomeric substrate (~4 mm thick). The hydrophobic PDMS surfaces (-CH ₃ and -H termini) were exposed to the hydrophilic state (-OH and -O-Si-O termini) by exposing them to the ozone environment generated by intense ultraviolet light (240-260 nm) ). The PDMS substrate thus activated was simply heated at 70-180 ° C. in a convection oven to induce isotropically thermal expansion to a controlled extent. This element was contacted with the treated SOI wafer and then stripped off again, so that the entire nanofiber was transferred to the PDMS. Continued heating for several minutes in a convection oven facilitated the formation of strong adhesive bonds between the membrane and the PDMS. In the final step, the nanofiber / PDMS structure was cooled to room temperature (ca. 25 占 폚) to release the thermally induced pre-strain (? L / L). This process led to the spontaneous formation of two-dimensional (2D) wave-like bony structures near the surface areas of Si nanofoam and PDMS. These structures exhibit different behaviors near the edge where the one-dimensional periodic wave predominates, the inner regions where the two-dimensional herringbone layout is typically observed, and the central vicinity where the disordered herringbone structures often arise. The herringbone region is defined by the distance between neighboring peaks in the waves, the amplitude A ₁ (not shown in FIG. 1) of the wave, the "jog" neighboring within the herringbone structure, , And is characterized by the longer distance 2π / k ₂ (along the x2 direction) which we call the long wavelength. The other characterization length is a "jog" wavelength 2π / k ₁ (along the x1 direction perpendicular to the long wavelength direction x2 direction), the amplitude A ₂ of the jog, and the angle θ of the jog. The lower frames of Figure 39 conceptually illustrate these characteristics.

Parts a to f of Figure 40 show that for the case of a thermal pre-strain of ~ 3.8% (as defined by heating to 150 ° C) and a nanomembrane with a 100 nm thickness (lateral dimension ca 4 x 4 mm ² ) We show optical microscope photographs collected at different stages during the formation of herringbone waves. These images indicate that the structure is formed in two stages, the first of which involves a significant one-dimensional wave over a large area, and then bending these wave structures, which ultimately leads to a compact herringbone layout (D to f in FIG. 40). FIG. 40 h shows a time evolution of two characteristic wavelengths. Due to the relatively large thermal shrinkage of the PDMS, the short wavelength tends to decrease as the cooling progressively leads to a larger compressive strain on the silicon. In particular, this value decreases from ~ 17-18 urn in the initial stage to ~ 14.7 ㎛ when the herringbone structure becomes prominent, and finally to ~ 12.7 urn in the fully cooled state. This wavelength is uniform over a large area (~ 5% variation). In contrast, the long wavelength associated with the herringbone layout shows a wide range of values, which is apparent from the image shown in Figure 40, g. The results of the measurement at ~ 100 points over this sample showed the value of the distribution summarized by the histogram in Figure 40 (g). The herringbone structure can be represented by an out-of-plane displacement of w = Alcos [k1x1 + k1A2cos (k2x2)] (Fig. 49). Here, the coefficients, the amplitude A ₁ , the long wavelength 2? / K ₂ , the jog wavelength 2? / K ₁ , and the jog amplitude A ₂ of the wave are determined by analyzing the thickness of the specific film, the mechanical properties of the film and the substrate. The short wavelength? Is (2? / K ₁ ) sin (? / 2). The modeling is used (Fig. 50) because the Si strain is determined from the measured contour lengths and the periods of the waved structures instead of the thermal pre-strain as the applied pre-strain. The actual strain to deform Si is usually slightly less than the estimated thermal pre-strain.

This may be due to the loading effect of Si on the PDMS. The Si strain is, for example, 2.4% in a thermal pre-strain of 3.8%. For such a displacement w, the fields of stress, strain, and displacement of the Si film can be obtained from terms of A ₁ , k ₁ , A ₂ and k ₂ from Von Karman flat plate theory. The fields in the PDMS substrate can be obtained from the 3D elasticity theory. A ₁ , k ₁ , A _2, and k ₂ are obtained by minimizing the total energy of the film energy and bending energy in the Si film and the elastic energy in the PDMS substrate. The Young's Modulus and Poisson ratios of Si and PDMS are E _Si = 130 GPa, v _Si = 0.27, E _PDMS = 1.8 MPa, and v _PDMS = 0.5. Both the experiment and the model obtained a jog angle θ of about 90 °. The short wavelength given by the above theory is 12.4 ㎛ in the 2.4% pre-twist pre-strain, which agrees well with the above experimental results. The large fluctuation of the long wavelength 2? / K ₂ was expected to be 30 to 60 占 퐉 by the theoretical calculation.

FIG. 41 shows images of an atomic force microscope (AFM) and a scanning electron microscope (SEM) of structures similar to those shown in the fully cooled state of FIG. These images clearly show that the herringbone patterns are characterized by a zig-zag structure that defines two characteristic directions, even if the compression deformation is completely isotropic. Herringbone structures exhibit a minimum elastic energy configuration that reduces in-plane stresses in the system and alleviates biaxial compression in both directions. Thus, this geometry is preferred over a large area as compared to 1D wave layout and "checkerboard". Because the herringbone mode is the only mode among these three modes that can mitigate in-plane stress in all directions without causing significant tensile energy. Significant stretching is induced only in the vicinity of the jaws. The 1D mode lowers the prestress in only one direction. The checkerboard mode lowers the stress in all directions but produces significant tensile energy associated with bending.

The two line-cuts extracted from the AFM images, although approximately sinusoidal only, exhibit periodic angular profiles that follow the jog direction (profile (i)) and perpendicular to the wave (profile (ii)). The lambda and A ₁ of the waves can be determined from the profile (ii) and are 12.8 and 0.66 μm, respectively. The lambda given by the theoretical interpretation is 12.4 μm and is similar to the experimental data; However, the A1 obtained by the theoretical analysis is 0.90 탆, which is slightly higher than the experimental result. The SEM images clearly show the close bond between the membrane and the PDMS, as evidenced by the behavior of the sample in the vicinity of the small hole in the silicon in both the raised and recessed portions of the waves. Since the size of the hole, 2.5 탆, is much smaller than the characteristic wavelength of the deformation mode of the present experiment, these images indicate that the wave structures are completely independent of the position of these holes. Studies on the dependence of the geometry of the waveguided structures on the silicon thickness can provide additional insight into the physical phenomena and further validate the mechanical model. Figure 42 shows some results, including the wavelengths and amplitudes of wave structures formed in the film at different thicknesses for thermal deformation similar to optical microscope photographs. For 100 nm thickness, the lambda and A ₁ of the wave are 12.6 (± 0.37) and 0.64 (± 0.07) μm, respectively, and for 320 nm thickness they are 45.1 (± 1.06) and 1.95 (± 0.18) μm, respectively. These values agree well with the theoretical calculations that λ and A ₁ are 12.4 and 0.90 μm for λ and A ₁ and 45.1 and 3.29 μm for 320 nm cases, respectively, for the case of 100 nm.

In contrast to the one-dimensional stretch potential provided by the ribbon geometry described above, these waved films provide true stretchability for deformation in a variety of in-plane directions. To investigate this aspect, uniaxial tensile tests were performed along different directions using a graduated mechanical stage and a 2D tensile film prepared with 3.8% thermally induced pre-strain. Figure 43 provides some images. In case (i), the tensile strain applied along the direction of long wave (ε _st) is "unfolded that _{(unfold)" (ε st)} 1.8%) resulting in a herringbone structure and gradually a fully tensioned state of (ε _st) 3.8%) leading to 1D wave geometry. This tension, due to the Poisson effect, results in a compressive strain in the vertical direction with approximately the same amplitude as half the tensile strain. This compressive strain can be accommodated by compression of the wave-like structures in this direction. With the release of the applied tensile strain, the original herringbone wave was restored and showed a structure almost similar to the original. (FIG. 51 shows optical microscope photographs collected after 5, 10 and 15 times of the tensile cycle).

In full stretching, although the 1D wave structures are aligned along the direction determined by the applied deformation rather than the initial geometry, the tensile strains applied in diagonal directions (case ii ) Showed similar structural changes. For vertical case iii, at small strains (ε _st 1.8%), a certain percentage of the sample completely loses the herringbone layout to create new 1D waves along the stretching direction. With increasing tension, more regions are so deformed until the entire area is composed of 1D waves oriented in this way. The newly formed 1D waves are perpendicular to the orientation of the initial waves; Once released, they are simply bent to create a disordered herringbone-like geometry. For all of the cases shown in FIG. 43B, even if the compressive stresses are induced in the orthogonal direction by the Poisson effect, the wavelength increases with the tensile strain and recovers to its initial value upon release. This behavior is due to an increase in lambda induced by the unfolding of the herringbone waves, which is greater than the decrease in such wavelength caused by the Poisson effect. (Fig. 52) For the case i, by the Poisson's effect, is a tensile strain, under ε _st, for example, k ₁ '> If the k _1, the jog switch wavelength, 2π / k ₁ (FIG. 52A) is 2π / k ₁ (Fig. 52B). However, the corresponding jog angle? 'Is larger than the angle? By the spreading of the herringbone structure. The short wavelength λ = (2π / k ₁ ) sin (θ / 2) becomes λ '= (2π / k ₁ ') sin (θ '/ 2) lt; / RTI &gt; Our theoretical models are λ = 12.4, 14.6, and 17.2 μm for ε _st = 0, 1.8, and 3.8%, and as observed in the experiment, this confirms that the shorter wavelength increases with the applied tensile. In case iii, both λ and 2π / k ₁ increased with an applied stretching tension because the waves were relaxed along the direction of the stretching tension and the Jogg angle θ was remarkably increased by the Poisson effect It is because it has not changed. The biaxial tensile potential of buckling membranes was also investigated by thermally induced tensile strains (Figure 53). Herringbone waves generated by thermal stretching slowly disappeared as the sample was heated; They were completely restored upon cooling.

Only the central part of the membranes were observed in this manner. As indicated in the lower frame of Figure 39, the edges of the films represent 1D wave structures with the wave vectors oriented along the edges. AFM images and line-cut profiles of the edge region, the center region, and the transition region between them are shown in FIG. 1D waves starting near the edge of the Si (upper frame) are gradually bent (intermediate frame) and transformed from central regions to herringbone geometries (lower frame). The lambda values of these regions are 16.6, 13.7, and 12.7 μm, with A ₁ of 0.52, 0.55, and 0.67 μm, respectively (from the top frame). Assuming that the inner region of Si is more affected by compression strain than the edges, as compared to 1D waves at the edges, the 2D herringbone waves have smaller λ and A ₁ . The stress state near the edge is approximately uniaxial compression within a predetermined distance range due to the traction-free edge of the film. This uniaxial compression is parallel to this free edge, thus causing the 1D waves to follow the edge. However, the stress state is equi-biaxial compressive at the center of the herringbone structures. In the transient region between the 1D wavefront edge and the herringbone waves, unstable biaxial compression causes a &quot; semi &quot; -herinbone wave with a large jog angle. In our model, λ and A ₁ in the wave 1D each are 16.9 and 0.83 μm, respectively, λ ₁ and A in a herringbone structure is 12.4 and 0.90 μm, respectively. These results are in good agreement with the experimental observations.

To further investigate these edge effects, we fabricated a rectangular film with widths of 100, 200, 500, and 1000 μm and 1000 μm on the same PDMS substrate. Figure 45 shows optical micrographs of these structures for two different levels of thermal prestrain. In the low thermal pre-strain (case 2.3%, Figure 45A), films with widths of 100 and 200 μm exhibit perfect 1D waves from one side to the other, with flat, unmodified portions at the ends. The film with a width of 500 μm represents similar 1D waves and flat areas, but the waves have a slightly curved geometry at the center of the structures and the orientation uniformity and overall arrangement is substantially lower than the case of 100 and 200 μm . In the case of a 1000 μm square film, 1D waves appear in the central parts of the edges and flat areas appear in the corners. The middle part of the membrane represents fully grown herringbone geometries. The flat area of the corner is roughly stress-free due to the two free edges. No waves are formed near these corners. Increasing the pre-strain (4.8%, Figure 45B) decreases the size of the flat areas in all cases. 1D wave properties persist in 100 and 200 μm ribbons, but noticeable herringbone morphologies appear in the center of the 500 μm case. In higher pre-strains, equivalent-biaxial compression stretches appear in the middle region of the membrane with a width of 500 [mu] m. For a 1000 μm square film, the herringbone nature extends to areas close to the edges. Characteristic length scales that define the spatial extent of flat regions are referred to as _edge lengths (L _edges ) and can be obtained as a function of film size and pre-strain. Figure 45C shows the results of linear scaling of this length for pre-strain, in a manner independent of the size of the film, for the cases investigated here. The larger the pre-strain, the smaller the length of the uniaxially stretched region. Thus, a shorter range of 1D waves is formed and similar properties can be observed in the stress-free regions near the two free edges.

Figure 46 shows optical micrographs of the wavy structures formed with different membrane geometries including circular, elliptical, hexagonal, and triangular. The results are qualitatively consistent with the observations in the rectangles and ribbons of FIG. In particular, the edge regions represent 1D waves oriented parallel to the edges. Waves with orthogonal directions appear only at distances greater than L _edge at the _edges . In the case of a circle, 1D waves appear near the edges and have a generally azimuthal direction due to the shape of the film. Herringbone waves appear in the center. The elliptical shape exhibits similar properties, but has flat portions of the major axis edges, which is due to the small radius of curvature of these regions. For hexagonal and triangular shapes, angled corners (angles of 120 ° and 60 °, respectively) result in flat areas. Herringbone geometries appear at the center of the hexagon. The center of the triangle represents the merging of the 1D waves at the level of the pre-distortion presented herein. In the case of models with distinct corners (eg hexagonal, triangular and elliptical ends), there are no waves near the corners, and the two intersecting free edges (not necessarily vertical) give a stress-free state. In the case of triangles, even in the middle region, there is not enough space to generate the herringbone structure.

The films themselves provide a path to biaxially stretchable electronic devices. The edge effects described above can be exploited to achieve a particular result that may be useful for a particular kind of such devices. In particular, in an imaging system, it may be valuable to maintain flat, unmodified areas at the locations of the photodetectors to avoid non-ideal properties that occur when these devices have a wavy form. Figure 47 shows representative examples of some of the stretchable membranes achieving this performance. Such a structure is formed by ribbons of 30 μm × 150 μm (30 μm × 210 μm for orthogonal ribbons) in the vertical and horizontal directions (FIGS. 47A, C) and in the vertical, horizontal and diagonal directions It consists of 100 x 100 μm square islands connected. The change in amplitude and wavelength of the waves of the ribbons provides a means to accommodate the applied tensile in a manner that significantly avoids deformation in the square island portions. We have investigated the nature of these structures in several differently validated stretches. 47 (a) and (e) illustrate representative cases in a low tensile (case 2.3%) regime applied by heating the samples in an oven. 47C and 47G show the same structures at relatively high biaxial tensile (case 15%) applied using a mechanical stage. Obviously, in the low-tensile type, the islands remain flat; At sufficiently high stretches, wave structures begin to form at these sites. Good adhesion between PDMS and SI was maintained at all tensile, as can be seen in inclined SEM images (Figures 47B, D, F, H). The high magnification SEM image inserted in Figures 47 (b) and (d) also confirms a strong coupling between SI and PDMS.

In summary, the nanofibers of silicon can be integrated into pre-strained elastomeric substrates to create 2D &quot; waveguide &quot; structures with a range of geometries. Many aspects of the mechanical properties of these systems are in good agreement with the theoretical predicted properties. These results are useful for applying to electronic devices in systems that require full tensile potential during use or installation.

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Example 4: A heterogeneous three-dimensional electronic device by the use of printed semiconductor nanomaterials

We have developed a simple approach to combine large classes of non-similar materials into heterogeneously integrated (HGI) electronic systems with two- or three-dimensional (3D) layouts. The process begins with the synthesis of different semiconductor nanomaterials on separate substrates (eg single-walled carbon nanotubes and single-crystal nanowires / ribbons of gallium nitride, silicon and gallium arsenide). The repeated application of an additional, transfer printing process that uses these substrates as soft stamps and donors, followed by device and wiring formation, can be accomplished using these (or other) semiconductors on a rigid or flexible device substrate Performance 3D-HGI electronics including any combination of nanomaterials. This versatile methodology can produce a wide range of unconventional electronic device systems that are difficult or impossible to obtain using other technologies.

Many existing and emerging electronic devices benefit from monolithic, heterojunction (HGI) semiconductors in a two-dimensional or three-dimensional layout into a single system. Embodiments include a multi-function radio frequency communication device, an infrared (IR) imaging camera, an addressable sensor array, and a hybrid CMOS / nanowire / nano device circuit 3-7. In some representative systems, compound semiconductors or other materials often provide high-speed operation, efficient photodetection or sensing capability in circuits that include stacked 3D forms, while silicon CMOS provides digital readout readout and signal processing. Wafer bonding 8 and epitaxial growth 9,10 illustrate the two most widely used methods for obtaining this type of 3D-HGI systems. The former process involves physical coupling of integrated circuits, photodiodes or sensors formed separately on different semiconductor wafers by the use of a junction or thermally initiated chemistry. This approach works well in many cases, but has significant drawbacks, including the following: (i) limiting the ability to expand into larger regions or more than several layers of a three-dimensional (i.e., laminate), (ii) materials that are unconventional (e.g., nanostructured materials) (Iii) challenging fabrication and alignment for through-wafer electrical wiring, (iv) requirements for flat, planar bonding surfaces, and (v) other thermal expansion of heterogeneous materials / Bowing or cracking that can result from mechanical stresses caused by shrinkage. Epitaxial growth provides another approach that involves directly forming a thin layer of semiconductor material on the surface of a wafer of another material by molecular beam epitaxy or other means. Although this method avoids some of the aforementioned problems, the requirements for epitaxy place severe limitations on the quality or type of materials that can be grown even if buffer layers and other advanced techniques are used. On the other hand, emerging class of semiconductor nanomaterials such as nanoscale wires, ribbons, membranes, particles of inorganic materials or carbon-based systems such as single-walled carbon nanotubes (SWNTs) or graphene sheets -14) &lt; / RTI &gt; epitaxial growth or wafer bonding, and then dispersed in a solvent or transferred onto a substrate. Recent work, for example, shows the integration of crossed nanowire diodes formed by solution casting in a 2D layout (15). The results presented here demonstrate how single crystal inorganic semiconductors (eg, GaN, Si, and GaAs) that are dissimilar to each other using a scalable and deterministic printing method can be used to create complex HGI electronic systems in a 2D or 3D layout Nanowires / ribbons) can also be combined with other classes of nanomaterials (eg, SWNTs). In particular, high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs) of ultra-thin multi-layer stacks integrated with rigid inorganic materials and flexible plastic substrates, device arrays, logic gates and actively addressable photodetectors, - Semiconductor field-effect transistors (MESFETs), thin-film transistors (TFTs), photodiodes and other elements demonstrate some of the capabilities.

Figure 57 illustrates exemplary steps for creating such 3D-HGI systems. The process begins with the synthesis of semiconductor nanomaterials on their respective source substrates. The devices presented herein are based on single crystal Si, GaN and GaAs nanowires and nanoribbons (16-21) formed using the source materials of the wafer substrate and photolithography process, and SWNT networks grown by chemical vapor deposition (13, 21). At the top of Figure 57, the scanning electron micrograph shows these semiconductor nanomaterials after they have been removed from the source substrates. For circuit fabrication, these elements remain in the form defined on the wafer during the fabrication or growth phase: Si, GaN and GaAs nanowires / aligned arrangements in the case of ribbons and sub-monolayer random networks in the case of SWNTs. A high temperature doping and annealing process for ohmic contact to Si, GaN and GaAs can be performed on the source substrate. The next step is to transfer these processed elements from a source substrate to a device substrate, such as a polyimide (PI) sheet, as shown in Figure 57, using the elastomeric stamp- . In particular, laminating a stamp of polydimethylsiloxane (PDMS) to the source substrate results in weak anti-adhesive adhesion to the semiconductor nanomaterial elements. Contacting an 'ink' stamp over an element substrate having a thin, spin-cast layer of a liquid prepolymer (eg, polyamic acid) on its surface, and then curing the polymer, So that these semiconductor materials are embedded and well adhered onto this layer (16-20). Similar processes work well with a series of substrates (i.e., rigid or flexible; organic or inorganic) and semiconductor nanomaterials (a slightly modified form of this process is used for SWNTs 21). The thickness of the intermediate layer (in this case PI) may be as small as 500 nm for the systems described herein, typically 1-1.5 占 퐉. After several additional processes involving the formation of gate dielectric layers, electrodes and interconnects, the transfer printing and device fabrication steps may be repeated, beginning with spin-coating a new prepolymer intermediate layer on top of the previously completed circuit level. Automated stages or general mask aligners designed specifically for transfer printing enable an overlay limiting accuracy of ~ 1 [mu] m for a few square centimeters (Fig. 61). The layer-to-layer interconnects 23 are simply formed by depositing metal lines on and in the openings in the interlayers defined by photo patterning and / or dry etching. This unconventional approach to 3D-HGI electronic devices has several important features. First, all processes on the device substrate occur at low temperatures, thereby avoiding differential thermal expansion / contraction effects that can result in unwanted deformation in a multi-layer laminate system. This action also allows the use of low temperature plastic substrates and interlayer materials, which helps to ensure that the underlying circuit layers are not thermally degraded by the process of the upper elements. Second, this method is applicable to a broad class of semiconductor nanomaterials including emerging materials such as SWMT films. Third, the soft stamp enables non-destructive contact with underlying element layers; These stamps can deal with surfaces with some topography along with ultra-thin semiconductor materials. Fourth, the ultrathin element topography (<1 μm) and the interlayer (<1.5 μm) facilitate the formation of layers for lamination to electrical interconnects. These features overcome many of the shortcomings of conventional approaches and are illustrated in some of the circuit descriptions that are described below.

FIG. 58 shows a cross-sectional view of a plasma enhanced chemical vapor deposited SiO 2 dielectric film (formed over a source substrate) doped contact, a Cr / Au metallization process for source, drain, and gate using monocrystalline silicon nanoribbons, Three layer stacked Si MOSFETs fabricated using a schematic process are presented. Each device has three aligned nanoribbons having width, thickness and length of 87 [mu] m, 290 nm and 250 [mu] m, respectively. 2A shows a top view optical photograph of an edge of a system having a layout designed to uncover portions of a substrate supporting one, two, and three layers of MOSFETs. The 90 degree rotation of the element geometry for the second layer relative to the first and third layers helps to clarify the layout of the system. Figure 58b shows a schematic cross-sectional view and a view of the slope of the laminate structure. Samples can be viewed in 3D using confocal optical microscopy. Figure 58c shows a top view and an oblique view of such colored images for easy viewing. 58d shows representative elements of each layer (upper gate MOSFET channel length (Lc) 19 [mu] m, gate electrode doped (Lc) Channel lag distance (Lo) 5.5 μm, channel width (W) 200 μm, defined as the distance extending over the source / drain regions. The devices above each of the three layers formed on the PI substrate had excellent properties (linear motion of 470 +/- 30 cm ² / Vs, on / off ratio> 10 ^4, and threshold voltage of -0.1 ± 0.2 V ) And there is no systematic difference between the elements in the other layers. Additional layers may be added to this system by repeating the same processes. 59, various semiconductors can be used in multiple layers to form a complete 3D-HGI system, in addition to a 3D circuit with a single semiconductor. To illustrate this capability, we fabricated arrays of MESFETs (especially high electron mobility transistors, HEMTs), MOSFETs and TFTs using GaN and Si nanoribbons and SWNT films, respectively, on the PI substrate. 59A and 59B show high magnification optical and co-focus images of the resulting elements, respectively. The GaN HEMT on the first layer uses ohmic contacts (Ti / Al / Mo / Au annealed on the source wafer) to the source and drain and Schottky (Ni / Au) contacts to the gate. The channel length and width and gate width are 20, 170 and 5 탆, respectively. Each device uses a GaN ribbon (consisting of multiple stacks of AlGaN / GaN / AlN) electrically interconnected by a process on the device substrate, with thicknesses, widths and lengths of 1.2, 10 and 150 μm, respectively. The SWNT TFT on the second layer uses SiO2 / epoxy for the gate dielectric film and Cr / Au for the source and drain, and has a channel length and width of 50 and 200 [mu] m, respectively. The Si MOSFET uses the same design as that shown in FIG. Various other 3D-HGI devices can be constructed using different combinations of Si, SWNT, and GaN (FIGS. 61 and 62). Figure 59c shows the current-voltage characteristics of typical devices in the systems of Figures 59a and 59b. In all cases, the characteristics are similar to those produced on a source wafer: a GaN HEMT has a threshold voltage (Vth) of -2.4 + - 0.2 V, a transconductance of on / off ratio> 10 ⁶ and 0.6 + - 0.5 mS, Lt; / RTI > SWNT TFTs have a Vth = -5.3 +/- 1.5 V, an on / off ratio > 10 ⁵ and a 5.9 + 2.0 cm ² / Vs linear mobility; Si MOSFETs have a Vth = 0.2 +/- 0.3 V, on / off ratio &gt; 10 ⁴ and 500 +/- 30 cm ² / Vs linear mobility. An interesting aspect of these devices is the mechanical bendability resulting from the use of a thin PI substrate (25 μm), a device (2.4 μm) and a PI / PU interlayer (5 μm) It is important for applications to. We have evaluated the effective transconductance ( _gff ) for Si, SWNT and GaN devices in the 3D-HGI system of Figure 59a as a function of the bending radius. _59D showing this data is normalized with respect to the transconductance g _0eff in the _unbent state, showing a stable performance for a bend radius below _{3.7 mm} .

Electrical wiring formed between different levels in these 3D-HGI devices can create interesting circuit performance. Thin polymer interlayers enable these interconnects to be readily formed by depositing metal lines over and into lithographically defined openings. Figure 60 shows several embodiments. 60A is a 3D NMOS inverter (logic gate) with a drive (L = 4 mu m, W = 200 mu m) and a load (L = 4 mu m, W = 30 mu m) Si MOSFETs on different levels. At a supply voltage of 5 V, this dual-layer inverter shows a clear transfer characteristic with a gain of ~ 2, comparable to that of a conventional planar inverter using a similar transistor (25). FIG. 60B shows an integrated n-channel Si MOSFET and p-channel SWNT TFT designed to equalize the current-drive capability in both directions of pull-up and pull-down and having a complementary design (CMOS) The inverter is shown (Fig. 65). A green transfer curve is shown in Figure 60A by applying a 5V bias to the VDD terminal and irradiating the gate voltage (input) from 0V to 5V. The shape of the curve and gain (as high as ~ 7) qualitatively match the computational circuit simulation (Fig. 65). As a third example, in order to demonstrate the ability to fabricate unit cells that can be used in an active IR imager, we have fabricated a GaAs metal-semiconductor-metal (MSM) infrared (IR) detector 26). In this case, printed GaAs nanoribbons (thicknesses, widths and lengths of 270 nm, 100 μm and 400 μm, respectively) transferred onto a substrate with a printed array of Si nanoribbon MOSFETs form the basis of the MSM. The electrodes deposited on the ends of these GaAs nanoribbons (Ti / Au = 5/70 nm) form a continuous Schottky diode with a separation of 10 [mu] m. The resultant detection cell shows an improvement in current as the intensity of the IR irradiation increases (Fig. 60C), which is consistent with circuit simulation (Fig. 66). At a wavelength of 850 nm, the reactivity of about 0.3 A / W was observed from 1 to 5 V without considering the light reflected from the semiconductor surface. The system also showed the possibility of bending with a radius of curvature of less than 1 cm, which can be used for advanced systems, such as a focal plane array of curved surfaces for wide angle IR night vision cameras.

Printed semiconductor nanomaterials provide a new approach to 3D-HGI systems, and applications in various fields, as suggested by the systems reported here, as well as micro-emulsion engineering with integrated reading and sensing electronics Devices, chemical / biosensor systems incorporating non-conventional sensing materials into conventional silicon-based electronics, and other photonic / optoelectronic systems incorporating compound semiconductor light emitters with silicon- It can be applied to applications. Furthermore, the suitability of this approach with thin, lightweight plastic substrates will create additional opportunities for devices with unusual form factors or mechanical flexibility as key features.

Materials and methods: Device fabrication: Silicon devices: Fabrication is performed by treatment of contact dope (SOI) by treatment of a silicon wafer on insulator (Soitec uni-bond with 290 nm top Si layer with a doping level of SOI of 6.0-9.4 x 10 ¹⁴ / cm ³ ) We begin by defining thin ribbons of single crystal silicon. The first step is phosphorous doping using a solid source and a spin-on-dopant (P509), plasma enhanced chemical vapor deposition (PECVD) deposited SiO2 as a mask to control diffusion of the dopant into silicon, 300 nm, 900 mTorr, 350 sccm, 2% SiH4 / He, 795 sccm NO2, 250 占 폚). After doping, a SF6 plasma etch through the patterned photoresist layer defined the ribbon. The oxide film buried with concentrated HF solution (Fisher Chemicals) was undercut etched to release the ribbon from the wafer. This process completed the fabrication of the contact doped monocrystalline silicon ribbon. In the next step, a planar elastic stamp of polydimethylsiloxane (PDMS, A: B = 1:10, Sylgard 184, Dow Corning) is contacted with a ribbon coated with a photoresist, The wafers were removed and the ribbons were attached to the surface of the stamp by a half-valued force between the hydrophobic PDMS and the photoresist. The 'inked' stamp with the s-Si ribbon from the wafer was a 25 micron polyimide (PI) sheet (Dupont) coated spin-coated with a liquid PI precursor, a thin film of Sigma_Aldrich Inc. , &Lt; / RTI &gt; Kapton 100E). Curing of the precursor, peeling-off of the PDMS stamp and removal of the photoresist were such that the ribbons were embedded on the surface of the PI substrate and adhered well. A gate dielectric layer consisting of a layer of SiO2 (thickness ~ 100 nm) was deposited by PECVD at a relatively low temperature of 250 &lt; 0 &gt; C. Photolithography and CF4 plasma etching defined the openings for the source / drain regions of the silicon. Gate electrodes of source, drain and Cr / Au (5/100 nm, from bottom to top by electron beam deposition, Temescal FC-1800) were defined in a single step by photolithography and wet etching.

GaN devices: GaN microstructures were fabricated on a GaN bulk with hetero structure [AlGaN (18 nm) / GaN (0.6 탆) / AlN (0.6 탆) / Si]. The ohmic contact area was defined by AZ 5214 photoresist and then cleaned with a SiCl4 plasma in a RIE system. A Ti / Al / Mo / Au (15/60/35/50 nm) metal layer was then deposited by electron-beam evaporation (Ti / Al / Mo) and thermal deposition (Au). The resist was rinsed to complete the remaining metal contacts on the GaN. A thermally annealed ohmic was formed in an N2 atmosphere at 850 DEG C for 30 seconds. Layers of SiO2 (Plasmatherm, 300 nm, 900 mTorr, 350 sccm, 2% SiH4 / He, 795 sccm NO2, 250 캜) and Cr metal (electron-beam evaporator, 150 nm) were used as mask material for subsequent inductive couple plasma Lt; / RTI &gt; Photolithography, wet etching and RIE processes (50 mTorr, 40 sccm CF4, 100 W, 14 minutes) defined the ribbon shape of GaN. After removal of the photoresist with acetone, ICP dry etching (3.2 mTorr, 15 sccm Cl 2, 5 sccm Ar, -100 V bias) was performed to remove the exposed GaN and slightly etch into the Si (~1.5 urn) to promote subsequent anisotropic viewing , 14 minutes) was used. Subsequently, Si under the GaN was etched using tetramethyl ammonium hydroxide (Aldrich, 150 캜, 4 minutes 30 seconds). The sample was soaked in BOE (6: 1, NH4F: HF) for 30 seconds to remove the PECVD SiO2 and a new 50 nm electron-beam deposited SiO2 layer was deposited on top of the GaN ribbon. The 'inked' PDMS plate with GaN ribbon from the mother wafer was then laminated to a PI sheet coated with 2 쨉 m polyurethane (PU, Norland optical adhesive, No. 73). Samples were exposed to UV light (173 uWcm ^{- 2} ) for 15 min to cure PU. The GaN elements were transferred onto the plastic substrate by stripping the PDMS and immersing in BOE for 20 seconds to remove the electron-beam SiO2. A negative photoresist (AZ nLOF2020) was used to pattern the Schottky contact of Ni / Au (80/180 nm). The photoresist was removed with an AZ stripper (KWIK, 30 minutes).

SWNT Devices: Chemical vapor deposition (CVD) was used to grow a random network of individual single-walled carbon nanotubes on SiO ₂ / Si wafers. Ferritin (Sigma Aldrich) deposited on a substrate with methanol was used as a catalyst. The feed gas was methane (CH ₄ 1900 sccm and 300 sccm H _2). Before the growth, the quartz tube in the furnace was flushed with a high flow rate of Ar gas for cleaning. During the growth, the temperature was maintained at 900 占 폚 for 20 minutes. The transfer involved a slightly different method of coating the SiO ₂ / Si substrate with the Au layer and the PI precursor similar or thicker to the print, similar to the processes described above. After the PI was cured, the Au / PI was peeled off. This layer was coated with a thin epoxy layer (SU8, 150 nm), laminated on a pre-patterned device substrate, and then the PI layer and Au layer were removed by oxygen reactive ion etching and wet etching, respectively. In the case of bottom gate devices, the substrate supported pre-patterned gate electrodes and dielectrics. In particular, Cr / Au / Cr (2/10/10 nm) gate electrodes were patterned by photolithography, and then 300 nm SiO ₂ was deposited on the substrate using PECVE. The source and drain electrodes of Cr / Au (2/20 nm) were defined directly on top of the tube.

3D Circuit: 3D Si NMOS Inverter: Multilayer devices were fabricated by repeated application of the same fabrication process. In particular, the PI precursor was spin-cast onto the top of the existing layer of the device, and the silicon ribbons were also transferred-printed onto top. The same processes were then used to fabricate the devices. The electrode regions are defined by photo-patterning openings in a layer of AZ4620 photoresist for vertical metal interconnects, and then SiO ₂ and PI are implanted in the RIE system to form CF ₄ and O ₂ plasmas And removed by etching. By depositing Al of 300 nm in the region forming the lower contact, and further provided an electrical connection with a continuous edge on the steps formed by the etching of SiO ₂ and PI.

SWNT and Si CMOS Inverters: The SWNT devices consisted of gold (20 nm) source / drain contacts defined by photolithography on a tube network. The SiO ₂ (100 nm) / Si wafer substrate provided gate dielectrics and gates. An epoxy (SU8, 500 nm) was then spin-coated onto the substrate after the SWNT transistors were selectively coated with photoresist (AZ5214). After UV exposure to cure the epoxy, the &quot; inked &quot; PDMS slabs with undoped Si ribbons were laminated onto the substrate and removed by manual peeling by hand to complete the transfer-printing process. Cr / Au (5/100 nm) was used as Schottky contacts for the source and drain electrodes in silicon devices. Al (100 nm) was used to connect the SWNT and the Si transistor.

Si TFT and integrated GaAs MSM IR detector: GaAs wafers (IQE Inc., Bethlehem, PA) were used to fabricate back-to-back Schottky diodes. The ribbons were produced from high-quality bulk wafers of GaAs with multiple epitaxial layers (Si-doped n-type GaAs (120 nm) / semi-insulated (Si) -GaAs (150 nm) / AlAs -GaAs]. carrier concentration of the n- type GaAs is 4 × 10 ¹⁷ cm ^{- 3.} GaAs wafers with photoresist masks were anisotropically etched in an etchant (4 mL H ₃ PO ₄ (85 wt%), 52 mL H ₂ O ₂ (30 wt%), and 48 mL deionized water). The AlAs layers were removed by etching with an ethanol-diluted HF solution (2: 1 by volume). Layers of 2 nm Ti and 28 nm SiO ₂ were deposited by e-beam evaporation. The GaAs ribbons and the inked PDMS stamp were then in contact with a layer of Si transistor coated with PI (1.5 탆 thick). The PDMS was peeled off and Ti and SiO ₂ were removed with a BOE etchant to complete the transfer of GaAs to the device substrate. Metals (Ti / Au = 5/70 nm) for Schottky contact were deposited by e-beam evaporation. The electrical interconnection between the GaAs back-to-back Schottky diodes and the Si MOSFET is patterned first with a layer of AZ4620 photoresist and the CF ₄ and O ₂ plasmas are used in the RIE system to form openings Lt; RTI ID = 0.0 &gt; 300 nm. &Lt; / RTI &gt;

Device characterization: Electrical characteristics of diodes and transistors were measured using a semiconductor parameter analyzer (Agilent, 4155C) and a conventional probe. The IR response was measured under an IR LED source with a wavelength of 850 nM.

Circuit Simulation: A level 2 PSPICE model for n-channel Si MOSFETs and p-channel SWNT TFTs was experimentally generated to compare the measured transfer curves of CMOS inverters with the simulated results. These PSPICE models were generated by extracting parameters that fit the measured IV curves of both Si NMOS and SWNT PMOS shown in Figure 65B based on the default PSPICE MOSFET models (MbreakN and MbreakP). The PSPICE model for GaAs MSM photo-detectors was experimentally fabricated using back-to-back Schottky diodes in series with Si MOSFETs.

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Pop-up architectures are useful for aggregating a variety of device architectures and structures into embedded structures, but they are difficult to implement. It is an architecture that enables the implementation of critical capability devices that represent the functionality of electrical, optical, mechanical, and thermal forms. For convenience, the following specific embodiments are described in terms of basic mode functionality, but in many cases, system designs employ hierarchical effects that enable apparent device level performance results.

Electronic systems. The most immediate form of utility in the art is the provision of the above-described architectures that benefit from the design of complex, mechanically compatible electronic devices, where complex, mechanically compatible electronic devices are used in high performance electronic circuits- Sensing elements, RF-ID tags, including some challenging types of applications that benefit from the integration of electronic circuits. The designs disclosed herein significantly extend the entire range of mechanical compatibilities that can be realized. This specifies the specific architectural details that, at the system design level, can extend the range of mechanical deformations that can withstand the general limit of 1% typical strain for a device based on the planar integration of the components Thereby significantly extending the entire range of mechanical compatibility. The examples illustrate the simplest elements, concrete architectures for interconnects, where the concrete architecture is to provide a high level of formal system high level variants (greater than 30% in the appropriate form factor for the structure of bus lines and interconnects in the display) But also can be used to provide mechanical compatibility (resilience) of other more desirable forms. These benefits may also be extended to more complex device level components as illustrated by the exemplary devices shown in FIG. 31, the form factor of the GaAs MSM IR photodetector described above. All functional components of an essentially complex electronic system can be integrated into a design-specific, mechanically compatible form using the methods taught herein.

Optical components and systems. Optical components, such as waveguides, can respond with extreme sensitivity to the bend. These methods and systems provide new architectures for such devices that can withstand mechanical bends that benefit functional performance and, more importantly, utilize mechanical bends. Examples of techniques that can directly utilize the methods disclosed herein include improved types of photonic components, including, but not limited to, waveguide optical couplers and associated types of optical switches and limiters . At the system level of the integrated structure, the mechanical bend provides direct means (via compression or expansion) to influence these functionalities. Moreover, the loss in the channel is directly related to the significantly curved radii that promote leakage in an adjustable way from the bend-core mode of the waveguide to the sheath mode. These effects can be directly applied to various devices. For example, Figure 67 shows a waveguide array created through controlled buckling of optical microstructures partially attached to a deformable substrate. 67A shows that an optical device is created by attaching component 330 (e.g., a waveguide such as an optical fiber or other elongated microstructure) to substrate 30 by, for example, contact printing. The attachment includes strongly tied contact regions 310 and weakly bound regions corresponding to raised regions 320. As a modification, the second electrode deflects and the weakly touched region of the waveguide is physically separated from the substrate, thereby creating an elevated region. The device can simply operate as a waveguide which can have a significant resilience (of 5 to 50%) (see FIG. 67B). In another embodiment, the refractive indexes of the waveguide and the substrate as well as the buckling geometry can be selected so that the device operates with an optical switch and, due to high distortion in the buckled waveguides, (See FIG. 67A), but not in the shortened state (see FIG. 67A) (see FIG. 67B).

Mechanical functional systems. The intersection between mechanics and electronics is the basis for technologies in many important fields - inertial and other types of force sensors include specific examples, both of which are of current interest and discovery of widespread use. The methods and systems disclosed herein provide a way to create new types of such devices. Figure 68 is a representative example of a mechanical system, particularly an entwined multilayer architecture for capacitively coupled sensing. This exemplary architecture enables significant forms of force-related sensing - most notably inertia and pressure measurements. In each case, the methods and systems disclosed herein allow for their integration into new, compact form factor systems (e.g., by allowing integration of electronic systems in new ways) Many system-level aspects of the performance of devices - most notably provide a relatively direct means of controlling the dynamic range and area of optimal sensitivity. These structures supplement existing established MEMS-based approaches to these types of devices. 68, a mechanical device 400 (e.g., an accelerometer / pressure sensor) is produced through controlled buckling of a conductive microstructure partially attached to a changeable substrate 30. This device architecture can be used to determine the capacitance between the lower electrode 450 and the other electrode 440, which occurs when the raised region 320 of the other electrode 440 is moved relative to the substrate through acceleration or pressure in the z- By sensing changes. The device 400 is produced by providing an electrode (lower electrode 450) on a substrate 30 and then attaching another electrode 440 by contact printing. The attachment includes strongly tied contact areas 310 and weakly tied areas (e. G., In the area below 320). In a variation, the second electrode 440 is deflected and the weakly tied region is physically separated from the substrate, thereby creating the raised region 320.

Thermal function devices. The pop-up architectures supplied with the present invention result in new capabilities that provide thermal isolation of complex electronic components. The distinct device type provides a common design for the pixel elements of the long wavelength imaging system which provides direct integration and accurate thermal isolation of the two thermal devices that are thermally responsive (and for this example) High performance electronic components that provide other capabilities for read out, data handling, and systems. This required architecture is easily accessed using the methods taught by the present invention. In this case, functional electronic components, such as the AD converter required to read the pixel, are placed in close proximity to the IR response elements (suitable examples include Si and thin film multilayer photoresist supported on a SisN4 film ) Metal oxide films), i. E., Features that make it possible to simplify the design and improve performance are possible. Most notably, the systems and devices provided herein provide the ability to integrate such device elements in a non-planar focal array. Figure 69 shows a thermal device 500 (microbolometer) produced through controlled buckling of a heat resistant microstructure partially attached to a deformable substrate. The device 500 is produced by attaching an electrode 550 comprising a heat resistant material 560 to a substrate 30 by contact printing. The attachment includes strongly tied contact regions 310 and weakly bound regions corresponding to raised regions 320. The electrode 550 is deflected and the weakly tied region is physically separated from the substrate thereby creating an elevated region 320 that is thermally isolated from the substrate to a wide extent thereby permitting accurate and local In temperature sensing.

U.S. Patent Application Nos. 11 / 115,954, 11 / 145,574, 11 / 145-542, 60 / 863,248, 11 / 465,317, 11 / 423,287, 11 / 423,192, / RTI &gt; 421,654, incorporated herein by reference to the extent not inconsistent with the present disclosure.

All references throughout this application include, for example, patent documents that include issued, patented or equivalents; Patent application publications; And non-patent literature documents or other source materials are incorporated by reference in their entirety to the extent that each reference is not, at least in part, inconsistent with the disclosure of the present application (for example, , A partially mismatched reference is merged as a reference except for the partially mismatched part of the reference).

The terms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of appearing and excluding equivalents of the features described or portions thereof, It will be appreciated that the invention is susceptible of embodiment within the scope of the claimed invention. Therefore, while the present invention has been specifically disclosed in preferred embodiments, exemplary embodiments and optional features, it is to be understood that alterations or variations of the concepts herein disclosed may be resorted to by those skilled in the art And that such changes and modifications may be considered within the scope of the present invention as defined by the appended claims. It is to be understood that the specific embodiments provided herein are examples of useful embodiments of the present invention and that the present invention may be practiced using numerous variations of the apparatus, It is obvious to those of ordinary skill in the art. As will be apparent to those skilled in the art, methods and apparatus useful in the present methods may include a number of optional configuration and processing elements and steps.

All representations or combinations of the elements recited above or exemplified herein may be used in the practice of the invention, unless otherwise indicated.

* In the present description, whenever a range, for example, a temperature range, a time range, or a configuration or concentration range is given, all intermediate ranges and subranges, as well as all individual values contained in the given ranges, Are intended to be included in the specification. Any sub-ranges or individual ranges in the ranges or sub-ranges contained herein may be excluded from the claims herein.

All patents or publications mentioned in this specification are indicative of the levels of those of ordinary skill in the art to which this invention belongs. The references cited herein are incorporated herein by reference in their entirety to indicate the technical field of their disclosure or filing date and that this information may be used herein to exclude certain embodiments of the prior art, Is intended. For example, if the composition of a substance is claimed, mixtures which are known and available in the prior art to the applicant's invention, including the mixtures provided in the references cited in this specification, Are not intended to be &lt; RTI ID = 0.0 &gt; intended &lt; / RTI &gt;

As used herein, the term "comprising" is synonymous with "including", "containing", or "characterized by" and is inclusive or open- ended, and does not exclude additional, unrecited elements or method steps. As used herein, &quot; consisting of &quot; excludes any element, step or component not specified in the claim element. As used herein, &quot; consisting essentially of &quot; does not exclude materials or steps that do not materially affect the basic and novel characteristics of the claims. In each of the examples herein, &quot; comprising, &quot; &quot; consisting of, &quot; and &quot; consisting essentially of &quot; The invention illustratively described herein may be practiced in the absence of any element or element, limitation or limitation not specifically disclosed herein.

Those skilled in the art will recognize that the starting materials, biological materials, reactants, synthesis methods, purification methods, analytical methods, test methods, and biological methods not specifically illustrated thereof, Without departing from the scope of the present invention. All technically known functional equivalents of such materials and methods are intended to be included within the scope of the present invention. The terms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention in the use of the terms and expressions to exclude any equivalents of the disclosed and disclosed features, And that various modifications are possible. Therefore, although the present invention has been specifically disclosed in preferred embodiments and optional features, variations and modifications of the concepts disclosed herein may be resorted to by one of ordinary skill in the art And such variations and modifications are considered within the scope of the invention as defined by the appended claims.

Claims (6)

A flexible multilayer device comprising:
A flexible substrate;
An intermediate structure at least partially supported on the surface of the flexible substrate;
A first device layer disposed over the flexible substrate and at least partially embedded in the intermediate structure, the first device layer comprising a first device component and at least one tensionable first conductive structure;
An interlayer disposed over the first device layer and comprising a polymeric material;
A second device layer disposed over the interlayer and comprising a second device component; And
An electrical interconnect having a first end and a second end and extending through a portion of the interlayer;
Lt; / RTI &gt;
Wherein a first end of the electrical interconnect is in electrical communication with the first device component,
A second end of the electrical interconnect being in electrical communication with the second device component,
Wherein the first device component forms a part of a two-dimensional array,
Further comprising at least two tensionable interconnects,
Each of the at least two tensionable interconnects having a first end, a second end, and a central portion intermediate the first end and the second end,
The at least two tensionable interconnections extending along at least two different directions from the first device component to form the two dimensional array in a plane of the surface of the flexible substrate,
Wherein a first end of each of the at least two tensionable interconnects is in electrical communication with the first device component,
Wherein a central portion of each of the at least two tensionable interconnects comprises an area of a bending configuration. The method according to claim 1,
Wherein the tensionable interconnect, the electrical interconnect, or both comprise a metal or an alloy thereof. delete The method according to claim 1,
Wherein the tensionable interconnect, the electrical interconnect, or both comprise a semiconductor material. 5. The method of claim 4,
Wherein the semiconductor material comprises silicon, indium tin oxide, or GaAs. A flexible multilayer device comprising:
A flexible substrate;
An intermediate structure at least partially supported on the surface of the flexible substrate;
A first device layer disposed over the flexible substrate and at least partially embedded in the intermediate structure, the first device layer comprising a first device component and at least one tensionable first conductive structure;
An interlayer disposed over the first device layer and comprising a polymeric material;
A second device layer disposed over the interlayer and comprising a second device component; And
An electrical interconnect having a first end and a second end and extending through a portion of the interlayer;
Lt; / RTI &gt;
Wherein a first end of the electrical interconnect is in electrical communication with the first device component,
A second end of the electrical interconnect being in electrical communication with the second device component,
Wherein at least one of the first device component and the second device component comprises a physical sensor, a biosensor, a chemical sensor, an accelerometer, a pressure sensor, or any combination thereof.

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