JPS58124373A - Signal clamping system - Google Patents

Abstract

PURPOSE:To obtain a signal clamped to a value being set digitally, by controlling a clamp level of a clamp circuit in response to the output signal level of an A/D converter. CONSTITUTION:A digital comparison result ''0'' or ''1'' from a digital level comparator 4 and a clamp timing pulse S4 are applied to a gate 6, the comparison result ''0'' or ''1'' is applied to a switch SW in the timing of the pulse S4 to control the turning on/off of the SW. When the switch SW is turned on, a capacitor C1 is charged and when the switch SW is turned off, the capacitor C1 is discharged. Thus, the analog clamp level of the input to an amplifier 5 is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal clamping method in analog-to-digital conversion, and particularly to a method for making an analog-to-digital conversion output a signal clamped to a digitally set value.

In a digital television system,
In many cases, it is desired to set the clamp level digitally. The reason for this is that high-speed analog-to-digital converters for video (hereinafter analog-to-digital converters are referred to as A
The A/D converter (abbreviated as the A/D converter) itself contains a considerable amount of DC drift, so even if you try to specify the level at the analog stage, the absolute value of the digital signal at the A/D converter output cannot be determined. Can you name something that is difficult to determine?
On the other hand, in digital signal processing systems such as multi-human power, it is necessary to match the black level of the five image signals as a whole, and the digital value of the human power image signal must be determined even when processing such as changing the pedestal. need to be.

Therefore, it is conceivable to extract the pedestal level during the blanking period from the A/D-converted digital image signal in digital signal form B and clamp it digitally, but this would complicate the circuit configuration and require a clamping unit. amount(
It is not possible to reduce the offset (minimum correction layer) below the /quantization level.

In view of the above points, it is an object of the present invention to perform clamping using an analog method, and to clamp the signal to a digitally set value using the analog-to-digital conversion output. The object of the present invention is to provide a signal clamping method that can be used as a signal clamping method.

In order to achieve this objective, the present invention provides a clamp l! 2
Place the circuit before the analog-to-digital converter (~
, the clamp level of the clamp circuit is controlled in accordance with the output signal level of the analog-digital converter.

In a preferred embodiment of the present invention, the A/D converted output signal is digitally compared to a predetermined clamp setting level, for example during a synchronization signal period, and the comparison result is feedbanked to an analog clamper.

The following points can also be mentioned as advantages of the present invention. In other words, when converting an analog signal to A/D, it is necessary to clamp it before the A/D conversion. However, in order to accommodate the operating range of the A/D converter, the dynamic range must be expanded by an additional 4 dB, which is wasteful.
/ By providing an analog clamp circuit (hereinafter abbreviated as analog clamper) before the D converter and appropriately controlling the clamp level of the analog clamper using feedbank control, the digital level during the clamp period is set to the desired value. , the clamp level can be set digitally, and therefore the drawbacks mentioned above do not occur.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the basic configuration of the present invention, where / is an analog clamper 1.2 is an A/D converter, 3 is an integrator, and Hiroshi is a digital level comparator. A digital clamp level setting value 8 is added to the comparator, and the analog input signal 8zY is input to the A/
Supplied to D converter 2.

The A/D conversion output is taken as a digital output signal S3 and is supplied to a level comparator together with the signal generator, compared with a set value S1 of the clamp level, and the result of the comparison is integrated by an integrator 3. The integrated output is supplied as a clamp level to an analog clamper in the form of a feed bank.

According to the above configuration, the digital output signal S3 is digitally compared during the digital clamp level setting f&sx, for example, during the synchronization signal period, and the amount obtained based on the comparison result is feedbanked to the analog clamper. , digital (3) The clamp level of the output signal S3 is the digital clamp level setting value S! will match.

Next, an example of a specific configuration of the present invention is shown in FIG. Here, the same parts as in FIG. 1 are given the same reference numerals. In FIG. 2, 5 is a bumper amplifier 1g in the form of an I') C amplifier, a clamp gate using an AND gate, and a C
1 is a capacitor, R1 and IL2 are resistors, and SW is a switch. The analog input signal S2 is connected to the capacitor C1.
and is supplied to the A/D converter through the amplifier j. The output side of the capacitor C is connected via a resistor R1.
(2) Connect the power supply and also connect the 10V power supply via the resistor R2 and switch sW. Turn this switch SW to the output of gate B and turn it off. That is, the gate B receives the digital comparison result O or l from the digital comparator G.
and a clamp typing pulse S4, and at the timing of this clamp timing pulse s4, the digital comparison result 0 or / is supplied to the switch SW to control its on/off. When the switch SW is turned on, the capacitor Cl is charged (≦), and when the switch SW is turned off, the capacitor C1 discharges only σ), thereby changing the analog clamp level of the input to the amplification field 5. Therefore, this circuit has A/
Feed bank clamp system included in D conversion word +
NrN,l,, the digital output signal is clamped to a digital clamp level setting value S1. In addition, if the clamp level or peak value is reached, the clamp gate 6
is not necessary.

FIG. 3(-1) shows another example of the specific configuration of the present invention.

Here, a keyed clamp type configuration is adopted, where 7 is a digital averager, 7 is a D/A converter, 1 is a digital subtracter, /θ is a digital type coffin, and /' is a keyed clamper. Also, a clamp pulse S't is supplied to the clamper l' and the averager 7, and both circuits are operated only during the period of the clamp pulse S5.
The digital output signal S3 from the transducer λ is averaged by an averager 7 during the period of the clamp pulse S5, and during the remaining period, the averaged value is applied to the averager 70 (IB force &) to the next clamp. It is held until the arrival of pulse S5. Sword) average value and digital level setting value 8. A subtracter wa calculates the difference between the two, and the digital difference output is integrated by an integrator /θ, and then converted into an analog value by a D/A converter t. In this example, the difference output from the subtractor W is set to either positive or negative values, and accordingly
Positive and negative analog levels are obtained from the /D converter.

This level is supplied to the keyed clamper/' as an analog clamp level, and the analog input signal S is clamped to the above analog clamp level at the timing of the clamp pulse S5, thereby clamping the digital output signal S3Y to the set value S□ of the digital clamp level. do.

FIG. It is supplied to the output side of C2 to charge and discharge the capacitor C2. As a result, the input level of the analog input signal S2 supplied to the bumper amplifier via the capacitor C2 is shifted and the analog input signal S2 is clamped, and the digital output signal S3 is set to the digital clamp level. Clamp to set value S1. If a long clamp time constant is acceptable, a simple configuration can be used in which the keyed clamper is omitted, as in this example.

As described above, according to the present invention, A/D can be achieved with a simple configuration.
A signal clamped to a digitally set value can be obtained as the output signal of the converter. Further, in the present invention, although the clamp level is set in units of quantization level, there is an advantage that the offset of the analog input signal is continuously corrected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the signal clamping system of the present invention, and FIG. 4.2, FIG. 3, and FIG. l・Analog clamper /l... Keyed clamper, 2... A/D converter, 3... Integrator, G...
Digital level comparator, 5 bumper amplifier, O...clamp gate,
(9) 7... Dintal type averager, r/D/A converter, ?・Digital type subtracter, lθ...Digital type power divider, CI+C2...Capacitor, R1+R2+3...Resistor, SW...Switch, Sl...Digital clamp level setting value, S2...Analog input signal , S3...Digital output signal, S4...Clamp iminder pulse, S5...Clamp pulse. Patent Applicant Japan Broadcasting Corporation Figure 1 Anaroa Input No. 52 Figure 2 7 Run 7ゝ Taimin Kuha 0 Rusushi 4 Figure 3 0 Figure 4

Claims (1)

[Claims] 1) A clamp circuit is placed before an analog-to-digital converter, and the clamp level of the clamp circuit is controlled in accordance with the output signal level of the analog-to-digital converter. A signal clamp method featuring: 2) Comparing the levels of the output signal of the analog-to-digital converter and a reference digital signal corresponding to the clamp level setting value, or detecting the difference between these two signals, and applying the obtained digital signal to the clamp circuit. 2. The signal clamping method according to claim 1, wherein the clamping level is controlled by supplying the signal. 3) The signal clamp method according to claim 2, wherein the digital signal for controlling the clamp level is supplied to the 611th clamp circuit via an integrating circuit. 4) The output signal of the integrating circuit is supplied to a digital-to-analog converter to be converted into an analog signal, and then supplied to the lamp circuit. Signal clamp method.