JPS63204975A - Signal level clamping circuit - Google Patents

Abstract

PURPOSE:To remove an offset voltage, including the one produced from a signal processing circuit itself, and to set a highly precise signal level setting by giving a feedback to the output signal of the signal processing circuit, after converting it to a digital signal, and clamping the voltage level of the input signal of the signal processing circuit. CONSTITUTION:A clamping voltage is adjusted based on a digital voltage quantity, outputted from the signal processing circuit to process the input signal. Namely, the digital quantity of the voltage, outputted by the signal processing circuit, and a digital code, corresponding to the target reference voltage level are compared by a comparator 11, and the digital quantity corresponding to their difference voltage is outputted. Next, the digital quantity is converted into an analog quantity V10 by a D/A converter 12, and further, the analog voltage quantity V10 is added or subtracted during the specified period of the input signal. As the result of the addition or the subtraction of the first time, when the difference voltage appears still in the output of the comparator 11, the clamp voltage quantity V8 is corrected by giving the further feedback. Thus, the feedback is given until the difference voltage comes to zero substantially. Thus, the setting of the highly precise clamp voltage is made possible.

Description

[Detailed Description of the Invention] [Summary] The signal level clamp circuit of the present invention applies feedback after converting the output signal of a signal processing circuit into a digital signal, and clamps the voltage level of the input signal of the signal processing circuit. Features.

According to the present invention, it is possible to remove including the offset voltage generated from the signal processing circuit itself, thereby making it possible to set the signal level with high precision. This allows the signal processing circuit to perform appropriate signal processing.

[Industrial application field]

In a signal such as a video/image signal, in addition to a signal portion that is substantially a video-image signal, a reference level portion that is a reference level of the signal is included.

Conventionally, this signal portion is clamped to a specific voltage to optimize subsequent signal processing by a signal processing circuit.

The present invention relates to a signal level clamp circuit that clamps this reference level signal portion to a specific voltage,
More specifically, the present invention relates to a signal level clamp circuit that clamps a reference level signal portion of a video/image signal to a specific voltage.

[Lented technology]

FIG. 9 is an explanatory diagram of a conventional signal level clamp circuit. In FIG. 9(a), Vl is a signal output from a signal source, V2 is a signal input via a coupling capacitor 1k Cc,
l is a signal processing circuit consisting of a buffer 2 and an A/D converter;
V3 is a digital output signal of the signal processing circuit l.

Further, VB is the voltage of the bias power supply, and SB is a switch that is turned on when the signal portion a of the reference level of vl is input via the coupling capacitor CC, and clamps the signal portion of the reference level of v2 to the bias voltage ve. be.

(b) and (C) of the same figure are diagrams showing voltage waveforms of V1 and V2 during the sonograph rotation.

In this way, by clamping the reference level signal portion of v2 to the voltage Ve, the voltage level of the video/image signal can be kept within the voltage range that can be processed by the next-stage signal processing circuit 2. Appropriate signal processing by the signal processing circuit l becomes possible.

FIG. 10 is an explanatory diagram of a signal level clamp circuit according to another conventional example, and is shown in FIG. 10(a).

v4 is the output signal of the signal source, Cc is the coupling capacitance, 4 is the analog adder, V5 is the output signal of the analog adder, VB is A
/D converter 5 digital output signal.

6 is an S/H circuit that samples and holds the reference level signal portion of v5; 7 is an analog adder that adds and subtracts the output voltage of the S/H circuit 6 and the bias power supply voltage VB;
A buffer 8 amplifies the output voltage of the analog adder 7 and sends it to the analog adder 4.

According to this circuit, since feedback is applied to set the reference level signal portion of v5 to a predetermined voltage, more accurate voltage clamping is possible.

[Problem that the invention seeks to solve]

By the way, since the conventional circuit No. 954 does not have a configuration that applies feedback, it is not possible to clamp the voltage with high precision, and due to clock field through etc. when the switch S8 is switched from on to off, the circuit shown in FIG. As shown in (C), an offset voltage ΔV is generated.

According to another conventional circuit shown in FIG. 10, there is no problem like that shown in FIG. 9 because the circuit is configured to apply feedback.

However, since the A/D converter 5 is not included in the feedback loop, it is not possible to remove the offset voltage generated from the A/D converter 5, and it is also impossible to remove the offset voltage generated from the analog adder 7. Therefore, there is still the problem that it is not possible to set the clamp voltage with high precision.

The present invention was created in view of such conventional problems, and an object of the present invention is to provide a signal level clamp circuit that makes it possible to set a clamp voltage with high precision.

[Means for solving problems]

The signal level clamp circuit of the present invention includes a comparator that compares a digital amount of voltage output from a signal processing circuit with a digital amount of a predetermined reference voltage and outputs a digital amount for the voltage difference, and an output of the comparator. In specifying a D/A converter that converts a digital voltage amount into an analog voltage amount, and a signal input to the signal processing circuit, controlling the analog voltage amount to be added or subtracted from the input signal,
and a circuit that clamps the voltage level of the input signal to a predetermined voltage.

[Effect]

According to the present invention, the clamp voltage is adjusted based on the digital voltage amount output from the signal processing circuit that processes the input signal. In other words, a zero-order D/A converter that compares the digital amount of voltage output by the signal processing circuit with a digital code corresponding to a target reference voltage level using a comparator, and outputs a digital amount corresponding to the difference voltage. converts the digital quantity into an analog voltage quantity, and further adds or subtracts the analog voltage quantity in a specific period of the input signal.

If a difference voltage still appears in the output of the comparator as a result of the first addition-subtraction, feedback is further applied to correct the clamp voltage amount. In this way, feedback is applied until the differential voltage becomes substantially zero.

According to the present invention, since the feedback loop includes the signal processing circuit, offset voltage generated from the signal processing circuit can be removed.

Furthermore, since the signal voltage is digitized and compared with the reference clamp voltage level, the offset voltage generated from the comparator can be compressed to the voltage amount corresponding to the least significant bit representing the digital amount.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a signal level clamp circuit according to an embodiment of the present invention. In FIG. 0, v7 is the output voltage of the signal source, 9 is an analog adder, and V8 is an analog adder 9.
output voltage, lO is the A/D as part of the signal processing circuit.
converter.

v9 is the output voltage (digital quantity) of the A/D converter lO, 1
1 is a digital adder that compares V9 (digital quantity) and a reference voltage level (digital quantity) and outputs a digital quantity corresponding to the difference voltage.

Further, 12 is a D/A converter that converts the output voltage (digital quantity) of the digital adder 11 into an analog quantity, and its output timing is controlled by a clamp clock (GK). Reference numeral 13 denotes an integrator that integrates the output voltage of the D/A converter 12, and inputs the integrated voltage amount to one input of the analog adder 9.

FIG. 2 is a diagram specifically configuring the analog adder 9 and integrator 13 in FIG. 1 with a circuit. That is, the analog addition 's9 and the integrator 13 are 3I#! It is composed of width scales 14 and 15.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the voltage waveform diagram shown in FIG. In the figure, Vlo is D
This is the differential voltage output by the /A converter 12, and Vll is the voltage after the differential voltage is integrated by the operational amplifier 15.

First, the signal v7 is input to the positive input of the operational amplifier 14 and becomes the signal v8. After this signal v8 is digitally converted by the A/D converter 10 and becomes V9 (digital output),
A digital adder 11 compares it with a code corresponding to a reference voltage level.

As a result of the comparison, if there is a differential voltage (digital quantity), the differential voltage is converted into an analog quantity by the D/A converter 12. At this time, D/A conversion! The clamping clock that determines the output timing of signal v7 is output only when a voltage portion of a specific period of signal v7 is input. As a result, D/
The A converter 2 outputs the difference voltage between the human power signal v8 and the reference voltage level during this period. This differential voltage VI
After O is integrated by the operational amplifier 15 and becomes Vll, it is input to the negative input of the operational amplifier 14.

In this way, feedback is applied so that the voltage portion of the signal input during a specific period is equal to the reference voltage level.

Therefore, v8 can be set to a specific temperature voltage with high precision.

In particular, according to the circuit of the embodiment of the present invention, all the analog circuit parts where offset voltage occurs are included in the feedback loop, so that the offset voltage generated from the analog circuit part can be removed. Furthermore, since the voltage setting is performed by first comparing the digital amount of the signal with the digital amount of the reference voltage level, it is possible to eliminate the offset voltage generated by the conventional comparator itself that compares analog amounts. Therefore, extremely accurate flange voltage setting is possible.

FIG. 4 is a block diagram of a signal level clamp circuit according to another embodiment of the present invention.

V12 is the output of the signal source, CC is the coupling capacitor, 18 is the analog adder, V13 is the output of the analog adder 16, 17 is the A/D converter, vt 4t * the output of the A/Df converter 17 (
digital quantity).

18 is a code corresponding to V14 and the reference voltage level (
A digital adder that outputs the difference voltage (digital amount) by comparing the voltage with the digital JIT.

19 is a D/A converter, 20 is an integrator, v8 is the voltage of the bias power supply, and S8 is a switch that is turned on only for a certain period to set the voltage level of the receiving terminal of the coupling capacitor CC to v8. .

The circuit of FIG. 4 basically differs from the circuit of FIG. 1 in that a switch SB and a bias power supply (VB) are provided. As a result, the voltage level of signal V13 during a specific period is
Since the voltage is first set to VB or at least a voltage close to this, highly accurate clamp voltage setting can be quickly performed using the next feedback loop.

FIG. 5 is a circuit configuration diagram that further embodies the block diagram of FIG. 4. In FIG. 5, 21 is a buffer that amplifies V13, and 22 is A that outputs an m-bit digital voltage amount.
The /D converter 23 is an inverter that inverts v14 (digital output) of the A/D converter 22 to generate a complement.

24 is a digital adder that adds the complement of V14 and a code (m-bit digital amount) corresponding to the reference voltage level, thereby producing a digital output Xo "X@-" which indicates the voltage difference between V14 and the reference voltage level. 1 is outputted from the digital adder 24. 25 is a control circuit which inputs the digital output X6-Xs-+ and the clock signal (CK) and switches the switch S8.

SR, SJ on-fist off control and switch So~5s-1
A control signal Y8 that controls the switching operation of.

Generate YR, YJ, Yo”Y@-1.

FIG. 6 shows a latch circuit forming a part of the control circuit 25, whereby the output timing of the digital output Xi is controlled by a clock signal and is output as a U control signal Yi. Note that the control signals YB, YR, and YJ are generated by a timing control signal generation circuit (not shown) in the control circuit 25 and then output in synchronization with a clock signal.

CO''Cl-1 is a capacitor for charge storage, and between these capacitance values, CO=2'XCo (however.

k is an integer greater than or equal to 1 and less than or equal to m-1). VR
I and VB2 are reference voltages having different voltage values. Therefore, with SJ closed and SRGA open, by switching switch S1 from the TRI side to the VB2 side,
1+ = 21 XCo X (V112
-VRI) can be injected. Note that the terminal switching of the switches S and -1 of the most significant bit is opposite to that of the other switches S1. For example, when the control signal Yl that controls Sl is "1", the switch SI is connected to the VB2 side. On the other hand, 5s-1 is connected to the TRI side. This is because, for convenience of calculation, the higher-order bits are expressed as complements.・Figure 7 shows the changeover switch set to 0.
It is a circuit diagram in the case of comprising by MO5. In other words, when Yl is “L”, the CI terminal is connected to VB2, and Yl is “L”.
When l is "0", the terminal of CI is connected to TRI.

Also, in Fig. 5, VB is the voltage of the bias power supply +SB
is a switch that controls the voltage of the signal V13 during a specific period to be clamped to VB. esR is a switch that appropriately sets the terminal voltage of Ct to VB. For example, set VB = TRI, first close SR, set the terminal voltage of Ci to Vt+, and first turn switch 51 to T.
Switch to RI side. As a result, the charge accumulated in Ci becomes zero and becomes a reset state.Next, after opening S8 and disconnecting the terminal of C1 from VB, when the switch of Sl is switched to the VB2 side, Ct X (VB2 - VRI) = Q
A charge of l is injected (for C1-1, Cm
A charge of -+X (V R1-VB2) is injected.

).

SJ is a switch that appropriately connects the terminal of Ci to the receiving terminal of the coupling capacitor CC, so that the charge Qj accumulated at the terminal of Ci is injected to the receiving terminal of the coupling capacitor CC. As a result, the amount of voltage change at the receiving terminal of the coupling capacitance is the next 81i! While referring to the voltage waveform diagram of J,
The operation of the circuit shown in FIG. 5 will be explained.

First, when the first reference voltage part of signal V12 is input,
Output the control signal YB from the control circuit 25 and switch 3B.
Close. At this time, the control signal Y n *Y J closes the switch SR and opens the switch SJ.

This causes the reference voltage portion of signal 13 to be clamped to a voltage value very close to v8.

Next, xo #X5-1, which indicates the difference voltage between the next reference voltage portion of the signal V12 and the reference voltage level, is the digital adder 24.
is output from. Based on these XO to Xa-+ and the clock signal (CK), the control circuit 25 outputs control signals Ye, YR, YJ and Yo''Ys-1.
is output. First, the switch SR is opened by the control signal Y^, and then the switches So to S■-1 are opened by the control signal Y o
"The connection terminals are switched according to Y m -1. As a result, a charge Q1 is injected through Ci, and the total amount of the charge is accumulated in one terminal of Ct. Then, the control signal Y
J causes the charge to be injected into the receiving terminal of the coupling capacitor CC. Therefore, the voltage of the reference voltage portion of V13 fluctuates and is clamped to a predetermined voltage value.

Note that Sol and SJ are open when a substantial image Φ video portion other than the reference voltage portion of V12 is input. This results in a proper signal clamped to a predetermined voltage value.

As described above, according to the embodiment of the present invention, it is possible to set the clamp voltage with high precision, similar to the circuit shown in FIG.

In particular, according to the embodiment of the present invention, since the voltage close to the clamp voltage v8 is set in advance by the switch SB, the amount of voltage to be adjusted by injecting charge through the storage capacitor C1 is minute, and therefore the speed is extremely high. It is possible to adjust the voltage.

〔Effect of the invention〕

As explained above, since the signal level clamp circuit of the present invention is configured with a feedback loop including a signal processing circuit, it is possible to remove the offset voltage generated from the signal processing circuit from the signal level clamp voltage. can.

Furthermore, since the predetermined reference clamp voltage and the signal voltage are compared digitally, offset voltage generated by the conventional analog comparator itself is not mixed in.

Therefore, in this respect as well, it is possible to set the clamp voltage of the signal level with high precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal level clamp circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of FIG. 1. 3 is a voltage waveform diagram for explaining the operation of the circuit shown in FIG. 2, FIG. 4 is a block diagram of a signal level clamp circuit according to another embodiment of the present invention, and FIG. 5 is a specific example of the circuit shown in FIG. FIG. 6 is a diagram illustrating a latch circuit forming a part of the control circuit shown in FIG. 5; FIG. 7 is a circuit diagram in the case where the changeover switch shown in FIG. 5 is constituted by 0MO5. Figure 8 is a voltage waveform diagram for explaining the operation of the circuit in Figure 5, Figure 9 is a diagram for explaining a conventional signal level clamp circuit, and tjSio diagram is for explaining another conventional signal level clamp circuit. This is a diagram. (Explanation of symbols) 1...Signal processing circuit. 2.8.21...Buffer, 3.5,10,17.22...A/D converter. 4.7, 9.16... Analog adder. 6...S/H circuit. 11.18.24...Digital adder. 12.19... D/A converter, 13.20... Integrator, 14.15... Operational amplifier, 23... Inverter, 25... Control circuit, vt, va, v7. vtz--output signal of signal source, V2, V5, V8, Vl3=clamp signal. V3. V8. V9...Digital output signal, ■1G...
・Analog differential voltage. Vll...Differential voltage divided by a, VB...Voltage of bias power supply. VRI, VB2-...Reference N pressure, CC...Coupling capacitance, C6"Cs-+...Storage capacitance, So, S@, SJ...Open/close switch. S6"5s-1...Terminal Changeover switch, YR*
YJ tyo "'Y#-1"" control signal.

Claims (1)

[Scope of Claims] A comparator that compares a digital amount of voltage output from a signal processing circuit with a digital amount of a predetermined reference voltage and outputs a digital amount corresponding to the voltage difference, and a digital voltage output from the comparator. a D/A converter that converts a quantity into an analog voltage quantity; 1. A signal level clamp circuit comprising: a circuit for clamping the voltage level of an input signal to a predetermined voltage.