JPH08195894A - Picture input device - Google Patents

Abstract

PURPOSE: To provide a picture input device capable of accelerating the response time of a clamping operation itself and substantially suppressing the power consumption of the entire device. CONSTITUTION: A clamping circuit 2 clamps input picture signals corresponding to the blanking period of input picture signals corresponding to a clamping control voltage and an A/D converter 3 A/D converts the output. Then, a digital comparator 5 successively compares an output digital code outputted from the A/D converter 3 with a prescribed digital code corresponding to the blanking period, the compared result is integrated in an integration circuit 7 and integrated output from the integration circuit 7 is fed back as the clamping control voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image input device used in a still video camera or the like and using an A / D converter.

[0002]

2. Description of the Related Art Conventionally, in an image input device using an A / D converter, when the image signal is A / D converted, the input signal is kept within the input range of the A / D converter. It is known to use a digital feedback clamp system having a configuration as shown in FIG.

FIG. 3 is a block diagram showing an example of the configuration of an image input device using a conventional digital feedback clamp system.

In the figure, an analog signal (image signal) Ain input from an input terminal 101 is supplied to an A / D converter 103 as a signal S101 added with a DC voltage through a clamp circuit 102. A / D converter 1
On the other hand, the digital output Dout of 03 is output terminal 10
4 is supplied to the other side, and the digital comparator 105 is supplied to the other side.
Supplied to Further, the digital comparator 105
A reference / digital code Drf is supplied to the input terminal 106 from the input terminal 106. This comparator 1
The output signal S103 of 05 is supplied to the integrator 107, and the output signal S102 is fed back as the clamp control voltage of the clamp circuit 102.

The timing signal S104 is supplied from the timing generator 108 to the digital comparator 105 and the clamp circuit 102. For the integrator 107, for example, a first-order low-pass filter composed of a resistor 107a and a capacitor 107b as shown in FIG. 4 is used.

Next, the clamp operation of the above circuit will be described with reference to the signal waveform diagram shown in FIG.

First, when the power is turned on, since the DC voltage is not yet generated in the clamp circuit 102 at this point, the clamp output signal S101 is at the ground level and converted by the A / D converter 103. The output digital code of the digital value indicates "0". This output digital code Dout is compared with the reference code Drf given from the input terminal 106, and the output digital code Dof is compared with the reference code Drf.
The digital comparator 105 functions so as to give an "H" level (+5 V) if it is smaller, a floating (high impedance) state if it is equal, and an "L" level (0 V) if it is larger.

Therefore, since Dout = 0 when the power is turned on, the output S103 of the digital comparator 105 is "H" for the specific code Drf with Drf> 0.
Output level. In addition, the digital comparator 10
The output S103 of No. 5 is valid only at the clamp timing indicated by the "H" level of the signal S104 in the blanking period in which no image signal exists, and is in the floating state in other periods.

The "H" level output S103 of the digital comparator 105 causes the integrated output S of the integrator 107.
102 increases by that amount, and the clamp output S1
Also in 01, the DC voltage value added by one clamping operation increases.

The DC voltage value added to the clamp output S101 continues to increase at each clamp operation as long as the output S103 of the comparator 105 is at "H" level. Eventually, when the A / D-converted output digital code Dout becomes larger than the reference code Drf input to the digital comparator 105, the output S103 of the comparator 105 reverses to the “L” level, and the integrated value of the integrator 107 becomes As it decreases, it stops increasing.

After that, the digital code Dout repeatedly oscillates up and down around the reference code Drf in the clamp period indicated by the signal S104, and the integrated output S102 maintains the equilibrium state at the specific voltage V102.
As a result, the clamp output S101 is also balanced at the constant DC voltage value V101 during the blanking period, and the A / D conversion value Dout corresponding to the voltage value is also balanced at the reference code Drf.

Due to such a function, the present system has no influence of direct current fluctuation due to the temperature characteristic of the input range of the A / D converter 103, and does not require adjustment of the clamp bias. It can be said that this is a useful method as a D conversion method.

[0013]

However, in the image input device using the digital feedback clamp method, the comparison frequency component is removed from the output S103 of the digital comparator 105 and smoothed to generate the clamp control voltage S102. For the integrator 107
, A time constant equivalent to several tens of one clamp cycle is required.

Therefore, after the power is turned on, the response time required until the image input device is started and the DC voltage value reaches the above-mentioned equilibrium state is long, and during this period, the power consumption of the A / D converter 103, the comparator 105, etc. It is necessary to drive all of the large digital signal processing systems, resulting in an increase in power consumption as compared with a simple pulse clamp circuit.

This is a major obstacle from the viewpoints of continuous use time and increase in internal temperature in system applications such as still video cameras in which images must be input by battery drive.

In view of the above-mentioned conventional problems, it is an object of the present invention to provide an image input device that can shorten the response time of the clamp operation itself and can significantly reduce the power consumption of the entire device.

[0017]

In order to achieve the above-mentioned object, the present invention relates to a blanking period of an input image signal,
A clamp circuit that clamps the input image signal according to a clamp control voltage, an A / D converter connected to the output side of the clamp circuit, an output digital code output from the A / D converter, and a predetermined value. Digital feedback having comparing means for sequentially comparing a digital code according to the blanking period and integrating means for integrating the comparison result of the comparing means, and feeding back the integrated output from the integrating means as the clamp control voltage. In an image input device that performs a clamp-type clamping operation, a constant voltage source is connected to the output side of the integrating means, the constant voltage source is activated before the clamping operation, and the clamp control voltage is set to a predetermined value. It is provided with a control means for setting.

In the above invention, the predetermined value of the clamp control voltage set by starting the constant voltage source is
A value near the balanced DC voltage is desirable.

[0019]

According to the present invention having the above structure, the clamp circuit clamps the input image signal according to the clamp control voltage according to the blanking period of the input image signal, and the A / D converter outputs the output from the A / D converter. Convert. Then, the comparing means successively compares the output digital code output from the A / D converter with a predetermined digital code according to the blanking period, integrates the comparison result by the integrating means, and outputs the integrated output from the integrating means. Is fed back as the clamp control voltage.

According to the present invention, prior to such an original clamp operation, the clamp control voltage which is the output of the integrating means is set near the balanced DC voltage by the constant voltage source, so that the response time of the clamp operation itself is accelerated. be able to.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an image input apparatus according to the present invention.

This image input device differs from the conventional device shown in FIG. 3 in that a constant voltage source 9 is connected to the output side of an integrator 7 corresponding to the integrator 107 in FIG. 3 via a resistor 8 in series. That is what I did.

That is, in FIG. 1, the analog signal (image signal) Ain input from the input terminal 1 is input to the clamp circuit 2, and the clamp output S1 to which the DC voltage is added from the clamp circuit 2 is A / It is supplied to the D converter 3. The digital output Dout of the A / D converter 3 is
On the one hand, it is supplied from the output terminal 4 to a digital signal processing circuit (not shown), an image memory, etc., and on the other hand, it is supplied to the negative input side of the digital comparator 5.

The reference code Drf is supplied from the input terminal 6 to the positive input side of the comparator 5. The output signal S3 of the comparator 5 is supplied to the integrator 7, and the smoothed output signal S2 from the integrator 7 is fed back as the clamp control voltage of the clamp circuit 2.

The timing signal S4 for performing the comparison operation of the comparator 5 and the clamp operation of the clamp circuit 2 is
It is supplied from the timing generator 8.

The integrator 7 is composed of, for example, a primary low-pass filter composed of a resistor 7a and a capacitor 7b.

Next, the clamp operation of the image input apparatus of this embodiment will be described in detail with reference to the signal waveform diagram shown in FIG.

First, the constant voltage source 9 is activated by a start switch (not shown) prior to the power supply to the entire circuit of FIG. 1 (S5 in FIG. 2: activation timing waveform of the constant voltage source 9). Then, the output of the constant voltage source 9 charges the capacitor 7b at the output stage of the integrator 7 via the resistor 8. The output voltage of the constant voltage source 9 is the control voltage value V when the output S2 of the integrator 7 is clamp balanced as described in the conventional example.
It is set in advance to be in the vicinity V2 of 2.

The output S of the digital comparator 5
No. 3 is in the floating state when the power is not supplied. Therefore, the output S2 of the integrator 7 converges on the voltage V3 of the constant voltage source 9 according to the time constant represented by the product of the resistance value of the resistor 8 and the capacitance value of the capacitor 7b.

Thereafter, the system controller (not shown) powers on the entire circuit of FIG. 1, and the timing signal S4 becomes "H" level every blanking period of the input video signal, as in the conventional example. Only during this period, the output S3 of the digital comparator 5 becomes valid and the clamp operation is started.

The resistance value of the resistor 7a is different from the resistance value of the resistor 7a.
If the resistance value of is selected large enough,
The influence of the current flowing in and out by the constant voltage source 9 can be ignored.

The subsequent clamping operation itself is exactly the same as that described in the conventional example, but in this embodiment, the signal S2 has already been set to the voltage V3 near the clamp balanced voltage V2, so that The response time of the clamp circuit is not | V2-V as shown in the conventional example, but | V2-V
3 |, which results in a significant reduction in the selection of voltage V3.

In the present embodiment, the operation of one image input is described, but if the present invention is used, for example, when a plurality of images are input within a fixed time, the response time is further shortened and power consumption is reduced. Can be suppressed. That is, even after the first image input operation is completed and the power supplied to the entire circuit shown in FIG. 1 is turned off, only the constant voltage source 9 is kept active and the voltage value of the integrated output S2 is maintained. Thus, the response time of the second image input is shortened.

[0035]

As described in detail above, according to the present invention, a clamp circuit that clamps an input image signal according to a clamp control voltage according to a blanking period of the input image signal, and an output of the clamp circuit. A / connected to the side
A D converter, a comparing means for sequentially comparing the output digital code output from the A / D converter and a predetermined digital code according to the blanking period, and an integrating means for integrating the comparison result of the comparing means. In an image input device for performing a clamp operation of a digital feedback clamp system for feeding back an integrated output from the integrating means as the clamp control voltage, a constant voltage source is connected to an output side of the integrating means, and the clamp is provided. Since the constant voltage source is started before the operation and the control means for setting the clamp control voltage to a predetermined value is provided, the response time of the clamp operation itself can be shortened, and the power consumption of the entire device is significantly reduced. It becomes possible to suppress.

Further, in the above invention, the above-mentioned effect becomes more remarkable by setting the predetermined value of the clamp control voltage set by the activation of the constant voltage source in the vicinity of the balanced DC voltage.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of an image input apparatus according to the present invention.

FIG. 2 is a signal waveform diagram of the present embodiment.

FIG. 3 is a block diagram showing a configuration example of an image input device using a conventional digital feedback clamp method.

FIG. 4 is a circuit diagram showing a configuration of an integrator in FIG.

5 is a signal waveform diagram of the image input device shown in FIG.

[Explanation of symbols]

 2 Clamp circuit 3 A / D converter 5 Digital comparator 7 Integrator 8 Timing generator

Claims (2)

[Claims] 1. A clamp circuit for clamping the input image signal according to a clamp control voltage according to a blanking period of the input image signal, an A / D converter connected to an output side of the clamp circuit, and the A / D converter. The digital signal output from the D / D converter and a predetermined digital code are sequentially compared in accordance with the blanking period, and comparison means is provided, and addition means for adding up the comparison results of the comparison means is provided. In an image input device that performs a clamp operation of a digital feedback clamp system that feeds back the integrated output of the above as the clamp control voltage, a constant voltage source is connected to the output side of the integrating means, and the constant voltage source is connected before the clamp operation. Start the voltage source,
An image input device comprising a control means for setting the clamp control voltage to a predetermined value. 2. The image input device according to claim 1, wherein the predetermined value of the clamp control voltage set by starting the constant voltage source is a value near a balanced DC voltage.