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JP2828021B2 - ベアチップ実装構造及び製造方法 - Google Patents

ベアチップ実装構造及び製造方法

Info

Publication number
JP2828021B2
JP2828021B2 JP8099738A JP9973896A JP2828021B2 JP 2828021 B2 JP2828021 B2 JP 2828021B2 JP 8099738 A JP8099738 A JP 8099738A JP 9973896 A JP9973896 A JP 9973896A JP 2828021 B2 JP2828021 B2 JP 2828021B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
resin
substrate
corners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8099738A
Other languages
English (en)
Other versions
JPH09289221A (ja
Inventor
健市 得能
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP8099738A priority Critical patent/JP2828021B2/ja
Priority to US08/837,801 priority patent/US5892289A/en
Publication of JPH09289221A publication Critical patent/JPH09289221A/ja
Application granted granted Critical
Publication of JP2828021B2 publication Critical patent/JP2828021B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/13111—Tin [Sn] as principal constituent
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体チップのベ
アチップ実装構造及び製造方法に関し、特にフリップチ
ップ実装の樹脂封止技術に関する。
【０００２】
【従来の技術】従来のフリップチップの樹脂封止技術を
図３に示す。（ａ）はフリップチップ実装の製造工程を
示し、（ｂ）はその形態を示す平面図である。まず、製
造工程については、（ａ）に示すように、基板２上にフ
リップチップ実装した半導体チップ１の１辺近傍に液状
封止樹脂５を塗布し、半導体チップ１と基板２との間隙
に毛細管現象を利用して封止樹脂５を流し込む。流し込
み完了後、封止樹脂５を加熱硬化させる。
【０００３】また、特開昭６３−２４１９５５号公報や
特開平１−１９１４５７号公報に示されるように、基板
の半導体チップ搭載部に貫通穴を設け、この貫通穴から
封止樹脂を注入する技術がある。
【０００４】
【発明が解決しようとする課題】従来の第１の問題点
は、従来の技術において、半導体チップが大きい場合に
封止時間が長くなることである。その理由は、半導体チ
ップの１辺からの封止樹脂の流し込みでは、樹脂を流す
距離が長いためである。また、封止樹脂を一度に供給す
ることができないため、樹脂を時分割供給するためであ
る。
【０００５】第２の問題点は、従来の技術において、基
板が反った場合および半導体チップと基板との熱膨張係
数差に基づく応力が半導体チップの隅部のバンプ接続部
に集中し接続信頼性が低い。その理由は、フリップチッ
プ実装された半導体チップの隅部の封止樹脂フィレット
が小さく基板反りおよび熱膨張係数差に基づく応力の緩
和が不十分であるためである。
【０００６】従って、本発明の目的は、フリップチップ
実装の樹脂封止において半導体チップの４隅から樹脂を
流し込むことで封止時間を短縮し、生産性を向上させる
ことができるベアチップ製造方法を提供することであ
る。
【０００７】本発明の他の目的は、半導体チップの隅部
の樹脂フィレットを大きな構造とすることにより、基板
反りおよび熱サイクル時に半導体チップの隅のバンプ接
続部に集中する応力を緩和し、接続信頼性を向上させる
ことができるベアチップ実装構造を提供することであ
る。
【０００８】
【課題を解決するための手段】本発明によれば、フリッ
プチップの樹脂封止において、半導体チップの４隅近傍
に封止樹脂をポッティングし、毛細管現象を利用して半
導体チップと基板との間隙に流し込むベアチップ製造方
法が得られる。
【０００９】また本発明によれば、半導体チップの隅部
の封止樹脂フィレットが大きいベアチップ実装構造が得
られる。
【００１０】本発明においては、フリップチップ実装さ
れた半導体チップの４隅から樹脂を流し込むため、流し
込む距離が短くなり、かつ封止樹脂を４分割し同時供給
することができるため、封止時間が短縮できる。
【００１１】また本発明においては、封止樹脂を半導体
チップの４隅近傍に供給するために半導体チップの４隅
のフィレットが大きくなり、半導体チップ隅のバンプ接
続部に集中する応力を緩和できる。
【００１２】
【発明の実施の形態】次に本発明の実施の形態について
図１を参照して詳細に説明する。図１で（ａ）はフリッ
プチップの実装における構造を示す平面図、（ｂ）は断
面図である。図１を参照すると、本発明の最良の実施の
形態は、半導体チップ１の電極パッド上に形成したバン
プ３を基板２の搭載パッド４に接続したフリップチップ
実装において、半導体チップ１の４隅から封止樹脂５を
流し込むことにより、（ｂ）に示すように半導体チップ
１の４隅の樹脂フィレットを大きくした形態である。
【００１３】次に、本発明の動作について、図２の
（ａ）〜（ｃ）を参照して説明する。まず、（ａ）に示
すように基板２上にフリップチップ実装した半導体チッ
プ１の４隅近傍に封止樹脂５をポッティングする。する
と（ｂ）に示すように、封止樹脂５は毛細管現象により
半導体チップ１と基板２との間隙に流れ込む。本発明に
おいて、封止樹脂５を４分割して同時に流し込むこと、
および流し込み距離が短くなることにより、封止時間を
短縮することができる。更に、（ｃ）に示すように封止
完了時の樹脂封止形態は半導体チップ１の４隅の樹脂フ
ィレットが大きな構造となっており、基板の反り、また
は、熱サイクル試験時に半導体チップ１の４隅近傍のバ
ンプ接続部に生じる応力集中を緩和することができ、バ
ンプ接続部の接続信頼性が向上する。
【００１４】
【実施例】次に、本発明の実施例について図面を参照し
て詳細に説明する。図１の（ａ）（ｂ）を参照すると、
本発明の実施例は、半導体チップ１のアルミ電極パッド
上に形成されたφ８０μｍ、高さ４０μｍの金ボールバ
ンプ３と０．５ｍｍ厚のガラスエポキシ基板２上に形成
した搭載パッド４とを、Ａｇ−Ｓｎ系はんだ材料で接続
した後、半導体チップ１と、ガラスエポキシ基板との間
隙を一液性エポキシ樹脂５で封止する。
【００１５】樹脂封止は一液性エポキシ樹脂５を半導体
チップ１の４隅近傍にポッティングするために、樹脂封
止後の樹脂フィレットは半導体チップ１の４隅が４辺部
分よりも大きな丸形の形状となる。半導体チップ１の４
隅の大きな樹脂フィレットは、基板１が機械的に反った
場合または熱サイクルテスト時に、半導体チップ１とガ
ラスエポキシ基板２との熱膨張率差に基づき、半導体チ
ップ１の４隅部のバンプ３接続部に集中する応力を緩和
することができ、バンプ３接続部の接続信頼性を向上で
きる。
【００１６】次に、本発明の実施例の動作について説明
する。図２の（ａ）を参照すると、ガラスエポキシ基板
１上にフリップチップ実装された半導体チップ１の４隅
の半導体チップの対角線延長線上の半導体チップの隅か
ら０．５ｍｍの基板上に樹脂の一部が半導体チップ１に
接するように一液性のエポキシ封止樹脂５をポッティン
グする。エポキシ封止樹脂５は、毛細管現象により半導
体チップ１の４隅から半導体チップ１とガラスエポキシ
基板２との間隙４０μｍに流れ込む。封止樹脂５を半導
体チップ１の４隅から流すことにより、半導体チップ１
の１辺から流し込む場合と比較して封止樹脂５を流し込
む距離が短くなる。更に、封止樹脂５を４分割し、同時
に流し込むことにより封止時間を短縮することができ
る。
【００１７】次に、本発明の他の実施の形態について説
明する。基板２の材料はガラスエポキシだけではなく、
アルミナ、ガラスセラミックス、ポリイミドでも適用可
能である。また半導体チップ１と基板２との接続構造と
しては半導体チップ１のアルミ電極に形成したＡｕボー
ルバンプをＡｇ−Ｓｎ系はんだで接続するだけでなく、
Ａｕボールバンプを直接基板２の搭載パッド４上に加熱
圧着した接続構造、または、バンプ３の材料としてＰｂ
−Ｓｎ系はんだまたはインジウム系はんだによって接続
する構造も適用可能である。半導体チップの４隅のフィ
レットが半導体チップの側面だけでなく半導体チップの
上面の一部を覆う構造も適用可能である。
【００１８】
【発明の効果】本発明の第１の効果は、基板の反りまた
は熱サイクル試験時における半導体チップ４隅部のバン
プ接続部の接続信頼性を向上するということである。こ
れによりフリップチップ実装の信頼性が向上できるよう
になる。その理由は、応力の集中する半導体チップ４隅
部の樹脂フィレットが大きくバンプ接続部に生じる応力
を緩和できるからである。
【００１９】第２の効果は、封止樹脂を半導体チップと
基板間に短時間で流し込めるということである。これに
よりフリップチップ実装の製造時間を短縮できるように
なる。その理由は、封止樹脂を半導体チップの４隅から
流し込むことにより１辺から流し込む場合と比較して流
し込む距離が短くなることおよび封止樹脂を４分割して
同時に流し込むことができるからである。
【図面の簡単な説明】
【図１】本発明のフリップチップ実装の一実施の形態を
示す図で、（ａ）は平面図、（ｂ）は断面図である。
【図２】本発明のフリップチップ実装の一実施の製造を
示す平面図であり、（ａ）〜（ｃ）はその工程を示す。
【図３】従来のフリップチップ実装を示す図で、（ａ）
は製造工程を示す平面図、（ｂ）は形態を示す平面図で
ある。
【符号の説明】
１ 半導体チップ ２ 基板 ３ バンプ ４ 搭載パッド ５ 封止樹脂 ６ 封止樹脂の流れる方向
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/56 H01L 21/60 311

Claims (6)

    (57)【特許請求の範囲】
  1. 【請求項１】 基板にフリップチップ実装した半導体チ
    ップの４隅の樹脂フィレットが半導体チップ辺部の樹脂
    フィレットより大きいベアチップ実装構造。
  2. 【請求項２】 基板にフリップチップ実装した半導体チ
    ップの４隅から半導体チップと基板との間隙に封止樹脂
    を流し込むベアチップ実装構造の製造方法。
  3. 【請求項３】 半導体チップの対角線延長線上の半導体
    チップの隅から０．５ｍｍの基板上に封止樹脂をポッテ
    ィングする請求項２のベアチップ実装構造の製造方法。
  4. 【請求項４】 半導体チップの４隅のフィレットの外周
    が丸い請求項１のベアチップ実装構造。
  5. 【請求項５】 半導体チップの辺部のフィレットの上端
    が半導体チップ側面の下端から上端までに存在する請求
    項１のベアチップ実装構造。
  6. 【請求項６】 半導体チップの４隅のフィレットがチッ
    プの上面の一部を覆っている請求項１のベアチップ実装
    構造。
JP8099738A 1996-04-22 1996-04-22 ベアチップ実装構造及び製造方法 Expired - Fee Related JP2828021B2 (ja)

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US08/837,801 US5892289A (en) 1996-04-22 1997-04-22 Bare chip mounting structure and manufacturing method therefor

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