DE3575225D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number: DE3575225D1
Authority: DE; Germany
Prior art keywords: semiconductor memory; memory arrangement; arrangement; semiconductor; memory
Prior art date: 1984-05-30
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8585303810T

Other languages

English (en)

Inventor

Keizo Aoyama

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Ltd

Original Assignee

Fujitsu Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-05-30

Filing date

1985-05-30

Publication date

1990-02-08

1985-05-30 Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd

1990-02-08 Application granted granted Critical

1990-02-08 Publication of DE3575225D1 publication Critical patent/DE3575225D1/de

2005-05-31 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- H01L27/00—
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Condensed Matter Physics & Semiconductors (AREA)
General Physics & Mathematics (AREA)
Power Engineering (AREA)
Static Random-Access Memory (AREA)

DE8585303810T 1984-05-30 1985-05-30 Halbleiterspeicheranordnung. Expired - Fee Related DE3575225D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP59110291A JPS60253093A (ja)	1984-05-30	1984-05-30	半導体記憶装置

Publications (1)

Publication Number	Publication Date
DE3575225D1 true DE3575225D1 (de)	1990-02-08

Family

ID=14531968

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8585303810T Expired - Fee Related DE3575225D1 (de)	1984-05-30	1985-05-30	Halbleiterspeicheranordnung.

Country Status (5)

Country	Link
US (1)	US4656608A (de)
EP (1)	EP0166540B1 (de)
JP (1)	JPS60253093A (de)
KR (1)	KR900004345B1 (de)
DE (1)	DE3575225D1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4800552A (en) *	1985-12-18	1989-01-24	Fujitsu Limited	Semiconductor memory device with reset signal generating circuit
JPS6342090A (ja) *	1986-08-07	1988-02-23	Fujitsu Ltd	ユニバーサルジョイント
US4785427A (en) *	1987-01-28	1988-11-15	Cypress Semiconductor Corporation	Differential bit line clamp
KR910003605B1 (ko) *	1988-04-30	1991-06-07	삼성전자 주식회사	Sram 센스앰프의 등화회로
US5046052A (en) *	1988-06-01	1991-09-03	Sony Corporation	Internal low voltage transformation circuit of static random access memory
US5237534A (en) *	1989-04-27	1993-08-17	Kabushiki Kaisha Toshiba	Data sense circuit for a semiconductor nonvolatile memory device
KR920001081B1 (ko) *	1989-06-10	1992-02-01	삼성전자 주식회사	램 테스트시 고속기록회로
JP2963504B2 (ja) *	1990-07-23	1999-10-18	沖電気工業株式会社	半導体記憶装置
US5155702A (en) *	1990-11-30	1992-10-13	Samsung Electronics Co., Ltd.	Semiconductor memory device
KR970011971B1 (ko) *	1992-03-30	1997-08-08	삼성전자 주식회사	반도체 메모리 장치의 비트라인 프리차아지회로
US5268863A (en) *	1992-07-06	1993-12-07	Motorola, Inc.	Memory having a write enable controlled word line
US5508964A (en) *	1993-01-08	1996-04-16	Texas Instruments Incorporated	Write recovery time minimization for Bi-CMOS SRAM
JP3178946B2 (ja) *	1993-08-31	2001-06-25	沖電気工業株式会社	半導体記憶装置及びその駆動方法
US6058041A (en) *	1998-12-23	2000-05-02	Honeywell Inc.	SEU hardening circuit
US6928012B2 (en) *	2002-09-27	2005-08-09	Infineon Technologies Ag	Bitline equalization system for a DRAM integrated circuit
KR100555534B1 (ko) *	2003-12-03	2006-03-03	삼성전자주식회사	인액티브 위크 프리차아징 및 이퀄라이징 스킴을 채용한프리차아지 회로, 이를 포함하는 메모리 장치 및 그프리차아지 방법
US7888962B1 (en)	2004-07-07	2011-02-15	Cypress Semiconductor Corporation	Impedance matching circuit
KR100649351B1 (ko) *	2005-03-31	2006-11-27	주식회사 하이닉스반도체	저전압용 반도체 메모리 장치
US8036846B1 (en)	2005-10-20	2011-10-11	Cypress Semiconductor Corporation	Variable impedance sense architecture and method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4003035A (en) *	1975-07-03	1977-01-11	Motorola, Inc.	Complementary field effect transistor sense amplifier for one transistor per bit ram cell
JPS5827915B2 (ja) *	1978-07-28	1983-06-13	富士通株式会社	リセット回路
JPS5619587A (en) *	1979-07-27	1981-02-24	Nec Corp	Memory circuit
JPS6027113B2 (ja) *	1980-02-13	1985-06-27	日本電気株式会社	プリチャ−ジ装置
US4355377A (en) *	1980-06-30	1982-10-19	Inmos Corporation	Asynchronously equillibrated and pre-charged static ram
JPS6051194B2 (ja) *	1981-03-12	1985-11-12	富士通株式会社	非同期型スタティックメモリ
JPS57203334A (en) *	1981-06-08	1982-12-13	Mitsubishi Electric Corp	Semiconductor integrated circuit device
JPS58196693A (ja) *	1982-05-12	1983-11-16	Mitsubishi Electric Corp	半導体集積回路
JPS60154393A (ja) *	1984-01-24	1985-08-14	Seiko Epson Corp	半導体記憶装置

1984
- 1984-05-30 JP JP59110291A patent/JPS60253093A/ja active Granted
1985
- 1985-05-22 KR KR8503522A patent/KR900004345B1/ko not_active IP Right Cessation
- 1985-05-23 US US06/737,076 patent/US4656608A/en not_active Expired - Lifetime
- 1985-05-30 EP EP85303810A patent/EP0166540B1/de not_active Expired - Lifetime
- 1985-05-30 DE DE8585303810T patent/DE3575225D1/de not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP0166540B1 (de)	1990-01-03
EP0166540A2 (de)	1986-01-02
EP0166540A3 (en)	1987-08-19
JPH0456399B2 (de)	1992-09-08
US4656608A (en)	1987-04-07
JPS60253093A (ja)	1985-12-13
KR850008563A (ko)	1985-12-18
KR900004345B1 (en)	1990-06-22

Publication	Publication Date	Title
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3481957D1 (de)	1990-05-17	Halbleiteranordnung.
DE3686994D1 (de)	1992-11-26	Halbleiterspeicher.
DE3687322D1 (de)	1993-02-04	Halbleiterspeicheranordnung.
DE3485174D1 (de)	1991-11-21	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3485625D1 (de)	1992-05-07	Halbleiterspeicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3484180D1 (de)	1991-04-04	Halbleiterspeicheranordnung.
DE3582653D1 (de)	1991-05-29	Halbleiteranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3481355D1 (de)	1990-03-15	Halbleiterspeicheranordnung.
DE3675445D1 (de)	1990-12-13	Halbleiterspeicheranordnung.
DE3680562D1 (de)	1991-09-05	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.
DE3586675D1 (de)	1992-10-29	Halbleiterspeicheranordnung.
DE3486094D1 (de)	1993-04-15	Halbleiterspeicheranordnung.

Legal Events

Date	Code	Title	Description
1991-01-24	8364	No opposition during term of opposition
2005-03-17	8339	Ceased/non-payment of the annual fee