DE3582376D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number: DE3582376D1
Authority: DE; Germany
Prior art keywords: semiconductor memory; memory arrangement; arrangement; semiconductor; memory
Prior art date: 1984-08-03
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE8585109699T

Other languages

English (en)

Inventor

Takayasu C O Patent Di Sakurai

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Toshiba Corp

Original Assignee

Toshiba Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-08-03

Filing date

1985-08-02

Publication date

1991-05-08

1984-08-03 Priority claimed from JP59163508A external-priority patent/JPS6142794A/ja

1985-06-19 Priority claimed from JP60133420A external-priority patent/JPS61292292A/ja

1985-08-02 Application filed by Toshiba Corp filed Critical Toshiba Corp

1991-05-08 Application granted granted Critical

1991-05-08 Publication of DE3582376D1 publication Critical patent/DE3582376D1/de

2005-08-03 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

Engineering & Computer Science (AREA)
Microelectronics & Electronic Packaging (AREA)
Computer Hardware Design (AREA)
Databases & Information Systems (AREA)
Dram (AREA)

DE8585109699T 1984-08-03 1985-08-02 Halbleiterspeicheranordnung. Expired - Lifetime DE3582376D1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
JP59163508A JPS6142794A (ja)	1984-08-03	1984-08-03	半導体記憶装置のセンスアンプ系
JP60133420A JPS61292292A (ja)	1985-06-19	1985-06-19	半導体記憶装置

Publications (1)

Publication Number	Publication Date
DE3582376D1 true DE3582376D1 (de)	1991-05-08

Family

ID=26467790

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8585109699T Expired - Lifetime DE3582376D1 (de)	1984-08-03	1985-08-02	Halbleiterspeicheranordnung.

Country Status (3)

Country	Link
US (1)	US4764901A (de)
EP (1)	EP0170285B1 (de)
DE (1)	DE3582376D1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4864544A (en) *	1986-03-12	1989-09-05	Advanced Micro Devices, Inc.	A Ram cell having means for controlling a bidirectional shift
JPS63155494A (ja) *	1986-12-19	1988-06-28	Fujitsu Ltd	擬似スタテイツクメモリ装置
US4980863A (en) *	1987-03-31	1990-12-25	Kabushiki Kaisha Toshiba	Semiconductor memory device having switching circuit for coupling together two pairs of bit lines
JPH0793002B2 (ja) *	1987-06-04	1995-10-09	日本電気株式会社	メモリ集積回路
JPH0690873B2 (ja) *	1987-10-28	1994-11-14	三菱電機株式会社	半導体記憶装置の書き込み方法
JPH07107793B2 (ja) *	1987-11-10	1995-11-15	株式会社東芝	仮想型スタティック半導体記憶装置及びこの記憶装置を用いたシステム
JP2501344B2 (ja) *	1987-12-26	1996-05-29	株式会社東芝	デ―タ転送回路
US4926384A (en) *	1988-01-25	1990-05-15	Visic, Incorporated	Static ram with write recovery in selected portion of memory array
US4878198A (en) *	1988-01-25	1989-10-31	Visic, Incorporated	Static ram with common data line equalization
EP0329910B1 (de) *	1988-02-26	1991-05-29	International Business Machines Corporation	Zweistufiger Leserverstärker für RAM-Speicher
US5034917A (en) *	1988-05-26	1991-07-23	Bland Patrick M	Computer system including a page mode memory with decreased access time and method of operation thereof
KR910008101B1 (ko) *	1988-12-30	1991-10-07	삼성전자 주식회사	반도체 메모리 소자의 피드백형 데이타 출력 회로
US5134616A (en) *	1990-02-13	1992-07-28	International Business Machines Corporation	Dynamic ram with on-chip ecc and optimized bit and word redundancy
DE69122293T2 (de) *	1990-04-27	1997-04-24	Nippon Electric Co	Halbleiterspeicheranordnung
US5325335A (en) *	1991-05-30	1994-06-28	Integrated Device Technology, Inc.	Memories and amplifiers suitable for low voltage power supplies
US5304874A (en) *	1991-05-31	1994-04-19	Thunderbird Technologies, Inc.	Differential latching inverter and random access memory using same
US5305269A (en) *	1991-05-31	1994-04-19	Thunderbird Technologies, Inc.	Differential latching inverter and random access memory using same
US5357477A (en) *	1992-05-18	1994-10-18	Matsushita Electric Industrial Co., Ltd.	Semiconductor memory having multiple data I/O with bit aligned access function
US5689454A (en) *	1996-01-11	1997-11-18	Cyrix Corporation	Circuitry and methodology for pulse capture
DE59606849D1 (de) *	1996-06-04	2001-06-07	Infineon Technologies Ag	Verfahren zum Lesen und Auffrischen eines dynamischen Halbleiterspeichers
US6167486A (en) *	1996-11-18	2000-12-26	Nec Electronics, Inc.	Parallel access virtual channel memory system with cacheable channels
US6708254B2 (en)	1999-11-10	2004-03-16	Nec Electronics America, Inc.	Parallel access virtual channel memory system
US6573775B2 (en)	2001-10-30	2003-06-03	Integrated Device Technology, Inc.	Integrated circuit flip-flops that utilize master and slave latched sense amplifiers
US6700425B1 (en)	2001-10-30	2004-03-02	Integrated Device Technology, Inc.	Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times
US7082049B2 (en) *	2004-11-19	2006-07-25	Infineon Technologies North America Corp.	Random access memory having fast column access

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS51113545A (en) *	1975-03-31	1976-10-06	Hitachi Ltd	Memory
US4131951A (en) *	1976-05-17	1978-12-26	Tokyo Shibaura Electric Co., Ltd.	High speed complementary MOS memory
US4106109A (en) *	1977-02-01	1978-08-08	Ncr Corporation	Random access memory system providing high-speed digital data output
JPS55150179A (en) *	1979-05-04	1980-11-21	Fujitsu Ltd	Semiconductor memory unit
US4330852A (en) *	1979-11-23	1982-05-18	Texas Instruments Incorporated	Semiconductor read/write memory array having serial access
JPS59915B2 (ja) *	1979-11-29	1984-01-09	富士通株式会社	メモリ回路
JPS5951075B2 (ja) *	1980-03-31	1984-12-12	富士通株式会社	半導体記憶装置
JPS5766587A (en) *	1980-10-09	1982-04-22	Fujitsu Ltd	Static semiconductor storage device
US4551641A (en) *	1983-11-23	1985-11-05	Motorola, Inc.	Sense amplifier
US4542483A (en) *	1983-12-02	1985-09-17	At&T Bell Laboratories	Dual stage sense amplifier for dynamic random access memory

1985
- 1985-08-02 US US06/761,709 patent/US4764901A/en not_active Expired - Lifetime
- 1985-08-02 DE DE8585109699T patent/DE3582376D1/de not_active Expired - Lifetime
- 1985-08-02 EP EP85109699A patent/EP0170285B1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
EP0170285A3 (en)	1987-09-02
US4764901A (en)	1988-08-16
EP0170285B1 (de)	1991-04-03
EP0170285A2 (de)	1986-02-05

Publication	Publication Date	Title
DE3585711D1 (de)	1992-04-30	Halbleiterspeicheranordnung.
DE3583091D1 (de)	1991-07-11	Halbleiterspeicheranordnung.
DE3577944D1 (de)	1990-06-28	Halbleiterspeicheranordnung.
DE3481957D1 (de)	1990-05-17	Halbleiteranordnung.
DE3686994D1 (de)	1992-11-26	Halbleiterspeicher.
DE3687322D1 (de)	1993-02-04	Halbleiterspeicheranordnung.
DE3485174D1 (de)	1991-11-21	Halbleiterspeicheranordnung.
DE3582376D1 (de)	1991-05-08	Halbleiterspeicheranordnung.
DE3485625D1 (de)	1992-05-07	Halbleiterspeicheranordnung.
DE3586377D1 (de)	1992-08-27	Halbleiterspeicheranordnung.
DE3576236D1 (de)	1990-04-05	Halbleiterspeicheranordnung.
DE3484180D1 (de)	1991-04-04	Halbleiterspeicheranordnung.
DE3582653D1 (de)	1991-05-29	Halbleiteranordnung.
DE3577367D1 (de)	1990-05-31	Halbleiterspeicheranordnung.
DE3481355D1 (de)	1990-03-15	Halbleiterspeicheranordnung.
DE3675445D1 (de)	1990-12-13	Halbleiterspeicheranordnung.
DE3680562D1 (de)	1991-09-05	Halbleiterspeicheranordnung.
DE3575225D1 (de)	1990-02-08	Halbleiterspeicheranordnung.
DE3586556D1 (de)	1992-10-01	Halbleiterspeicheranordnung.
DE3580993D1 (de)	1991-02-07	Halbleiterspeicheranordnung.
DE3576754D1 (de)	1990-04-26	Halbleiterspeicheranordnung.
DE3582960D1 (de)	1991-07-04	Halbleiterspeicheranordnung.
DE3586675D1 (de)	1992-10-29	Halbleiterspeicheranordnung.
DE3578254D1 (de)	1990-07-19	Halbleiterspeicheranordnung.
DE3486094D1 (de)	1993-04-15	Halbleiterspeicheranordnung.

Legal Events

Date	Code	Title	Description
1992-04-30	8364	No opposition during term of opposition
1999-08-19	8320	Willingness to grant licences declared (paragraph 23)