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CN110660754A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

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Publication number
CN110660754A
CN110660754A CN201910571456.6A CN201910571456A CN110660754A CN 110660754 A CN110660754 A CN 110660754A CN 201910571456 A CN201910571456 A CN 201910571456A CN 110660754 A CN110660754 A CN 110660754A
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CN
China
Prior art keywords
semiconductor die
thermally conductive
semiconductor
encapsulant
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910571456.6A
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English (en)
Other versions
CN110660754B (zh
Inventor
林俊成
卢思维
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110660754A publication Critical patent/CN110660754A/zh
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Publication of CN110660754B publication Critical patent/CN110660754B/zh
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Abstract

提供了半导体封装件。半导体封装件中的一个包括半导体管芯、导热图案、密封剂和导热层。导热图案设置在半导体管芯旁边。密封剂密封半导体管芯和导热图案。导热层覆盖半导体管芯的后表面，其中，导热图案通过导热层热耦合至半导体管芯并且与半导体管芯电绝缘。

Description

半导体封装件
技术领域
本申请的实施例涉及半导体封装件。
背景技术
在集成电路的封装中，半导体管芯可以通过模塑料封装，并且可以接合至其它封装组件，诸如中介层和封装衬底。散热是半导体封装中的挑战。在有效地消散半导体封装件的内部管芯中产生的热量方面存在瓶颈。
发明内容
本申请的实施例提供了一种半导体封装件，包括：半导体管芯；导热图案，位于所述半导体管芯旁边；密封剂，密封所述半导体管芯和所述导热图案；以及导热层，覆盖所述半导体管芯的后表面，其中，所述导热图案通过所述导热层热耦合至所述半导体管芯并且与所述半导体管芯电绝缘。
本申请的另一实施例提供了一种半导体封装件，包括：半导体管芯；密封剂，横向密封所述半导体管芯；第一通孔，嵌入在所述密封剂中并且电连接至所述半导体管芯；第二通孔，嵌入在所述密封剂中并且与所述半导体管芯电绝缘；以及导热层，覆盖所述半导体管芯，其中，所述第二通孔通过所述导热层热耦合至所述半导体管芯。
本申请的又一实施例提供了一种半导体封装件，包括：半导体管芯；密封剂，横向密封所述半导体管芯；第一通孔，嵌入在所述密封剂中并且电连接至所述半导体管芯；第二通孔，嵌入在所述密封剂中并且与所述半导体管芯电绝缘；以及导热层，覆盖所述半导体管芯和所述密封剂，其中，所述导热层包括覆盖所述半导体管芯的第一部分和覆盖所述第二通孔的第二部分，并且所述导热层的第一部分比所述导热层的第二部分厚。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的示出形成半导体封装件的方法的工艺步骤的示例性流程图。
图2A至图2I是根据一些实施例的形成半导体封装件的方法的截面图。
图3是图2I的简化顶视图。
图4是根据一些实施例的半导体封装件的简化顶视图。
图5是根据一些实施例的半导体封装件的简化顶视图。
图6是根据一些实施例的半导体封装件的简化顶视图。
图7是根据一些实施例的半导体封装件的简化顶视图。
图8是根据一些实施例的半导体封装件的简化顶视图。
图9是根据一些实施例的示出半导体封装件的示意性截面图。
图10是根据一些实施例的示出半导体封装件的示意性截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参照标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
此外，为了便于描述，本文可以使用诸如“第一”、“第二”、“第三”、“第四”等术语，以描述附图中示出的类似或不同的元件或部件，并且可以根据出现的顺序或描述的上下文互换使用。
也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布电路结构中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以在中间结构以及最终结构上实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以提高良率和降低成本。
图1是根据一些实施例的示出形成半导体封装件的方法的工艺步骤的示例性流程图。图2A至图2I是根据一些实施例的形成半导体封装件的方法的截面图。图3是图2I的简化顶视图。为了简单和清楚的说明，在图3的简化顶视图中仅示出了诸如半导体管芯、通孔、导热图案和导热层的少量元件。
参照图1和图2A，在步骤S10中，提供其上涂覆有缓冲层104的载体102。在一些实施例中，载体102可以是玻璃载体或用于承载半导体晶圆的任何合适的载体或用于半导体封装件的制造方法的重构晶圆。在一些实施例中，缓冲层104包括脱粘层，并且脱粘层的材料可以是适合于将载体102与上面的层或设置在其上的晶圆接合和脱粘的任何材料。在一些实施例中，缓冲层104包括例如光热转换(“LTHC”)层，并且这种层能够通过施加激光照射从载体脱粘。在一些实施例中，缓冲层104还可以包括位于脱粘层和载体102之间的介电层，并且介电层由包括苯并环丁烯(“BCB”)、聚苯并恶唑(“PBO”)或任何其它合适的聚合物基介电材料的介电材料制成。
在步骤S20中，在缓冲层104上方形成通孔106a、106b和导热图案108。在一些实施例中，例如，在缓冲层104上形成多个通孔106a、106b以围绕用于半导体管芯的区域。在一些实施例中，如图3所示，通孔106a、106b可以沿着围绕半导体管芯的区域的至少一个环形路径布置。在一些实施例中，例如，第一组通孔106a沿着第一环形路径布置，并且第二组通孔106b沿着围绕第一环形路径的第二环形路径布置。换句话说，通孔106a设置在通孔106b和用于半导体管芯的区域之间。在一些实施例中，相同组的通孔106a、106b可以规则地布置，即，相同组的相邻通孔106a、106b之间的距离是恒定的。在一些可选实施例中，相同组的通孔106a、106b可以不规则地或随机地布置，即，相同组的通孔106a、106b之间的距离不是恒定的。在一些可选实施例中，通孔可以沿着一个环形路径或多于两个环形路径布置。在一些可选实施例中，当通孔沿着多于两个环形路径布置时，通孔的相邻组之间的距离可以是恒定的。
在一些实施例中，通孔106a、106b的材料包括铜(Cu)、铝(Al)、铝铜合金(AlCu)、金、钛、钴、合金或任何合适的导电材料。通孔106a、106b可以通过例如电化学镀(ECP)、电镀、化学镀或任何其它合适的工艺形成。
在一些实施例中，导热图案108设置在通孔106a、106b和用于半导体管芯的区域之间的缓冲层104上。在一些实施例中，导热图案108包括例如多个离散的通孔108a。在一些实施例中，例如，通孔108a沿着围绕用于半导体管芯的区域的一个环形路径P1布置。在一些实施例中，通孔108a可以规则地布置，即，相邻的通孔108a之间的距离是恒定的。在一些可选实施例中，通孔108a可以不规则地或随机地布置，即，通孔108a之间的距离不是恒定的。在一些可选实施例中，环形路径P1例如是矩形的。然而，取决于半导体管芯的形状和/或要求，环形路径P1可以被设计为其它合适的环形，诸如圆形、方形或多边形。
在本文中，通孔106a、106b指示功能性通孔，并且通孔108a指示非功能性通孔。具体地，封装结构中的通孔106a、106b电连接至相同封装结构或另一封装结构的前侧或背侧再分布电路结构或电组件。然而，通孔108a可以处于浮置电位并且与相同封装结构或另一封装结构的前侧或背侧再分布电路结构或电组件电绝缘。
在一些实施例中，如图3所示，通孔108a可以在第一方向和第二方向中的至少一个方向上与通孔106a、106b部分地对准，第一方向和第二方向垂直于管芯和半导体器件沿着其堆叠的堆叠方向。在一些实施例中，例如，第一方向和第二方向是诸如x方向和y方向的水平方向，并且堆叠方向是诸如z方向的垂直方向。在一些可选实施例中，通孔108a可以不在第一方向和/或第二方向上与通孔106a、106b对准。在一些实施例中，通孔108a和用于半导体管芯的区域之间的距离可以小于相邻的通孔106a、108a之间的距离。然而，在一些可选实施例中，通孔108a和用于半导体管芯的区域之间的距离可以大于或基本等于相邻通孔106a、108a之间的距离。在一些实施例中，相邻通孔106a、108a之间的距离可以大于相邻通孔106a、106b之间的距离。在一些实施例中，相邻通孔106a、108a之间的距离可以是相邻通孔106a、106b之间的距离的两倍或更多倍。例如，相邻通孔106a、108a之间的距离可以是相邻通孔106a、106b之间的距离的三倍、四倍、五倍或六倍。然而，在一些可选实施例中，相邻通孔106a、108a之间的距离可以小于或基本等于相邻通孔106a、106b之间的距离。
在一些实施例中，导热图案108的顶面可以与通孔106a、106b的顶面基本齐平并共面。在一些实施例中，例如，通孔108a的顶面可以与通孔106a、106b的顶面基本齐平并共面。然而，在一些可选实施例中，导热图案108的顶面可以低于或高于通孔106a、106b的顶面。
在一些实施例中，导热图案108的材料包括铜(Cu)、铝(Al)、铝铜合金(AlCu)、金、钛、钴、合金或任何其它合适的导电材料。导热图案108可以通过例如电化学镀(ECP)、电镀、化学镀或任何其它合适的工艺形成。在一些实施例中，例如，导热图案108的材料可以与通孔106a、106b的材料相同。在一些可选实施例中，导热图案108的材料可以与通孔106a、106b的材料不同。在一些实施例中，导热图案108和通孔106a、106b可以同时形成。例如，通孔108a和通孔106a、106b可以同时形成。在一些实施例中，对于电镀均匀性，通孔108a的尺寸(例如，宽度W2)在从通孔106a、106b的一个的尺寸(例如，宽度W1)的一半至两倍的范围内。在一些实施例中，宽度W2例如小于宽度W1。在一些可选实施例中，通孔106a、106b和导热图案108可以单独形成。
参照图1和图2B，在步骤S30中，提供半导体管芯110并将其设置在载体102上方的暴露的缓冲层104上。在一些实施例中，半导体管芯110可以是数字芯片、模拟芯片或混合信号芯片，诸如专用集成电路(“ASIC”)芯片、传感器芯片、无线和射频芯片、存储器芯片、逻辑芯片、电压调节器芯片或任何其它合适的芯片。在一些实施例中，半导体管芯110例如是片上系统(SoC)。在一些实施例中，半导体管芯110包括衬底112、有源表面114a、与有源表面114a相对的后表面114b、分布在有源表面114a上的多个焊盘116、覆盖有源表面114a的钝化层118、多个金属柱120和保护层122。衬底112可以是半导体衬底，诸如硅衬底，但是它可以由其它半导体材料形成，包括但不限于硅锗、硅碳、砷化镓等。半导体管芯110可以包括形成在衬底112中或衬底112上的器件层。在一些实施例中，器件层可以包括晶体管、电阻器、电容器、电感器等。焊盘116可以形成在器件层上并且电连接至器件层，并且可以是互连结构的焊盘。焊盘116由钝化层118部分地暴露，并且金属柱120设置在焊盘116上并且电连接至焊盘116。焊盘116例如是铝接触焊盘。例如，金属柱120是铜柱或铜合金柱。保护层122覆盖金属柱120和钝化层118。在一些可选实施例中，在将半导体管芯110放置在载体102上之前，金属柱120未被覆盖(即未被模制或封装的裸管芯)。在一些实施例中，保护层122是聚合物层。例如，保护层122包括光敏材料，诸如PBO、聚酰亚胺、BCB、它们的组合等。
在一些实施例中，半导体管芯110的顶面不与通孔106a、106b和导热图案108的顶面共面。在一些实施例中，例如，半导体管芯110的顶面低于通孔106a、106b和导热图案108的顶面。在一些可选实施例中，半导体管芯110的顶面可以与通孔106a、106b和导热图案108的顶面基本齐平或者高于通孔106a、106b和导热图案108的顶面。在一些实施例中，管芯附接膜124设置在半导体管芯110的后表面114b和缓冲层104之间以用于更好的附接，并且半导体管芯110的后表面114b粘合至载体102。在一些实施例中，半导体管芯110放置在导热图案108旁边的区域中的载体102上方。在一些实施例中，半导体管芯110设置在由导热图案108围绕的区域内。
在一些实施例中，导热图案108围绕半导体管芯110，并且通孔106a、106b围绕导热图案108。换句话说，导热图案108设置在半导体管芯110和通孔106a、106b之间。因此，通孔108a和半导体管芯110之间的第一最小距离D1小于通孔106a和半导体管芯110之间的第二最小距离D2。在一些实施例中，通孔106a、106b和导热图案108例如分别分布在半导体管芯110的四个侧。在一些实施例中，通孔106a、106b和通孔108a例如分别分布在半导体管芯110的四个侧。在一些实施例中，例如，通孔106a、106b和通孔108a在半导体管芯110的一侧处的分布与通孔106a、106b和通孔108a在半导体管芯110的另一侧处的分布基本对称。具体地，一侧处的通孔106a、106b和通孔108a相对于中心半导体管芯110在配置和位置上与另一侧处的通孔106a、106b和通孔108a对称。在一些实施例中，如图2B所示，虚线表示随后的切割工艺中的整个封装件的切割线，并且通孔106b布置在切割线附近但不在切割线上，并且布置在导热图案108和半导体管芯110周围。
参照图1和图2C，在步骤S40中，在载体102上方形成密封剂130，以密封半导体管芯110、通孔106a、106b和导热图案108。在一些实施例中，密封剂130覆盖缓冲层104并且填充在半导体管芯110、导热图案108和通孔106a、106b之间。在一些实施例中，密封剂130设置在半导体管芯110、通孔108a和通孔106a、106b之间。在一些实施例中，密封剂130横向密封半导体管芯110，即，半导体管芯110的侧壁由密封剂130密封。在一些实施例中，通过过模塑工艺形成覆盖半导体管芯110、通孔106a、106b和导热图案108的顶面的模塑材料，并且然后通过平坦化工艺去除部分模塑材料以暴露半导体管芯110、通孔106a、106b和导热图案108的顶面来形成密封剂130。在一些实施例中，用于平坦化模塑材料和半导体管芯110、通孔106a、106b和导热图案108的平坦化工艺包括飞切工艺、研磨工艺、化学机械抛光(“CMP”)工艺或任何其它合适的工艺。在一些实施例中，也通过平坦化工艺去除半导体管芯110的保护层122、通孔106a、106b和导热图案108的部分。在一些实施例中，密封剂130的第一表面130a与半导体管芯110的保护层122和金属柱120、通孔106a、106b和导热图案108基本共面和齐平。在一些实施例中，通孔106a、106b和导热图案108分别穿透并且嵌入密封剂130。在一些实施例中，密封剂130包括模塑料、模塑底部填充物、树脂(诸如环氧树脂)、光敏材料(诸如PBO、聚酰亚胺、BCB)、它们的组合等。
参照图1和图2D，在步骤S50中，在一些实施例中，在密封剂130、半导体管芯110、通孔106a、106b和导热图案108上方形成再分布电路结构140。在一些实施例中，在密封剂130的第一表面130a、半导体管芯110的有源表面114a以及通孔106a、106b和导热图案108的顶面上方形成再分布电路结构140。在一些实施例中，再分布电路结构140设置在半导体管芯110的金属柱120的顶面上。在一些实施例中，再分布电路结构140电连接至通孔106a、106b和半导体管芯110并且与导热图案108电绝缘。
在一些实施例中，再分布电路结构140包括介电层142和位于介电层142中的多个再分布图案144。在一些实施例中，再分布图案144电连接至同一封装结构的通孔106a、106b或电组件，诸如半导体管芯110的金属柱120。在一些实施例中，再分布图案144与导热图案108电绝缘。在一些实施例中，再分布电路结构140的底部再分布图案144例如与通孔106a、106b和半导体管芯110的金属柱120接触。在一些实施例中，导热图案108通过介电层142与再分布图案144电绝缘。在一些实施例中，导热图案108例如与底部介电层142接触。在一些实施例中，再分布图案144的材料包括铝、钛、铜、镍、钨、银和/或它们的合金。在一些实施例中，介电层142的材料包括聚酰亚胺、苯并环丁烯或聚苯并恶唑。在一些实施例中，介电层142可以是单层或多层结构。在一些实施例中，再分布电路结构140是电连接至半导体管芯110的前侧再分布电路结构并且电连接至通孔106a、106b。在一些实施例中，由于下面的密封剂130提供更好的平坦化和均匀性，之后形成的再分布电路结构140，尤其是具有细线宽或紧密间隔的再分布图案144，可以在平坦和水平密封剂130上方形成为具有均匀的线宽或均匀的轮廓，从而提高线/布线的可靠性。
在一些实施例中，多个导电元件146设置在再分布电路结构140上并且电连接至再分布电路结构140。在一些实施例中，在设置导电元件146之前，可以施加焊剂，使得导电元件146更好固定至再分布电路结构140的顶部再分布图案144，并且顶部再分布图案144可以用作导电元件146的接触焊盘。在一些实施例中，导电元件146例如是放置在再分布电路结构140上的焊球或球栅阵列(“BGA”)球，并且位于导电元件146下面的顶部再分布图案144用作球焊盘。在一些实施例中，一些导电元件146通过再分布电路结构140电连接至半导体管芯110，并且一些导电元件146电连接至通孔106a、106b。在一些实施例中，导电元件146与导热图案108电绝缘。
参照图1和图2D以及图2E，在步骤S60中，在一些实施例中，将整个封装件从载体102脱粘以将半导体管芯110与载体102分离。在一些实施例中，在从载体102脱粘之后，通过蚀刻工艺或清洁工艺去除保留在整个封装件上的缓冲层104。可选地，在一些可选实施例中，可以保留缓冲层104。
然后，在一些实施例中，将整个封装上下颠倒并且设置在载体膜150上。当封装结构上下颠倒时，顶面可以变成底面并且相对位置关系(诸如之上、之下、高于或低于)可以变得与如上所述的封装结构相反，但是相同的表面、共用表面或界面将用半导体封装件的相同参照标号标记。在从载体102脱粘之后，暴露管芯附接膜124。在一些实施例中，管芯附接膜124的顶面与密封剂130、通孔106a、106b和导热图案108的顶面基本共面和齐平。
之后，去除管芯附接膜124，并且因此在半导体管芯110上方的密封剂130中形成沟槽132。在一些实施例中，在去除管芯附接膜124之后，半导体管芯110的后表面114b暴露。在一些实施例中，半导体管芯110的后表面114b低于与密封剂130的第一表面130a相对的第二表面130b。此外，半导体管芯110的后表面114b低于通孔106a、106b和导热图案108的顶面。
参照图1以及图2E和图2F，在步骤S70中，在一些实施例中，在半导体管芯110和密封剂130上方形成导热层160，其中，导热图案108通过导热层160热耦合至半导体管芯110。在一些实施例中，散热结构包括导热图案108和导热层160。如本文所使用的，热耦合意味着将使散热结构的温度变化引起半导体管芯的温度变化，反之亦然。在一些实施例中，导热层160形成在半导体管芯110的后表面114b上方以填充沟槽132。因此，导热层160和再分布电路结构140设置在半导体管芯110的相对侧上。在一些实施例中，导热层160从半导体管芯110的后表面114b向外延伸，以覆盖密封剂130的第二表面130b的部分和导热图案108的顶面。在一些实施例中，导热层160覆盖导热图案108的顶面旁边的密封剂130的第二表面130b。在一些实施例中，导热层160与通孔106a、106b的顶面分离以与通孔106a、106b电绝缘。换句话说，导热层160的边缘与通孔106a的边缘分离，并且因此导热层160与通孔106a电绝缘。
在一些实施例中，导热层160可以与半导体管芯110的后表面114b、密封剂130的第二表面130b的部分和导热图案108的顶面接触。在一些实施例中，导热层160例如完全覆盖导热图案108的顶面。然而，在一些可选实施例中，导热层160可以部分地覆盖导热图案108，或可以不覆盖导热图案108。
在一些实施例中，导热层160包括覆盖半导体管芯110的第一部分162和覆盖密封剂130和导热图案108的第二部分164。在一些实施例中，例如，第一部分162的顶面与第二部分164的顶面基本齐平。然而，在一些可选实施例中，第一部分162和第二部分164的顶面可以彼此不共面。在一些实施例中，第一部分162比第二部分164厚，因为第一部分162的部分填充在沟槽132中。换句话说，从半导体管芯110的后表面114b至其自身顶面的第一部分162的厚度T1大于从密封剂130的第二表面130b的顶面至其自身顶面的第二部分164的厚度T2。在一些实施例中，厚度T2可以例如大于或等于5μm。在一些实施例中，半导体管芯110和导热层160之间的界面低于密封剂130和导热层160之间的界面。导热层160是诸如银膏的导电膏，并且例如通过印刷工艺形成。
参照图1和图2G，在步骤S80中，半导体器件170堆叠在半导体管芯110上方并且电连接至半导体管芯110。在一些实施例中，半导体器件170是诸如动态随机存取存储器(DRAM)封装件或任何其它合适的半导体器件的封装件。在一些实施例中，半导体器件170设置在半导体管芯110上方的导热层160上，并且导热层160设置在半导体管芯110和半导体器件170之间。在一些实施例中，半导体器件170包括多个接触件172。例如，接触件172可以是焊盘或焊盘上金属柱。半导体器件170的接触件172通过导电元件174和通孔106a、106b电连接至再分布电路结构140。在一些实施例中，导电元件174例如是放置在半导体器件170上的焊球或BGA球。在一些实施例中，在半导体器件170和导热层160之间形成间隙G，即，间隙G小于导电元件174的高度。因此，导热层160不与半导体器件170接触并且因此与半导体器件170电绝缘。在一些实施例中，间隙G可以在例如导电元件174的高度的25％至40％的范围内。在一些实施例中，半导体管芯110和半导体器件170之间的垂直距离可以在从50至60μm的范围内，并且间隙G可以例如大于10μm。在一些可选实施例中，导热层160的至少部分与第二管芯170直接接触。换句话说，例如，导热层160的部分可以与第二管芯170接触，导热层160的部分可以与第二管芯170分开一定距离，并且导热层160的顶面可以不是平坦的。
参照图2H，在一些实施例中，在导电元件174、半导体器件170和导热层160之间形成底部填充物176。因此，间隙G填充有底部填充物176。在一些实施例中，半导体器件170和导热层160之间的间隙G中的底部填充物176确保半导体器件170和导热层160之间的电绝缘。
参照图1、图2H和图2I，在一些实施例中，实施切割工艺以沿着切割线(虚线)将整个封装结构(至少切割穿过密封剂130和再分布电路结构140)切割成单独且分离的半导体封装件100，如图2I所示。在一个实施例中，切割工艺是包括机械刀片锯切或激光切割的晶圆切割工艺。在一些实施例中，半导体封装件100是例如集成扇出封装(InFO PoP)器件。在一些可选实施例中，半导体封装件100可以进一步安装在电子器件上，电子器件可以例如是诸如印刷电路板(PCB)的板。在一些可选实施例中，半导体封装件100可以安装有附加封装件、芯片/管芯或其它电子器件。
在一些实施例中，如图2I所示，通孔106a、106b和导热图案108嵌入在半导体管芯110旁边的密封剂130中，并且导热层160设置在半导体管芯110上并且延伸至密封剂130上。通孔106a、106b电连接至半导体管芯110，并且导热图案108与半导体管芯110电绝缘，但是通过导热层160热耦合至半导体管芯110。因此，由半导体封装件100的任何组件(诸如半导体管芯110或半导体器件170)产生的热量可以通过导热层160和导热图案108消散，并且半导体封装件100的散热面积扩大。因此，例如，与没有导热图案和导热层的传统半导体封装件相比，传统的半导体封装件具有导热层(其不与半导体器件接触)而没有导热图案，或传统的半导体封装件具有导热层(其与半导体器件接触)而没有导热图案，可以提高半导体管芯的散热效率。
在一些实施例中，导热图案108被示出为具有沿着一个环形路径P1布置的多个离散通孔108a，然而，本发明不限于此。换句话说，导热图案可以沿着多个环形路径布置。在一些实施例中，如图4所示，导热图案108可以包括沿着多个环形路径P1、P2布置的多个通孔108a、108b。在一些实施例中，第一组离散通孔108a沿着第一环形路径P1布置，第二组离散通孔108b沿着围绕第一环形路径P1的第二环形路径P2布置，并且环形路径P1、P2分别围绕半导体管芯110。在一些实施例中，第二组通孔108b设置在第一组通孔108a和第一组通孔106a之间。在一些实施例中，通孔108a的宽度可以与通孔108b的宽度相同或不同。在一些实施例中，例如，在垂直于半导体管芯110和半导体器件170的堆叠方向的方向上，第一组的通孔108a中的一个与第二组的通孔108b中的一个部分地对准。此外，对准的通孔108a、108b可以进一步与对准的通孔106a和通孔106b对准。然而，在一些可选实施例中，通孔106a、106b可以彼此不对准或者可以不与通孔108a、108b对准。例如，在一些实施例中，如图5所示，在垂直于堆叠方向的方向上，第一组通孔108a中的一个和第二组通孔108b中的一个彼此紧邻，并且它们可以交替地设置。此外，在一些实施例中，也可以交替地设置彼此紧邻的通孔106a和通孔106b。在一些实施例中，在垂直于堆叠方向的方向上，第一组通孔108a中的一个可以与第一组通孔106a中的一个部分地对准，并且类似地，第二组通孔108b中的一个与第二组通孔106b中的一个部分对准。
导热图案108可以具有其它配置。例如，如图6所示，导热图案108包括围绕半导体管芯110的环形结构108c。环形结构108c沿着环形路径P连续形成。换句话说，环形结构108c连续地设置在半导体管芯110周围。在一些实施例中，例如，环形结构108c的宽度W2可以基本相同，并且宽度W2可以在从通孔106a、106b中的一个的尺寸(例如，宽度W1)的一半至两倍的范围内。在一些可选实施例中，导热图案108可以包括分别沿着围绕半导体管芯110的多个环形路径设置的多个环形结构。
在一些实施例中，如图7和图8所示，导热图案108可以包括多个离散的壁状结构108d。壁状结构108d彼此分离，并且壁状结构108d沿着一个环形路径P布置。在一些实施例中，如图7所示，壁状结构108d分别设置在半导体管芯110的一侧处。在一些实施例中，壁状结构108d例如是长方体。在一些实施例中，如图8所示，至少一个壁状结构108d可以设置在半导体管芯110的两个相邻侧处。在一些可选实施例中，例如，一个壁状结构108d可以设置在半导体管芯110的三个或四个相邻侧处。在一些实施例中，例如，壁状结构108d的宽度W2可以基本相同，并且宽度W2可以在从通孔106a、106b中的一个的尺寸(例如，宽度W1)的一半至两倍的范围内。在一些可选实施例中，壁状结构108d的宽度W2可以是不同的。在一些可选实施例中，壁状结构108d可以沿着分别围绕半导体管芯110的多个环形路径布置。此外，应该注意，在图3至图8中，示例性地示出了半导体管芯110和导热图案108之间或者导热图案108和通孔106a之间的距离，实际上，在一些实施例中，上述距离可以大于例如，相邻的两个通孔106a、106b之间的距离。然而，在一些可选实施例中，上述距离可以等于或小于相邻的两个通孔106a、106b之间的距离。此外，图3至图8中的导热图案108的材料可以是导电材料，诸如针对通孔108a所描述的那些。
在以上实施例中，导热图案被示出为沿着一个环形路径或两个环形路径布置，然而，本发明不限于此。换句话说，导热图案可以沿着两个以上的环形路径布置。此外，环形路径可以具有相同或不同的形状，并且沿着相邻的两个环形路径的导热图案的组件之间间隔可以相同或不同。
图9是根据一些实施例的示出半导体封装件的示意性截面图。图9的半导体封装件和图2I的半导体封装件之间的差异在于：再分布电路结构还包括伪图案。下面详细说明差异，并且此处不重复相似性。在一些实施例中，如图9所示，再分布电路结构140还包括与封装结构中的再分布图案144或相同封装结构或另一封装结构的电组件电绝缘的伪图案148。在一些实施例中，伪图案148设置在再分布电路结构140的底部。在一些实施例中，伪图案148设置在密封剂130的第一表面130a上并设置在再分布电路140的介电层142中。在一些实施例中，导热图案108连接至伪图案148，这意味着导热图案108电连接至伪图案148。在一些实施例中，例如，导热图案108可以与伪图案148接触。在一些实施例中，导热图案108在第一侧热耦合至导热层160，并且在与第一侧相对的第二侧热耦合至伪图案148。因此，由半导体封装件产生的热量可以通过导热层160、导热图案108和伪图案148消散，并且半导体管芯110的散热面积扩大。因此，可以提高散热效率。
图10是根据一些实施例的示出半导体封装件的示意性截面图。图10的半导体封装件和图2I的半导体封装件之间的差异在于：半导体封装件还包括管芯附接膜。下面详细说明差异，并且此处不重复相似性。在一些实施例中，如图10所示，例如，如果管芯附接膜124具有良好的导热性，则在形成导热层160之前可以不去除管芯附着膜124，并且因此管芯附接膜124可以设置在半导体管芯110和导热层160之间。在一些实施例中，导热层160可以基本具有恒定的厚度T，即，半导体管芯110上方的第一部分162和密封剂130和导热图案108上方的第二部分164可以基本具有相同的厚度T。例如，厚度T可以大于或等于5μm。
在一些实施例中，半导体封装件具有热耦合至半导体管芯的散热结构。在一些实施例中，散热结构包括半导体管芯旁边的导热图案和设置在半导体管芯上并且延伸至导热图案上的导热层。因此，导热图案可以通过导热层热耦合至半导体管芯。通过设置散热结构，可以大大扩展半导体封装件的散热面积，并且可以显著提高半导体封装件的散热效率。此外，虽然导热层设置在半导体管芯和半导体器件之间，但是控制导热层的高度以防止与其上方的半导体器件接触。因此，可以防止诸如PoW(片上封装件)冷接合风险和其它工艺问题的冷接合风险。此外，导热层在密封剂和导热图案上的延伸增加了半导体管芯和导热层之间的接触面积，从而增强了导热层与半导体管芯的粘合。因此，半导体封装件的散热稳定并得到提高。
根据一些实施例，半导体封装件包括半导体管芯、导热图案、密封剂和导热层。导热图案设置在半导体管芯旁边。密封剂密封半导体管芯和导热图案。导热层覆盖半导体管芯的后表面，其中，导热图案通过导热层热耦合至半导体管芯并且与半导体管芯电绝缘。根据一些实施例，半导体封装件还包括堆叠在所述半导体管芯上方并且电连接至所述半导体管芯的半导体器件。根据一些实施例，所述导热图案包括多个离散的通孔。根据一些实施例，所述多个离散的通孔沿着围绕所述半导体管芯的至少一个环形路径布置。根据一些实施例，所述导热图案包括围绕所述半导体管芯的环形结构。根据一些实施例，所述导热图案包括多个离散的壁状结构。根据一些实施例，半导体封装件还包括，设置在所述半导体管芯的有源表面和所述密封剂的第一表面上方的再分布电路结构，其中，所述半导体管芯的有源表面与所述半导体管芯的所述后表面相对，并且所述再分布电路结构电连接至所述半导体管芯。根据一些实施例，所述再分布电路结构还包括设置在所述密封剂的第一表面上的伪图案，并且所述导热图案连接至所述伪图案。根据一些实施例，所述导热层从所述半导体管芯的后表面向外延伸以部分地覆盖所述密封剂的第二表面，并且，所述密封剂的第二表面与所述密封剂的第一表面相对。
根据一些实施例，半导体封装件包括半导体管芯、密封剂、第一通孔、第二通孔和导热层。密封剂横向密封半导体管芯。第一通孔嵌入在密封剂中并且电连接至半导体管芯。第二通孔嵌入在密封剂中并且与半导体管芯电绝缘。导热层覆盖半导体管芯，其中，第二通孔通过导热层热耦合至半导体管芯。根据一些实施例，半导体封装件还包括，堆叠在所述半导体管芯上方并且电连接至所述半导体管芯的半导体器件，其中，所述导热层和所述半导体器件分开一段距离。根据一些实施例，所述导热层设置在所述半导体管芯上方并且延伸至所述第二通孔上。根据一些实施例，所述导热层与所述半导体管芯和所述第二通孔接触。根据一些实施例，所述导热层包括覆盖所述半导体管芯的第一部分和覆盖所述密封剂的第二部分，并且所述第一部分比所述第二部分厚。根据一些实施例，所述第一通孔和所述半导体管芯之间的第一最小距离小于所述第二通孔和所述半导体管芯之间的第二最小距离。
根据一些实施例，半导体封装件包括半导体管芯、密封剂、第一通孔、第二通孔和导热层。密封剂横向密封半导体管芯。第一通孔嵌入在密封剂中并且电连接至半导体管芯。第二通孔嵌入在密封剂中并且与半导体管芯电绝缘。导热层覆盖半导体管芯和密封剂，其中，导热层包括覆盖半导体管芯的第一部分和覆盖第二通孔的第二部分，其中，导热层的第一部分比导热层的第二部分厚。根据一些实施例，所述导热层部分地覆盖所述密封剂。根据一些实施例，所述第一通孔和所述半导体管芯之间的第一最小距离大于所述第二通孔和所述半导体管芯之间的第二最小距离。根据一些实施例，所述第二通孔的第二宽度在从所述第一通孔的第一宽度的一半至两倍的范围内。根据一些实施例，所述导热层与所述第二通孔接触。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体封装件，包括：
半导体管芯；
导热图案，位于所述半导体管芯旁边；
密封剂，密封所述半导体管芯和所述导热图案；以及
导热层，覆盖所述半导体管芯的后表面，其中，所述导热图案通过所述导热层热耦合至所述半导体管芯并且与所述半导体管芯电绝缘。
2.根据权利要求1所述的半导体封装件，还包括，堆叠在所述半导体管芯上方并且电连接至所述半导体管芯的半导体器件。
3.根据权利要求1所述的半导体封装件，其中，所述导热图案包括多个离散的通孔。
4.根据权利要求3所述的半导体封装件，其中，所述多个离散的通孔沿着围绕所述半导体管芯的至少一个环形路径布置。
5.根据权利要求1所述的半导体封装件，其中，所述导热图案包括围绕所述半导体管芯的环形结构。
6.根据权利要求1所述的半导体封装件，其中，所述导热图案包括多个离散的壁状结构。
7.根据权利要求1所述的半导体封装件，还包括，设置在所述半导体管芯的有源表面和所述密封剂的第一表面上方的再分布电路结构，其中，所述半导体管芯的有源表面与所述半导体管芯的所述后表面相对，并且所述再分布电路结构电连接至所述半导体管芯。
8.根据权利要求7所述的半导体封装件，其中，所述再分布电路结构还包括设置在所述密封剂的第一表面上的伪图案，并且所述导热图案连接至所述伪图案。
9.一种半导体封装件，包括：
半导体管芯；
密封剂，横向密封所述半导体管芯；
第一通孔，嵌入在所述密封剂中并且电连接至所述半导体管芯；
第二通孔，嵌入在所述密封剂中并且与所述半导体管芯电绝缘；以及
导热层，覆盖所述半导体管芯，其中，所述第二通孔通过所述导热层热耦合至所述半导体管芯。
10.一种半导体封装件，包括：
半导体管芯；
密封剂，横向密封所述半导体管芯；
第一通孔，嵌入在所述密封剂中并且电连接至所述半导体管芯；
第二通孔，嵌入在所述密封剂中并且与所述半导体管芯电绝缘；以及
导热层，覆盖所述半导体管芯和所述密封剂，其中，所述导热层包括覆盖所述半导体管芯的第一部分和覆盖所述第二通孔的第二部分，并且所述导热层的第一部分比所述导热层的第二部分厚。
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