Nothing Special   »   [go: up one dir, main page]

CN103681515B - 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置 - Google Patents

一种互补型薄膜晶体管驱动背板及其制备方法、显示装置 Download PDF

Info

Publication number
CN103681515B
CN103681515B CN201310723714.0A CN201310723714A CN103681515B CN 103681515 B CN103681515 B CN 103681515B CN 201310723714 A CN201310723714 A CN 201310723714A CN 103681515 B CN103681515 B CN 103681515B
Authority
CN
China
Prior art keywords
type tft
preparation
layer
type
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310723714.0A
Other languages
English (en)
Other versions
CN103681515A (zh
Inventor
刘晓娣
王刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201310723714.0A priority Critical patent/CN103681515B/zh
Publication of CN103681515A publication Critical patent/CN103681515A/zh
Priority to PCT/CN2014/078571 priority patent/WO2015096382A1/zh
Priority to US14/416,872 priority patent/US9647014B2/en
Application granted granted Critical
Publication of CN103681515B publication Critical patent/CN103681515B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/38—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
    • H01L21/383—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明涉及显示技术领域，尤其涉及一种互补型薄膜晶体管驱动背板及其制备方法、显示装置。所述制备方法包括在衬底基板上形成下层电极；依次设置连续生长介质层、半导体层和扩散保护层；通过多灰阶光罩曝光工序形成无光刻胶区、N型薄膜晶体管制备区和P型薄膜晶体管制备区；通过等离子体灰化工序去除N型薄膜晶体管制备区的光刻胶层；去除N型薄膜晶体管制备区的扩散保护层；去除P型薄膜晶体管制备区的光刻胶层；对衬底基板进行氧化处理；在衬底基板上设置钝化层；在钝化层上形成上层电极。

Description

一种互补型薄膜晶体管驱动背板及其制备方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种互补型薄膜晶体管驱动背板及其制备方法、显示装置。
背景技术
薄膜晶体管（TFT，Thin-FilmTransistor）目前正在从技术研发领域转向量产，各个面板厂家不断推出新的样机和产品。尤其对于氧化铟镓锡（IGZO）材料，深得市场认可。然而，目前该材料主要为N型薄膜晶体管制造材料，其化学特性决定无法实现互补型薄膜晶体管驱动背板的制造需要，具体地说，无法实现把周边驱动电路做在基板阵列上，集成度低，产品轻巧特征受限。在互补型薄膜晶体管驱动背板制造方面，目前成熟的技术仍然以低温多晶硅技术为主，该技术又存在技术和设备复杂、制备成本高等缺点。因此，互补型薄膜晶体管驱动背板（主要集中在P型薄膜晶体管）的制备，成为各大面板厂商和科研单位的研究热点和瓶颈；目前，制备方法中所出现的问题集中在因制造过程中对于互补型薄膜晶体管驱动背板中的P型薄膜晶体管、N型薄膜晶体管及像素电极的区域不易界定，因界定不准而极易造成互补型薄膜晶体管驱动背板生产良率底的问题，以及因步骤过于繁琐，光罩掩膜使用次数过多而造成的制备成本过高的问题。
因此，针对上述问题本发明提出一种新的互补型薄膜晶体管驱动背板及其制备方法、显示装置。
发明内容
本发明提供一种互补型薄膜晶体管驱动背板及其制备方法、显示装置，该制备方法首先制备SnO材料，再利用扩散阻挡层选择性高温氧化SnO材料。被扩散阻挡层保护区域未被氧化，为p型有源层的材料，而未保护区域的SnO被氧化成为SnOx，其中,1<x<2，为n型有源层的材料。
为减少光罩掩膜版，降低制备成本，本发明涉及一种多灰阶曝光刻蚀方案制备不同特性的有源层。即光刻、显影、剥离后形成三个区域：无光刻胶区，N型薄膜晶体管制备区和P型薄膜晶体管制备区。
本发明的目的是通过以下技术方案实现的：一种互补型薄膜晶体管驱动背板的制备方法，包括如下步骤：
S1、在衬底基板上形成下层电极；
S2、依次设置连续生长介质层、半导体层和扩散保护层；
S3、通过多灰阶光罩曝光工序形成无光刻胶区、N型薄膜晶体管制备区和P型薄膜晶体管制备区；
S4、通过等离子体灰化工序去除N型薄膜晶体管制备区的光刻胶层；
S5、去除N型薄膜晶体管制备区的扩散保护层；
S6、去除P型薄膜晶体管制备区的光刻胶层；形成具有P型有源层的P型薄膜晶体管；
S7、对衬底基板进行氧化处理；形成具有N型有源层的N型薄膜晶体管；
S8、在衬底基板上设置钝化层；
S9、在钝化层上形成上层电极。
进一步地，还包括对制备后的互补型薄膜晶体管驱动背板进行退火处理的步骤。
进一步地，所述半导体层材料为SnO材料。
进一步地，经氧化处理后的N型薄膜晶体管制备区内的半导体层，其材料由SnO被氧化成SnOx，其中1<x<2；被用作N型薄膜晶体管中的N型有源层；而在氧化处理过程中，由于有扩散保护层的保护，因此P型薄膜晶体管的P型有源层没有经受氧化处理。
进一步地，所述步骤S2中所述半导体层采用溅射工艺、溶胶-凝胶工序、真空蒸镀工序、喷涂工序其中一种制得。
进一步地，在钝化层上通过溅射工艺设置上电极层，对上电极层进行图形化处理，形成多个上层电极。
一种如上述中所述制备方法制得的互补型薄膜晶体管驱动背板，有一个衬底基板，在该衬底基板上设置有多个P型薄膜晶体管制备区、多个N型薄膜晶体管制备区，以及设置在P型薄膜晶体管制备区与N型薄膜晶体管制备区之间的无光刻胶区。
一种显示装置，包括如上述中所述的互补型薄膜晶体管驱动背板。
本发明与现有技术相比具有以下的优点：
本发明只需通过多灰阶光罩曝光工序即可同时定义并形成N型薄膜晶体管制备区和P型薄膜晶体管制备区；以此可清晰的界定区分出如P型薄膜晶体管、N型薄膜晶体管及像素电极的制作区域；为之后的各器件的制作提供了可靠保障；使现有互补型薄膜晶体管驱动背板制造工序中由于各器件制作区域界定不清而导致的P型薄膜晶体管与N型薄膜晶体管相互干扰的问题得到了有效解决，使的由此产生的产品制造良率低的问题得到了有效改善；并且有效降低了制备成本；同时，利用P型薄膜晶体管制备区的扩散保护层作为高温退火氧化处理中P型有源层的掩膜板，可省去现有技术中需单独通过一次光罩曝光工序制造P型有源层的步骤；简化制备工序、提高生产良率、有效降低了生产升本。
附图说明
以下结合附图和实施例对本发明作进一步说明。
图1是本发明中所述制备方法的步骤框图；
图2是本发明中所述制备方法的步骤1示意图（主剖视图）；
图3是本发明中所述制备方法的步骤2示意图（主剖视图）；
图4是本发明中所述制备方法的步骤3示意图（主剖视图）；
图5是本发明中所述制备方法的步骤4示意图（主剖视图）；
图6是本发明中所述制备方法的步骤5示意图（主剖视图）；
图7是本发明中所述制备方法的步骤6示意图（主剖视图）。
具体实施方式
参见图1所示，本发明的一种互补型薄膜晶体管驱动背板的制备方法，包括如下步骤：
1、参见图2所示，选择衬底基板101，并在衬底基板上通过溅射工艺设置下电极层，按照设计要求通过光罩曝光工序对下电极层进行图形化处理，形成按照预设计的分布图案分布的多个下层电极102；本实施例中所述的衬底基板可采用通常的玻璃、硅等材料，所选用的材料不限于这两种，理论上说只要具有好的透光度和一定的硬度的材料均可制成衬底基板。本实施例中所述下层电极为Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo或Au/Ti中任一材料；形成于衬底基板上的各个下层电极将被用作P型薄膜晶体管或N型薄膜晶体管的栅极。
2、参见图3所示，在下电极层上由下至上依次设置连续生长介质层103、半导体层104和扩散保护层105；本实施例中所述连续生长介质层或扩散保护层可设置为单层也可设置为多层。具体地说，所述连续生长介质层将设置在衬底基板上的所有下层电极全部覆盖，并在连续生长介质层上依次设置半导体层和扩散保护层。所述半导体层材料为SnO（氧化亚锡）材料。本实施例中所述半导体层采用溅射工艺、溶胶-凝胶工序、真空蒸镀工序、喷涂工序其中一种制得。SnO符合P型薄膜晶体管特性。
本实施例中所述连续生长介质层采用热生长热生工序、常压化学气相沉积工序、低压化学气相沉积工序、等离子辅助体化学气相淀积工序、或溅射工艺其中一种制得。所述连续生长介质层为SiOx或SiNx其中之一。
本实施例中所述扩散保护层采用热生长热生工序、常压化学气相沉积工序、低压化学气相沉积工序、等离子辅助体化学气相淀积工序、或溅射工艺其中一种制得。所述扩散保护层为SiOx或SiNx其中之一。
3、参见图4所示，在扩散保护层上设置光刻胶层114；通过多灰阶光罩曝光工序在衬底基板上分别形成无光刻胶区107、N型薄膜晶体管制备区108和P型薄膜晶体管制备区109；其中，通过多灰阶光罩曝光工序依次形成所述无光刻胶区，N型薄膜晶体管制备区和P型薄膜晶体管制备区。
具体地说，根据位于衬底基板上的无光刻胶区的设计位置通过多灰阶光罩曝光工序进行曝光、显影、刻蚀以去除无光刻胶区的设计位置处的光刻胶层、扩散保护层和半导体层，以此形成无光刻胶区，相应地，该无光刻胶区一侧为P型薄膜晶体管制备区的设计位置，另一侧为N型薄膜晶体管制备区的设计位置，成为两个晶体管间的隔离区；所述N型薄膜晶体管制备区的设计位置和P型薄膜晶体管制备区的设计位置，采用双调掩膜板进行多灰阶光罩曝光工序，所述双调掩膜板对所述无光刻胶区不进行遮挡，此时，N型薄膜晶体管制备区的设计位置通过双调掩膜板上的半透膜进行部分曝光、显影、剥离后，其上的光刻胶层变薄，形成N型薄膜晶体管制备区；而双调掩膜板对P型薄膜晶体管制备区被双调掩膜板完全遮挡，使P型薄膜晶体管制备区的光刻胶层未被曝光、显影，剥离后，其厚度也保持不变，形成P型薄膜晶体管制备区。
本实施例中所述的无光刻胶区将用来制作薄膜晶体管的隔离区，通过形成隔离区的设计可以清晰定义出分别位于其两侧的N型薄膜晶体管制备区和P型薄膜晶体管制备区；其中，N型薄膜晶体管制备区将被用作N型薄膜晶体管的制作区域，P型薄膜晶体管制备区将被用作P型薄膜晶体管的制作区域。
4、参见图4所示，通过等离子体灰化工序去除N型薄膜晶体管制备区的光刻胶层；此时，经等离子体灰化后的P型薄膜晶体管制备区上的光刻胶层也相应变薄；
通过刻蚀工序去除N型薄膜晶体管制备区的扩散保护层；
通过光刻胶剥离工序去除P型薄膜晶体管制备区的光刻胶层；
在去除光刻胶层后的P型薄膜晶体管制备区内形成具有P型有源层106的P型薄膜晶体管。
5、参见图5所示，在氧气环境中对衬底基板进行高温退火氧化处理后，在N型薄膜晶体管制备区内形成完整的具有N型有源层的N型薄膜晶体管；具体地说，在氧化处理过程中由于有扩散保护层的保护，因此，位于P型薄膜晶体管制备区的P型薄膜晶体管没有经受氧化处理，其内的经过多灰阶光罩曝光工序后形成的P型有源层依旧保持为符合P型薄膜晶体管的特性的SnO。经氧化处理后的N型薄膜晶体管制备区内的半导体层，其材料由SnO被氧化成SnOx，其中1<x<2；使N型薄膜晶体管制备区内的半导体层的化学特性转变为符合N型薄膜晶体管特性，被用于制作N型薄膜晶体管中连接上层电极的N型有源层110；以此，在N型薄膜晶体管制备区内形成N型薄膜晶体管。
6、参见图6所示，在位于衬底基板上的无光刻胶区、P型薄膜晶体管制备区和N型薄膜晶体管制备区上设置钝化层111，钝化层完全覆盖于三者之上，并将无光刻胶区填充，使无光刻胶区、P型薄膜晶体管和N型薄膜晶体管具有同样高度，并可起到对包覆在其内的各器件进行隔离保护的作用，钝化层通常采用绝缘材料制成；按照设计要求通过光罩曝光工序对钝化层进行图形化处理，在钝化层上形成接触孔112；该接触孔分别设置在与位于P型薄膜晶体管制备区或N型薄膜晶体管制备区两侧的P型有源层或N型有源层相对应处的钝化层上；尤其是位于P型薄膜晶体管制备区处的接触孔，该接触孔穿过P型薄膜晶体管制备区两侧的扩散保护层，直通P型有源层；本实施例中所述钝化层可设置为单层也可设置为多层。所述钝化层采用热生长热生工序、常压化学气相沉积工序、低压化学气相沉积工序、等离子辅助体化学气相淀积工序、或溅射工艺其中一种制得。所述钝化层为SiOx或SiNx其中之一。
7、参见图7所示，在钝化层上通过溅射工艺设置上电极层，按照设计要求通过光罩曝光工序对上电极层进行图形化处理，形成按照预设计的分布图案分布的多个上层电极113；所述上层电极下部均伸入接触孔并与P型有源层或N型有源层接触导通。本实施例中所述上层电极为Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo或Au/Ti中任一材料；对通过上述步骤制备得到的互补型薄膜晶体管驱动背板在真空、氮气、或氧气的环境下进行退火处理的步骤；退火温度控制在120～450℃之间，退火时间控制在0.5～2小时之间；至此，互补型薄膜晶体管驱动背板制备完毕。
本发明只需通过在多灰阶光罩曝光工序中使用一次双调掩膜板对衬底基板进行部分曝光、显影，即可同时定义并形成N型薄膜晶体管制备区和P型薄膜晶体管制备区；以此可清晰的界定区分出如P型薄膜晶体管、N型薄膜晶体管及像素电极的制作区域；为之后的各器件的制作提供了可靠保障；使现有互补型薄膜晶体管驱动背板制造工序中由于各器件制作区域界定不清而导致的P型薄膜晶体管与N型薄膜晶体管相互干扰的问题得到了有效解决，使的由此产生的产品制造良率低的问题得到了有效改善；并且有效降低了制备成本；同时，利用P型薄膜晶体管制备区的扩散保护层作为高温退火氧化处理中P型有源层的掩膜板，可省去现有技术中需单独通过一次光罩曝光工序制造P型有源层的步骤；简化制备工序、提高生产良率、有效降低了生产升本。
本发明中通过上述制备方法制得的互补型薄膜晶体管驱动背板，其结构具体如下：
参见图7所示，互补型薄膜晶体管驱动背板有一个衬底基板，在该衬底基板上设置有多个P型薄膜晶体管制备区201、多个N型薄膜晶体管制备区202，以及设置在P型薄膜晶体管制备区与N型薄膜晶体管制备区之间的无光刻胶区203；所述P型薄膜晶体管制备区由下至上依次设有下层电极、连续生长介质层、P型有源层、扩散保护层和钝化层；P型有源层两侧设有与其接触的上层电极，该上层电极伸入所述钝化层上的接触孔内，其上端设有电极接引头204；其中，P型有源层和下层电极组成了P型薄膜晶体管。
所述N型薄膜晶体管制备区由下至上依次设有下层电极、连续生长介质层、N型有源层和钝化层；N型有源层两侧设有与其接触的上层电极，该上层电极伸入所述钝化层上的接触孔内，其上端设有电极接引头；其中，N型有源层和下层电极组成了N型薄膜晶体管。
所述无光刻胶区由下至上依次设有连续生长介质层和钝化层，其中无光刻胶区内的连续生长介质层两端分别与P型薄膜晶体管制备区和N型薄膜晶体管制备区内的连续生长介质层连接成一体，该无光刻胶区内的钝化层位于P型薄膜晶体管制备区中其中一个上层电极与与其相邻的N型薄膜晶体管制备区中另一个上层电极之间；无光刻胶区内的钝化层一侧将与其对应的所述N型有源层一侧压制于连续生长介质层上，另一侧将与其相对应的所述P型薄膜晶体管制备区一侧的扩散保护层连同P型有源层一同压制于连续生长介质层上。本实施例中在所述无光刻胶区上设有像素电极（属现有技术，图中未显示），该像素电极可以是有源矩阵发光有机电致显示管（OLED）中的阳极，也可以是有源矩阵液晶显示器（TFT-LCD）的像素电极；该像素电极通过与上层电极的电极接引头连接，分别与P型有源层和N型有源层连接。
本发明还提供一种显示装置，该显示装置包括如上述中所述的互补型薄膜晶体管驱动背板；该显示装置为有源矩阵发光有机电致显示管或有源矩阵液晶显示器；当显示装置为有源矩阵发光有机电致显示管时，在该互补型薄膜晶体管驱动背板上还设有有机电致发光层；当显示装置为有源矩阵液晶显示器时，在该互补型薄膜晶体管驱动背板上、下两侧还应分别设有液晶面板和背光模组。本实施例中关于有机电致发光层、液晶面板和背光模组的具体结构均属于现有技术，此处不再过多赘述。

Claims (8)

1.一种互补型薄膜晶体管驱动背板的制备方法，其特征在于：包括如下步骤：
S1、在衬底基板上形成下层电极；
S2、依次设置连续生长介质层、半导体层和扩散保护层；
S3、通过多灰阶光罩曝光工序形成无光刻胶区、N型薄膜晶体管制备区和P型薄膜晶体管制备区；
S4、通过等离子体灰化工序去除N型薄膜晶体管制备区的光刻胶层；
S5、去除N型薄膜晶体管制备区的扩散保护层；
S6、去除P型薄膜晶体管制备区的光刻胶层；形成具有P型有源层的P型薄膜晶体管；
S7、对衬底基板进行氧化处理；形成具有N型有源层的N型薄膜晶体管；
S8、在衬底基板上设置钝化层；
S9、在钝化层上形成上层电极；
其中，所述互补型薄膜晶体管驱动背板上具有相互独立的N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管的N型有源层两侧设有与所述N型有源层接触的上层电极作为所述N型薄膜晶体管的源极和漏极，所述P型薄膜晶体管的P型有源层两侧设有与所述P型有源层接触的上层电极作为所述P型薄膜晶体管的源极和漏极；
所述无光刻胶区上设有像素电极，所述像素电极通过上层电极分别与P型有源层和N型有源层连接。
2.如权利要求1所述互补型薄膜晶体管驱动背板的制备方法，其特征在于：还包括对制备后的互补型薄膜晶体管驱动背板进行退火处理的步骤。
3.如权利要求2所述的互补型薄膜晶体管驱动背板的制备方法，其特征在于：所述半导体层材料为SnO材料。
4.如权利要求3所述的互补型薄膜晶体管驱动背板的制备方法，其特征在于：经氧化处理后的N型薄膜晶体管制备区内的半导体层，其材料由SnO被氧化成SnOx，其中1<x<2；被用作N型薄膜晶体管中的N型有源层；而在氧化处理过程中，由于有扩散保护层的保护，因此P型薄膜晶体管的P型有源层没有经受氧化处理。
5.如权利要求4所述的互补型薄膜晶体管驱动背板的制备方法，其特征在于：所述步骤S2中所述半导体层采用溅射工艺、溶胶-凝胶工序、真空蒸镀工序、喷涂工序其中一种制得。
6.如权利要求5所述的互补型薄膜晶体管驱动背板的制备方法，其特征在于：在钝化层上通过溅射工艺设置上电极层，对上电极层进行图形化处理，形成多个上层电极。
7.一种如权利要求1-6其中之一所述制备方法制得的互补型薄膜晶体管驱动背板，其特征在于：有一个衬底基板，在该衬底基板上设置有多个P型薄膜晶体管制备区、多个N型薄膜晶体管制备区，以及设置在P型薄膜晶体管制备区与N型薄膜晶体管制备区之间的无光刻胶区；
其中，所述互补型薄膜晶体管驱动背板上具有相互独立的N型薄膜晶体管和P型薄膜晶体管，所述N型薄膜晶体管的N型有源层两侧设有与所述N型有源层接触的上层电极作为所述N型薄膜晶体管的源极和漏极，所述P型薄膜晶体管的P型有源层两侧设有与所述P型有源层接触的上层电极作为所述P型薄膜晶体管的源极和漏极；
所述无光刻胶区上设有像素电极，所述像素电极通过上层电极分别与P型有源层和N型有源层连接。
8.一种显示装置，其特征在于：包括如权利要求7所述的互补型薄膜晶体管驱动背板。
CN201310723714.0A 2013-12-24 2013-12-24 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置 Active CN103681515B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201310723714.0A CN103681515B (zh) 2013-12-24 2013-12-24 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置
PCT/CN2014/078571 WO2015096382A1 (zh) 2013-12-24 2014-05-27 互补型薄膜晶体管驱动背板及其制备方法、显示装置
US14/416,872 US9647014B2 (en) 2013-12-24 2014-05-27 Complementary thin film transistor driving back plate and preparing method thereof, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310723714.0A CN103681515B (zh) 2013-12-24 2013-12-24 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置

Publications (2)

Publication Number Publication Date
CN103681515A CN103681515A (zh) 2014-03-26
CN103681515B true CN103681515B (zh) 2016-06-22

Family

ID=50318651

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310723714.0A Active CN103681515B (zh) 2013-12-24 2013-12-24 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US9647014B2 (zh)
CN (1) CN103681515B (zh)
WO (1) WO2015096382A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681515B (zh) 2013-12-24 2016-06-22 京东方科技集团股份有限公司 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置
JP6942943B2 (ja) * 2016-07-22 2021-09-29 株式会社リコー 半導体素子の製造方法
CN106328592A (zh) * 2016-10-27 2017-01-11 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板和显示装置
KR102676341B1 (ko) * 2016-12-30 2024-06-17 엘지디스플레이 주식회사 박막 트랜지스터, 그의 제조방법, 및 그를 포함한 표시장치
CN108110088B (zh) * 2017-12-21 2020-11-10 苏州阿特斯阳光电力科技有限公司 太阳能电池的低压扩散工艺及利用其制备得到的太阳能电池
US11239399B2 (en) * 2019-02-05 2022-02-01 Facebook Technologies, Llc Architecture for hybrid TFT-based micro display projector

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102263134A (zh) * 2011-07-22 2011-11-30 北京大学深圳研究生院 一种双极性薄膜晶体管及其制备方法
CN102341912A (zh) * 2009-03-06 2012-02-01 佳能株式会社 半导体膜的形成方法、半导体器件的形成方法和半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000231346A (ja) * 1999-02-09 2000-08-22 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置
JP2008124408A (ja) * 2006-11-16 2008-05-29 Sony Corp 薄膜半導体装置の製造方法
CN103681515B (zh) 2013-12-24 2016-06-22 京东方科技集团股份有限公司 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102341912A (zh) * 2009-03-06 2012-02-01 佳能株式会社 半导体膜的形成方法、半导体器件的形成方法和半导体器件
CN102263134A (zh) * 2011-07-22 2011-11-30 北京大学深圳研究生院 一种双极性薄膜晶体管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Sputtering formation of p-type SnO thin-film transistors on glass toward oxide complimentary circuits;Hisato Yabuta等;《Applied physics letters》;20100818;第072111-1—072111-3 *

Also Published As

Publication number Publication date
WO2015096382A1 (zh) 2015-07-02
CN103681515A (zh) 2014-03-26
US9647014B2 (en) 2017-05-09
US20150325605A1 (en) 2015-11-12

Similar Documents

Publication Publication Date Title
CN103681515B (zh) 一种互补型薄膜晶体管驱动背板及其制备方法、显示装置
WO2019140733A1 (zh) 柔性amoled基板及其制作方法
CN102270656B (zh) 有机发光二极管显示器及其制造方法
US20160307929A1 (en) Manufacture method and structure of tft backplate applicable to amoled
WO2016026246A1 (zh) 薄膜晶体管及其制备方法、阵列基板及其制备方法和显示装置
CN102654698B (zh) 液晶显示器阵列基板及其制造方法、液晶显示器
WO2017121012A1 (zh) 一种阵列基板及其制备方法
CN103745955B (zh) 显示装置、阵列基板及其制造方法
US9825069B2 (en) Array substrate manufacturing method
CN105304500B (zh) N型tft的制作方法
US20190027612A1 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
CN107359177A (zh) 一种柔性背板的制作方法、液晶显示面板以及oled显示面板
US11152490B2 (en) Array substrate and method for manufacturing same
WO2017000335A1 (zh) Tft背板的制作方法及其结构
WO2015100859A1 (zh) 阵列基板及其制造方法和显示装置
WO2021120378A1 (zh) 一种阵列基板及其制作方法
KR100847846B1 (ko) 국부 도핑을 이용한 박막트랜지스터의 제조 방법
US10629746B2 (en) Array substrate and manufacturing method thereof
WO2019210602A1 (zh) 阵列基板及其制造方法、显示面板
CN104022129A (zh) 显示器件的阵列基板及其制备方法
KR102037514B1 (ko) 평판 표시장치용 박막 트랜지스터 기판 및 그 제조 방법
TWI574322B (zh) 薄膜電晶體、其製造方法、具有該薄膜電晶體之顯示裝置及製造該顯示裝置之方法
KR20110066452A (ko) 패턴 형성 방법 및 박막 트랜지스터 어레이 기판의 제조 방법
US10366636B2 (en) Manufacturing method of flexible backplate, liquid crystal display panel, and organic light-emitting diodedisplay panel
KR100539583B1 (ko) 실리콘의 결정화 방법 및 이를 이용한 박막트랜지스터제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant