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WO2017000335A1 - Tft背板的制作方法及其结构 - Google Patents

Tft背板的制作方法及其结构 Download PDF

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Publication number
WO2017000335A1
WO2017000335A1 PCT/CN2015/085154 CN2015085154W WO2017000335A1 WO 2017000335 A1 WO2017000335 A1 WO 2017000335A1 CN 2015085154 W CN2015085154 W CN 2015085154W WO 2017000335 A1 WO2017000335 A1 WO 2017000335A1
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layer
island
source
shaped active
polysilicon
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PCT/CN2015/085154
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English (en)
French (fr)
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张晓星
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深圳市华星光电技术有限公司
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Priority to US14/781,309 priority Critical patent/US9735186B2/en
Publication of WO2017000335A1 publication Critical patent/WO2017000335A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT backplane and a structure thereof.
  • OLED organic light emitting diodes
  • OLEDs can be classified into passive OLEDs (PMOLEDs) and active OLEDs (AMOLEDs) according to the type of driving.
  • the AMOLED is usually composed of a Low Temperature Poly-Silicon (LTPS) TFT backplane and an electroluminescent layer.
  • LTPS Low Temperature Poly-Silicon
  • Low-temperature polysilicon has high electron mobility and strong driving ability.
  • low-temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio and low energy consumption.
  • the common processes for making low-temperature polysilicon are Excimer Laser Annealing (ELA), Solid Phase Crystallization (SPC), etc.
  • ELA Excimer Laser Annealing
  • SPC Solid Phase Crystallization
  • SPC technology is easy and has a larger size due to its large size.
  • the high cost advantage has become a hot research topic.
  • SPC technology is further divided into direct high temperature long-time heating baking method and ion induction method.
  • the ion-inducing mode induces amorphous silicon crystallization by implanting specific ions.
  • the conventional SPC-based TFT backplane manufacturing method generally includes the following steps:
  • Step 1 as shown in FIG. 1, a substrate 100 is provided, on which a buffer layer 200 and an amorphous silicon (a-Si) layer 300 are sequentially deposited;
  • a-Si amorphous silicon
  • Step 2 As shown in FIG. 2, the amorphous silicon (a-Si) layer 300 is implanted with induced ions, and then baked at a high temperature to rapidly crystallize the amorphous silicon to form a poly-Si layer 300'.
  • the upper layer portion 310 of the polysilicon layer 300' has more implanted induced ions, and the lower layer portion is a semiconductor layer 320 having relatively pure polysilicon;
  • Step 3 as shown in Figure 3, the upper layer portion 310 of the polysilicon layer 300' is etched away, leaving a semiconductor layer 320 with relatively pure polysilicon;
  • Step 4 as shown in FIG. 4, the semiconductor layer 320 is patterned by using a photomask. Forming an island-shaped active layer 400;
  • Step 5 as shown in FIG. 5, first coating the photoresist, patterning the photoresist through a mask, and then using the photoresist pattern 500 as a shielding layer, implanting dopant ions into the island-shaped active layer 400, The doped ions are implanted into the source region/drain contact region 401 on both sides of the island-shaped active layer 400, and the doped ions are not implanted into the channel region 402 in the middle of the island-shaped active layer 400;
  • Step 6 as shown in FIG. 6 and FIG. 7, after the photoresist pattern 500 is removed, the gate insulating layer 700, the gate electrode 800, the interlayer insulating layer 900, and the source/drain 1000 are sequentially formed, and the source/drain electrodes 1000 and The source/drain contact regions 401 are in contact to complete the fabrication of the low temperature polysilicon TFT backplane.
  • the above-mentioned conventional SPC-based TFT backplane manufacturing method needs to etch away the upper layer portion 310 having more implanted induced ions after implanting induced ions to crystallize the amorphous silicon to form the polysilicon layer 300'.
  • the semiconductor layer 320 is patterned by a photomask to form the island-shaped active layer 400; subsequently, since the source/drain contact region 401 needs to be formed, it is necessary to use another
  • the mask is used to form the photoresist pattern 500, and the dopant ions are formed on both sides of the island-shaped active layer 400 with the photoresist pattern 500 as a shielding layer to form a source/drain contact region 401.
  • the process requires not only a large number of masks, but also two ion implantations, which are costly to produce.
  • Another object of the present invention is to provide a TFT backplane structure which is simple in process and low in production cost.
  • the present invention firstly provides a method for fabricating a TFT backplane. After implanting an amorphous silicon layer into an induced ion solid phase to form a polysilicon layer, the polysilicon layer is patterned by using a halftone mask. While forming the island-shaped active layer, the upper portion of the island-shaped active layer having more implanted induced ions is etched away to form a channel region, which is more on both sides of the island-shaped active layer. The upper portion of the implanted induced ions remains as a source/drain contact region.
  • the manufacturing method of the TFT backplane includes the following steps:
  • Step 1 providing a substrate, sequentially depositing a buffer layer and an amorphous silicon layer on the substrate;
  • Step 2 implanting an induced ion into the amorphous silicon layer, and then baking at a high temperature to rapidly solidify the amorphous silicon to form a polysilicon layer, wherein the upper portion of the polysilicon layer has more implanted induced ions, and the lower portion is a semiconductor layer having relatively pure polysilicon;
  • Step 3 patterning the polysilicon layer by using a halftone mask to form an island active layer
  • the upper portion of the central portion of the island-shaped active layer is etched away to form a channel region, and the upper portion on both sides of the island-shaped active layer is left as a source/drain contact region;
  • Step 4 sequentially forming a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source/drain on the island-shaped active layer and the buffer layer, wherein the source/drain are in contact with the source/drain contact regions.
  • the substrate is a glass substrate.
  • the induced ions implanted in the amorphous silicon layer in the step 2 are boron ions or nickel ions.
  • the step 3 specifically includes:
  • Step 31 Apply a photoresist layer on the upper portion of the polysilicon layer, and use a halftone mask to fully expose the photoresist layer corresponding to the region outside the island-shaped active layer, and correspondingly cover the The photoresist layer in the channel region region is subjected to half exposure, and the photoresist layer corresponding to the region covering the source/drain contact region is not exposed to form a photoresist layer pattern;
  • Step 32 etching a polysilicon layer not covered by the photoresist layer pattern to form an island-shaped active layer
  • Step 33 first removing the half-exposed portion of the photoresist layer pattern, and etching away the upper portion of the exposed polysilicon layer to form a channel region;
  • Step 34 removing the unexposed portion of the photoresist layer pattern, leaving the upper portion of the polysilicon layer covered by the unexposed portion of the photoresist layer pattern to form a source/drain contact region.
  • the buffer layer, the gate insulating layer, and the material of the interlayer insulating layer are silicon nitride, silicon oxide, or a combination of both.
  • the gate, the source/drain material is a combination of one or more of molybdenum, titanium, aluminum, copper.
  • the present invention also provides a method for fabricating a TFT backplane. After implanting an induced silicon solid layer into a polysilicon layer by implanting an amorphous silicon layer, the polysilicon layer is patterned by a halftone mask to form an island active. Simultaneously, the upper portion of the island-shaped active layer with more implanted induced ions is etched away to form a channel region, and more implanted ions are implanted on both sides of the island-shaped active layer. The upper portion remains as a source/drain contact region;
  • Step 1 providing a substrate, sequentially depositing a buffer layer and an amorphous silicon layer on the substrate;
  • Step 2 implanting an induced ion into the amorphous silicon layer, and then baking at a high temperature to rapidly solidify the amorphous silicon to form a polysilicon layer, wherein the upper portion of the polysilicon layer has more implanted induced ions, and the lower portion is a semiconductor layer having relatively pure polysilicon;
  • Step 3 using a halftone mask to pattern the polysilicon layer to form an island-shaped active layer, while etching the upper portion of the central portion of the island-shaped active layer to form a channel region, which will be located in an island-like active region.
  • the upper portion of the layer remains as a source/drain contact region;
  • Step 4 sequentially forming a gate insulating layer, a gate, and an interlayer on the island-shaped active layer and the buffer layer a source layer and a source/drain, the source/drain being in contact with the source/drain contact regions;
  • the substrate is a glass substrate
  • the induced ions implanted in the amorphous silicon layer in the step 2 are boron ions or nickel ions.
  • the invention also provides a TFT backplane structure, comprising:
  • a buffer layer disposed on the substrate
  • a gate insulating layer a gate electrode, an interlayer insulating layer, and a source/drain provided on the island-shaped active layer and the buffer layer;
  • the source/drain are in contact with the source/drain contact regions.
  • the substrate is a glass substrate; the buffer layer, the gate insulating layer, and the material of the interlayer insulating layer are silicon nitride, silicon oxide, or a combination of the two.
  • the gate, the source/drain material is a combination of one or more of molybdenum, titanium, aluminum, copper.
  • a method for fabricating a TFT backplane is characterized in that a polycrystalline silicon layer is patterned by using a halftone mask after implanting an amorphous silicon layer into an induced ion solid phase to form a polycrystalline silicon layer. While forming the island-shaped active layer, the upper portion of the island-shaped active layer having more implanted induced ions is etched away to form a channel region, which will be located on both sides of the island-shaped active layer. The upper portion of the multi-implanted induced ions remains as a source/drain contact region, which reduces the number of masks and eliminates the need to separately implant dopant ions into the source/drain contact regions, thereby simplifying the process.
  • the present invention provides a TFT backplane structure in which an island-shaped active layer has a shape of convex on both sides and a central recess, and both sides of the island-shaped active layer include an upper portion having more implanted induced ions. And a lower layer portion having a relatively pure polysilicon as a semiconductor layer, the upper portion forming a source/drain contact region; the middle portion of the island-shaped active layer including only a lower portion to form a channel region; the TFT back plate structure
  • the process is simple and the production cost is low.
  • step 1 is a schematic diagram of step 1 of a conventional method for fabricating a TFT backplane based on SPC technology
  • step 2 is a schematic diagram of step 2 of a conventional method for fabricating a TFT backplane based on SPC technology
  • step 3 is a schematic diagram of step 3 of a conventional method for fabricating a TFT backplane based on SPC technology
  • step 4 is a schematic diagram of step 4 of a conventional method for fabricating a TFT backplane based on SPC technology
  • step 5 is a schematic diagram of step 5 of a conventional method for fabricating a TFT backplane based on SPC technology
  • FIG. 6 and FIG. 7 are schematic diagrams of step 6 of a conventional method for fabricating a TFT backplane based on SPC technology
  • FIG. 8 is a flow chart of a method of fabricating a TFT backplane of the present invention.
  • step 9 is a schematic diagram of step 1 of a method for fabricating a TFT backplane according to the present invention.
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT backplane according to the present invention
  • FIG. 11 and FIG. 12 are schematic diagrams showing the third step of the method for fabricating the TFT backplane of the present invention.
  • FIG. 13 and FIG. 14 are schematic diagrams showing the step 4 of the method for fabricating the TFT backplane of the present invention.
  • FIG. 14 is also a schematic diagram of the TFT backplane structure of the present invention.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 as shown in FIG. 9, a substrate 1 is provided, on which a buffer layer 2 and an amorphous silicon layer 3 are sequentially deposited.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • the material of the buffer layer 2 is a combination of silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • Step 2 As shown in FIG. 10, the amorphous silicon layer 3 is implanted with induced ions, and then baked at a high temperature to rapidly solidify the amorphous silicon to form a polycrystalline silicon layer 3'.
  • the induced ions implanted in the amorphous silicon layer 3 in the step 2 are boron (B) ions or nickel (Ni). ion.
  • Step 3 as shown in FIG. 11 and FIG. 12, the polysilicon layer 3' is patterned by a halftone mask to form the island-shaped active layer 4, and the upper layer portion 31 located in the middle of the island-shaped active layer 4 is formed. Etching away, a channel region is formed, and the upper portion 31 on both sides of the island-shaped active layer 4 is left as a source/drain contact region.
  • step 3 specifically includes:
  • Step 31 applying a photoresist layer on the upper layer portion 31 of the polysilicon layer 3', and using a halftone mask to fully expose the photoresist layer corresponding to the region outside the island-shaped active layer 4,
  • the photo-resist layer covering the region of the channel region is subjected to half exposure, and the photoresist layer corresponding to the region of the source/drain contact region is not exposed to form a photoresist layer pattern 5;
  • Step 32 etching the polysilicon layer 3' not covered by the photoresist layer pattern 5 to form an island-shaped active layer 4;
  • Step 33 first removing the half-exposed portion of the photoresist layer pattern 5, and etching away the upper portion 31 of the exposed polysilicon layer 3' to form a channel region;
  • Step 34 removing the unexposed portion in the photoresist layer pattern 5, leaving the upper portion 31 of the polysilicon layer 3' covered by the unexposed portion in the photoresist layer pattern 5, forming a source/drain contact region.
  • Step 4 as shown in FIG. 13 and FIG. 14, the gate insulating layer 6, the gate electrode 7, the interlayer insulating layer 8, and the source/drain electrodes 9 are sequentially formed on the island-shaped active layer 4 and the buffer layer 2.
  • the source/drain 9 is in contact with the source/drain contact region 42.
  • the material of the gate insulating layer 6 and the interlayer insulating layer 8 is SiNx, SiOx, or a combination of the two.
  • the material of the gate electrode 7 and the source/drain electrodes 9 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • the polysilicon layer 3' is patterned by a halftone mask to form an island shape. Simultaneously with the active layer 4, the upper portion 31 having more implanted induced ions in the middle of the island-shaped active layer 4 is etched away to form a channel region which will be located on both sides of the island-shaped active layer 4.
  • the multi-implanted induced ion upper portion 31 remains as a source/drain contact region, which reduces the number of masks and eliminates the need to separately implant dopant ions into the source/drain contact regions, thereby simplifying Process, reducing production costs.
  • the present invention further provides a TFT backplane structure, as shown in FIG. 14, comprising:
  • the shape of the island-shaped active layer 4 includes an upper layer portion 31 having a larger amount of implanted ions and a lower layer portion 32 having a relatively pure polysilicon as a semiconductor layer.
  • the upper layer portion 31 forms a source/drain contact region; the middle portion of the island-shaped active layer 4 includes only the lower layer portion 32 to form a channel region;
  • the source/drain 9 is in contact with the source/drain contact region 42.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • the buffer layer 2, the gate insulating layer 6, and the material of the interlayer insulating layer 8 are SiNx, SiOx, or a stack combination of the two.
  • the gate 7 and the material of the source/drain 9 are combined in a stack of one or more of Mo, Ti, Al, and Cu.
  • the TFT backplane structure has a simple process and a low production cost.
  • the polysilicon layer is patterned by a halftone mask to form an island shape.
  • the upper layer portion of the island-shaped active layer having more implanted induced ions is etched away to form a channel region, and more implants are provided on both sides of the island-shaped active layer.
  • the upper portion of the induced ions remains as a source/drain contact region, which reduces the number of masks and eliminates the need to separately implant dopant ions into the source/drain contact regions, thereby simplifying the process and reducing production costs. .
  • the island-shaped active layer has a shape of convex on both sides and a concave shape in the middle, and both sides of the island-shaped active layer include an upper layer portion having more implanted induced ions and having Pure polysilicon, as a lower portion of the semiconductor layer, the upper portion forms a source/drain contact region; the middle portion of the island-shaped active layer includes only a lower portion to form a channel region; the TFT backplane structure is simple in process Production costs are lower.

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  • Thin Film Transistor (AREA)

Abstract

一种TFT背板的制作方法及其结构。该TFT背板的制作方法，在通过对非晶硅层(3)植入诱导离子固相结晶成多晶硅层(3')后，利用半色调光罩对多晶硅层(3')进行图案化处理，形成岛状有源层(4)的同时，将位于岛状有源层(4)中部的具有较多植入的诱导离子的上层部分(31)蚀刻掉，形成沟道区(32)，将位于岛状有源层(4)两侧的具有较多植入的诱导离子的上层部分(31)保留下来成为源/漏极接触区，既减少了光罩数量，又省去了单独对源/漏极接触区植入掺杂离子的工艺，从而能够简化制程，降低生产成本。

Description

TFT背板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT背板的制作方法及其结构。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。其中，AMOLED通常是由低温多晶硅(Low Temperature Poly-Silicon，LTPS)TFT背板和电激发光层组成自发光组件。低温多晶硅具有较高的电子迁移率，较强的驱动能力，对AMOLED而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点。
制作低温多晶硅的常用工艺主要有准分子激光退火晶化(Excimer Laser Annealing，ELA)、固相诱导晶化(Solid Phase Crystallization，SPC)、等，其中，SPC技术由于其大尺寸化容易且具有较高的成本优势，成为当前的研究热点。SPC技术又分为直接高温长时间加热烘烤方式和离子诱导方式。离子诱导方式通过植入特定的离子诱导非晶硅结晶。
传统的基于SPC技术的TFT背板的制作方法大体包括如下步骤：
步骤1、如图1所示，提供一基板100，在该基板100上依次沉积缓冲层200、与非晶硅(a-Si)层300；
步骤2、如图2所示，对非晶硅(a-Si)层300植入诱导离子，然后进行高温烘烤，使非晶硅快速结晶，形成多晶硅(poly-Si)层300’，该多晶硅层300’的上层部分310具有较多植入的诱导离子，下层部分为具有较纯净的多晶硅的半导体层320；
步骤3、如图3所示，将多晶硅层300’的上层部分310蚀刻掉，保留具有较纯净的多晶硅的半导体层320；
步骤4、如图4所示，利用一道光罩对半导体层320进行图案化处理， 形成岛状有源层400；
步骤5、如图5所示，先涂布光阻，通过一道光罩对光阻进行图案化处理，再以光阻图案500为遮蔽层，对岛状有源层400植入掺杂离子，使得岛状有源层400的两侧经植入掺杂离子成为源/漏极接触区401，而岛状有源层400的中部未植入掺杂离子成为沟道区402；
步骤6、如图6、图7所示，去除光阻图案500后，依次制作栅极绝缘层700、栅极800、层间绝缘层900、及源/漏极1000，源/漏极1000与源/漏极接触区401接触，完成低温多晶硅TFT背板的制作。
可见，上述传统的基于SPC技术的TFT背板的制作方法在植入诱导离子使非晶硅结晶形成多晶硅层300’后，需要将其具有较多植入的诱导离子的上层部分310蚀刻掉，以保留具有较纯净的多晶硅的半导体层320；然后利用一道光罩对半导体层320进行图案化处理，形成岛状有源层400；后续因为需要制作源/漏极接触区401，必需再使用一道光罩制作光阻图案500，以光阻图案500为遮蔽层对岛状有源层400的两侧植入掺杂离子形成源/漏极接触区401。该制程过程不仅需要的光罩数量较多，还需要两次离子植入，生产成本较高。
发明内容
本发明的目的在于提供一种TFT背板的制作方法，能够简化制程，降低生产成本。
本发明的目的还在于提供一种TFT背板结构，其制程简单、生产成本较低。
为实现上述目的，本发明首先提供一种TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区。
所述的TFT背板的制作方法包括如下步骤：
步骤1、提供一基板，在该基板上依次沉积缓冲层、与非晶硅层；
步骤2、对非晶硅层植入诱导离子，然后进行高温烘烤，使非晶硅快速固相结晶，形成多晶硅层，该多晶硅层的上层部分具有较多植入的诱导离子，下层部分为具有较纯净的多晶硅的半导体层；
步骤3、利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层 的同时，将位于岛状有源层中部的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的上层部分保留下来成为源/漏极接触区；
步骤4、在岛状有源层与缓冲层上依次制作栅极绝缘层、栅极、层间绝缘层、及源/漏极，所述源/漏极与源/漏极接触区接触。
所述基板为玻璃基板。
所述步骤2对非晶硅层植入的诱导离子为硼离子或镍离子。
所述步骤3具体包括：
步骤31、在所述多晶硅层的上层部分上涂布一层光阻层，使用半色调光罩将对应覆盖所述岛状有源层以外区域的光阻层进行全曝光，将对应覆盖所述沟道区区域的光阻层进行半曝光，将对应覆盖所述源/漏极接触区区域的光阻层不进行曝光，形成光阻层图案；
步骤32、将未被光阻层图案覆盖的多晶硅层蚀刻掉，形成岛状有源层；
步骤33、先去除光阻层图案中的半曝光部分，再将暴露出来的多晶硅层的上层部分蚀刻掉，形成沟道区；
步骤34、去除光阻层图案中的未曝光部分，保留被光阻层图案中的未曝光部分覆盖的多晶硅层的上层部分，形成源/漏极接触区。
所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氮化硅、氧化硅、或二者的堆栈组合。
所述栅极、与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区；
其中，包括如下步骤：
步骤1、提供一基板，在该基板上依次沉积缓冲层、与非晶硅层；
步骤2、对非晶硅层植入诱导离子，然后进行高温烘烤，使非晶硅快速固相结晶，形成多晶硅层，该多晶硅层的上层部分具有较多植入的诱导离子，下层部分为具有较纯净的多晶硅的半导体层；
步骤3、利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的上层部分保留下来成为源/漏极接触区；
步骤4、在岛状有源层与缓冲层上依次制作栅极绝缘层、栅极、层间绝 缘层、及源/漏极，所述源/漏极与源/漏极接触区接触；
其中，所述基板为玻璃基板；
其中，所述步骤2对非晶硅层植入的诱导离子为硼离子或镍离子。
本发明还提供一种TFT背板结构，包括：
基板；
设于所述基板上的缓冲层；
设于所述缓冲层上的岛状有源层；所述岛状有源层由非晶硅层植入诱导离子形成多晶硅层后，再利用半色调光罩进行图案化处理得到，其呈两侧凸起、中部凹陷的形状；所述岛状有源层的两侧包括具有较多植入的诱导离子的上层部分和具有较纯净的多晶硅、作为半导体层的下层部分，所述上层部分形成源/漏极接触区；所述岛状有源层的中部仅包括下层部分，形成沟道区；
依次设于所述岛状有源层与缓冲层上的栅极绝缘层、栅极、层间绝缘层、及源/漏极；
所述源/漏极与源/漏极接触区接触。
所述基板为玻璃基板；所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氮化硅、氧化硅、或二者的堆栈组合。
所述栅极、与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明提供的一种TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区，既减少了光罩数量，又省去了单独对源/漏极接触区植入掺杂离子的工艺，从而能够简化制程，降低生产成本。本发明提供的一种TFT背板结构，其岛状有源层呈两侧凸起、中部凹陷的形状，所述岛状有源层的两侧包括具有较多植入的诱导离子的上层部分和具有较纯净的多晶硅、作为半导体层的下层部分，所述上层部分形成源/漏极接触区；所述岛状有源层的中部仅包括下层部分，形成沟道区；该TFT背板结构的制程简单、生产成本较低。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为传统的基于SPC技术的TFT背板的制作方法的步骤1的示意图；
图2为传统的基于SPC技术的TFT背板的制作方法的步骤2的示意图；
图3为传统的基于SPC技术的TFT背板的制作方法的步骤3的示意图；
图4为传统的基于SPC技术的TFT背板的制作方法的步骤4的示意图；
图5为传统的基于SPC技术的TFT背板的制作方法的步骤5的示意图；
图6、图7为传统的基于SPC技术的TFT背板的制作方法的步骤6的示意图；
图8为本发明的TFT背板的制作方法的流程图；
图9为本发明的TFT背板的制作方法的步骤1的示意图；
图10为本发明的TFT背板的制作方法的步骤2的示意图；
图11、图12为本发明的TFT背板的制作方法的步骤3的示意图；
图13、图14为本发明的TFT背板的制作方法的步骤4的示意图；图14同时为本发明的TFT背板结构的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图8，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、如图9所示，提供一基板1，在该基板1上依次沉积缓冲层2、与非晶硅层3。
具体地，所述基板1为透明基板，优选的，所述基板1为玻璃基板。
所述缓冲层2的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的堆栈组合。
步骤2、如图10所示，对非晶硅层3植入诱导离子，然后进行高温烘烤，使非晶硅快速固相结晶，形成多晶硅层3’，该多晶硅层3’的上层部分31具有较多植入的诱导离子，下层部分32为具有较纯净的多晶硅的半导体层。
具体地，该步骤2对非晶硅层3植入的诱导离子为硼(B)离子或镍(Ni) 离子。
步骤3、如图11、图12所示，利用半色调光罩对多晶硅层3’进行图案化处理，形成岛状有源层4的同时，将位于岛状有源层4中部的上层部分31蚀刻掉，形成沟道区，将位于岛状有源层4两侧的上层部分31保留下来成为源/漏极接触区。
进一步地，该步骤3具体包括：
步骤31、在所述多晶硅层3’的上层部分31上涂布一层光阻层，使用半色调光罩将对应覆盖所述岛状有源层4以外区域的光阻层进行全曝光，将对应覆盖所述沟道区区域的光阻层进行半曝光，将对应覆盖所述源/漏极接触区区域的光阻层不进行曝光，形成光阻层图案5；
步骤32、将未被光阻层图案5覆盖的多晶硅层3’蚀刻掉，形成岛状有源层4；
步骤33、先去除光阻层图案5中的半曝光部分，再将暴露出来的多晶硅层3’的上层部分31蚀刻掉，形成沟道区；
步骤34、去除光阻层图案5中的未曝光部分，保留被光阻层图案5中的未曝光部分覆盖的多晶硅层3’的上层部分31，形成源/漏极接触区。
步骤4、如图13、图14所示，在岛状有源层4与缓冲层2上依次制作栅极绝缘层6、栅极7、层间绝缘层8、及源/漏极9，所述源/漏极9与源/漏极接触区42接触。
具体地，所述栅极绝缘层6、与层间绝缘层8的材料为SiNx、SiOx、或二者的堆栈组合。
所述栅极7、与源/漏极9的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
本发明的TFT背板的制作方法，在通过对非晶硅层3植入诱导离子固相结晶成多晶硅层3’后，利用半色调光罩对多晶硅层3’进行图案化处理，形成岛状有源层4的同时，将位于岛状有源层4中部的具有较多植入的诱导离子的上层部分31蚀刻掉，形成沟道区，将位于岛状有源层4两侧的具有较多植入的诱导离子的上层部分31保留下来成为源/漏极接触区，既减少了光罩数量，又省去了单独对源/漏极接触区植入掺杂离子的工艺，从而能够简化制程，降低生产成本。
在上述TFT背板的制作方法的基础上，本发明还提供一种TFT背板结构，如图14所示，包括：
基板1；
设于所述基板1上的缓冲层2；
设于所述缓冲层2上的岛状有源层4；所述岛状有源层4由非晶硅层植入诱导离子形成多晶硅层后，再利用半色调光罩进行图案化处理得到，其呈两侧凸起、中部凹陷的形状；所述岛状有源层4的两侧包括具有较多植入的诱导离子的上层部分31和具有较纯净的多晶硅、作为半导体层的下层部分32，所述上层部分31形成源/漏极接触区；所述岛状有源层4的中部仅包括下层部分32，形成沟道区；
依次设于所述岛状有源层4与缓冲层2上的栅极绝缘层6、栅极7、层间绝缘层8、及源/漏极9；
所述源/漏极9与源/漏极接触区42接触。
具体地，所述基板1为透明基板，优选的，所述基板1为玻璃基板。
所述缓冲层2、栅极绝缘层6、与层间绝缘层8的材料为SiNx、SiOx、或二者的堆栈组合。
所述栅极7、与源/漏极9的材料为Mo、Ti、Al、Cu中的一种或多种的堆栈组合。
该TFT背板结构的制程简单、生产成本较低。
综上所述，本发明的TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区，既减少了光罩数量，又省去了单独对源/漏极接触区植入掺杂离子的工艺，从而能够简化制程，降低生产成本。本发明的TFT背板结构，其岛状有源层呈两侧凸起、中部凹陷的形状，所述岛状有源层的两侧包括具有较多植入的诱导离子的上层部分和具有较纯净的多晶硅、作为半导体层的下层部分，所述上层部分形成源/漏极接触区；所述岛状有源层的中部仅包括下层部分，形成沟道区；该TFT背板结构的制程简单、生产成本较低。
综上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区。
  2. 如权利要求1所述的TFT背板的制作方法，其中，包括如下步骤：
    步骤1、提供一基板，在该基板上依次沉积缓冲层、与非晶硅层；
    步骤2、对非晶硅层植入诱导离子，然后进行高温烘烤，使非晶硅快速固相结晶，形成多晶硅层，该多晶硅层的上层部分具有较多植入的诱导离子，下层部分为具有较纯净的多晶硅的半导体层；
    步骤3、利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的上层部分保留下来成为源/漏极接触区；
    步骤4、在岛状有源层与缓冲层上依次制作栅极绝缘层、栅极、层间绝缘层、及源/漏极，所述源/漏极与源/漏极接触区接触。
  3. 如权利要求2所述的TFT背板的制作方法，其中，所述基板为玻璃基板。
  4. 如权利要求2所述的TFT背板的制作方法，其中，所述步骤2对非晶硅层植入的诱导离子为硼离子或镍离子。
  5. 如权利要求2所述的TFT背板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述多晶硅层的上层部分上涂布一层光阻层，使用半色调光罩将对应覆盖所述岛状有源层以外区域的光阻层进行全曝光，将对应覆盖所述沟道区区域的光阻层进行半曝光，将对应覆盖所述源/漏极接触区区域的光阻层不进行曝光，形成光阻层图案；
    步骤32、将未被光阻层图案覆盖的多晶硅层蚀刻掉，形成岛状有源层；
    步骤33、先去除光阻层图案中的半曝光部分，再将暴露出来的多晶硅层的上层部分蚀刻掉，形成沟道区；
    步骤34、去除光阻层图案中的未曝光部分，保留被光阻层图案中的未曝光部分覆盖的多晶硅层的上层部分，形成源/漏极接触区。
  6. 如权利要求2所述的TFT背板的制作方法，其中，所述缓冲层、栅 极绝缘层、与层间绝缘层的材料为氮化硅、氧化硅、或二者的堆栈组合。
  7. 如权利要求2所述的TFT背板的制作方法，其中，所述栅极、与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  8. 一种TFT背板的制作方法，在通过对非晶硅层植入诱导离子固相结晶成多晶硅层后，利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的具有较多植入的诱导离子的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的具有较多植入的诱导离子的上层部分保留下来成为源/漏极接触区；
    其中，包括如下步骤：
    步骤1、提供一基板，在该基板上依次沉积缓冲层、与非晶硅层；
    步骤2、对非晶硅层植入诱导离子，然后进行高温烘烤，使非晶硅快速固相结晶，形成多晶硅层，该多晶硅层的上层部分具有较多植入的诱导离子，下层部分为具有较纯净的多晶硅的半导体层；
    步骤3、利用半色调光罩对多晶硅层进行图案化处理，形成岛状有源层的同时，将位于岛状有源层中部的上层部分蚀刻掉，形成沟道区，将位于岛状有源层两侧的上层部分保留下来成为源/漏极接触区；
    步骤4、在岛状有源层与缓冲层上依次制作栅极绝缘层、栅极、层间绝缘层、及源/漏极，所述源/漏极与源/漏极接触区接触；
    其中，所述基板为玻璃基板；
    其中，所述步骤2对非晶硅层植入的诱导离子为硼离子或镍离子。
  9. 如权利要求8所述的TFT背板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述多晶硅层的上层部分上涂布一层光阻层，使用半色调光罩将对应覆盖所述岛状有源层以外区域的光阻层进行全曝光，将对应覆盖所述沟道区区域的光阻层进行半曝光，将对应覆盖所述源/漏极接触区区域的光阻层不进行曝光，形成光阻层图案；
    步骤32、将未被光阻层图案覆盖的多晶硅层蚀刻掉，形成岛状有源层；
    步骤33、先去除光阻层图案中的半曝光部分，再将暴露出来的多晶硅层的上层部分蚀刻掉，形成沟道区；
    步骤34、去除光阻层图案中的未曝光部分，保留被光阻层图案中的未曝光部分覆盖的多晶硅层的上层部分，形成源/漏极接触区。
  10. 如权利要求8所述的TFT背板的制作方法，其中，所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氮化硅、氧化硅、或二者的堆栈组合。
  11. 如权利要求8所述的TFT背板的制作方法，其中，所述栅极、与 源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  12. 一种TFT背板结构，包括：
    基板；
    设于所述基板上的缓冲层；
    设于所述缓冲层上的岛状有源层；所述岛状有源层由非晶硅层植入诱导离子形成多晶硅层后，再利用半色调光罩进行图案化处理得到，其呈两侧凸起、中部凹陷的形状；所述岛状有源层的两侧包括具有较多植入的诱导离子的上层部分和具有较纯净的多晶硅、作为半导体层的下层部分，所述上层部分形成源/漏极接触区；所述岛状有源层的中部仅包括下层部分，形成沟道区；
    依次设于所述岛状有源层与缓冲层上的栅极绝缘层、栅极、层间绝缘层、及源/漏极；
    所述源/漏极与源/漏极接触区接触。
  13. 如权利要求12所述的TFT背板结构，其中，所述基板为玻璃基板；所述缓冲层、栅极绝缘层、与层间绝缘层的材料为氮化硅、氧化硅、或二者的堆栈组合。
  14. 如权利要求12所述的TFT背板结构，其中，所述栅极、与源/漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
PCT/CN2015/085154 2015-07-01 2015-07-27 Tft背板的制作方法及其结构 WO2017000335A1 (zh)

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