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WO2015096382A1 - 互补型薄膜晶体管驱动背板及其制备方法、显示装置 - Google Patents

互补型薄膜晶体管驱动背板及其制备方法、显示装置 Download PDF

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WO2015096382A1
WO2015096382A1 PCT/CN2014/078571 CN2014078571W WO2015096382A1 WO 2015096382 A1 WO2015096382 A1 WO 2015096382A1 CN 2014078571 W CN2014078571 W CN 2014078571W WO 2015096382 A1 WO2015096382 A1 WO 2015096382A1
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thin film
film transistor
layer
type thin
preparation
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PCT/CN2014/078571
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English (en)
French (fr)
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刘晓娣
王刚
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京东方科技集团股份有限公司
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Priority to US14/416,872 priority Critical patent/US9647014B2/en
Publication of WO2015096382A1 publication Critical patent/WO2015096382A1/zh

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    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a complementary thin film transistor driving backplane and a method of fabricating the same Display device.
  • TFT Thin-Film Transistor
  • IGZO indium gallium zinc oxide
  • the driver backplane is prepared, the peripheral driving circuit cannot be made on the substrate array. Therefore, manufacturing complementary type
  • the thin film transistor drive backplane is mainly based on low temperature polysilicon technology, but its preparation process and equipment are complicated. The preparation cost is high. Therefore, the complementary thin film transistor drives the backplane (mainly concentrated in the P-type thin film crystal
  • the preparation of tubes has become a research hotspot for major panel manufacturers and research institutes.
  • Some embodiments of the present invention provide a complementary thin film transistor driving backplane and a preparation method thereof Method, display device.
  • a preparation method provided by at least one embodiment of the present invention includes: forming a lower layer on a substrate Electrode; sequentially providing a continuous growth medium layer, a semiconductor layer and a diffusion protection layer; passing through a multi-gray mask The exposure process forms a photoresist-free region, an N-type thin film transistor preparation region, and a P-type thin film transistor preparation region; Removing the photoresist layer in the preparation region of the N-type thin film transistor by a plasma ashing process; removing the N-type thin a diffusion protective layer of the film transistor preparation region; a photoresist layer for removing a P-type thin film transistor preparation region; Forming a P-type thin film transistor having a P-type active layer; oxidizing the substrate; forming N-type thin film transistor of N-type active layer; providing a passivation layer on the base substrate; forming on the passivation layer Upper electrode.
  • At least one embodiment of the present invention provides a complementary thin film transistor driving backplane, the complementary type
  • the thin film transistor driving back plate includes a base substrate on which a plurality of P-type thin film crystals are disposed Body tube preparation area, multiple N-type thin film transistor preparation areas, and P-type thin film transistor fabrication A photoresist-free region between the region and the N-type thin film transistor fabrication region.
  • At least one embodiment of the present invention also provides a display device including the complementary thin film as described above
  • the membrane transistor drives the backplane.
  • FIG. 1 is a flow chart of a method for fabricating a complementary thin film transistor driving backplane according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of the first step of the preparation method according to an embodiment of the present invention (main section) Figure);
  • FIG 3 is a schematic structural view of a step 2 of the preparation method according to an embodiment of the present invention (main section) Figure);
  • FIG. 4 is a schematic structural view of a step 3 of the preparation method according to an embodiment of the present invention (main section) Figure);
  • FIG 5 is a schematic structural view of the step 4 of the preparation method in an embodiment of the present invention (main section Figure);
  • FIG. 6 is a schematic structural view of a step 5 of the preparation method according to an embodiment of the present invention (main section) Figure);
  • FIG. 7 is a schematic structural view of a complementary thin film transistor driving back plate according to an embodiment of the present invention (main section) view).
  • the complementary thin film transistor In the preparation process of the complementary thin film transistor driving backplane, the complementary thin film transistor is driven back The area of the P-type thin film transistor, the N-type thin film transistor, and the pixel electrode in the board is not easily defined, and is easy The production of the complementary thin film transistor driving backplane is low, and the manufacturing steps are too cumbersome. The mask is used too much and the preparation cost is too high.
  • FIG. 1 is a diagram of preparation of the complementary thin film transistor driving backplane according to at least one embodiment of the present invention Schematic diagram of the method flow, as shown in FIG. 1, the method includes the following steps:
  • the base substrate 101 is selected and set on the base substrate 101 by a sputtering process.
  • the electrode layer is placed, and the lower electrode layer is patterned by a mask exposure process according to design requirements.
  • a plurality of lower layer electrodes 102 distributed in a pre-designed distribution pattern are formed. Lining as described in this embodiment
  • the base substrate can be made of ordinary glass, silicon, etc., but the materials selected are not limited to these two, as long as A material having good transmittance and a certain hardness can be made into a substrate.
  • the layer electrode is any material of Mo, Al/Nd, Al/Nd/Mo, Mo/Al/Nd/Mo or Au/Ti or it Any combination of them; each of the lower layer electrodes 102 formed on the base substrate 101 will be used as a P-type thin The gate of a film transistor or an N-type thin film transistor.
  • a continuous growth medium layer is sequentially disposed on the lower layer electrode 102 from bottom to top. 103, a semiconductor layer 104 and a diffusion protective layer 105.
  • the dielectric layer 103 is continuously grown or
  • the diffusion protective layer 105 may be a single layer or a plurality of layers.
  • the continuous growth medium layer 103 will be placed at All of the lower layer electrodes 102 on the base substrate 101 are entirely covered and are on the continuous growth medium layer 103.
  • the semiconductor layer 104 and the diffusion protective layer 105 are sequentially disposed.
  • the material of the semiconductor layer 104 is, for example, SnO (stannous oxide) material.
  • the semiconductor layer 104 is, for example, a sputtering process, a sol- One of a gel process, a vacuum vapor deposition process, and a spray process.
  • SnO has high hole mobility, The structure and physical properties are stable and conform to the characteristics of P-type thin film transistors.
  • the continuous growth medium layer 103 can adopt a thermal growth process and atmospheric pressure chemistry. a vapor deposition process, a low pressure chemical vapor deposition process, a plasma assisted chemical vapor deposition process, Or one of the sputtering processes.
  • the continuous growth dielectric layer 103 is one of SiOx or SiNx or Their combination.
  • the diffusion protection layer 105 can adopt a thermal growth process and an atmospheric pressure chemical vapor phase. Deposition process, low pressure chemical vapor deposition process, plasma assisted chemical vapor deposition process, or sputtering One of the shooting techniques is made.
  • the diffusion protective layer 105 is one of SiOx or SiNx or a group thereof Hehe.
  • a photoresist layer 114 is disposed on the diffusion protection layer 105; for example, by graying
  • the mask exposure process forms a photoresist-free region 107 and an N-type thin film transistor on the substrate.
  • the spare area 108 and the P-type thin film transistor preparation area 109 For example, in this embodiment, a multi-gray mask is used.
  • the exposure process sequentially forms the photoresist-free region 107, the N-type thin film transistor preparation region 108 and the P-type Thin film transistor fabrication area 109.
  • the photoresist-free region 107 according to the setting of the photoresist-free region 107 on the substrate 101
  • the position is exposed, developed, and etched by a multi-gray reticle exposure process to remove the photoresist-free region 107
  • the side of the photoresist-free region 107 is a P-type thin film transistor preparation region 109. Design location, the other side is the design location of the N-type thin film transistor fabrication region 108, the photoresist-free Region 107 becomes the isolation region between the two transistors.
  • the design position of 108 and the design position of the P-type thin film transistor preparation region 109 can be, for example, double Adjusting the mask to perform a multi-gray mask exposure process, the dual mask to the photoresist-free region 107 No occlusion is made.
  • the design position of the N-type thin film transistor fabrication region can be masked by double modulation. After the partial exposure, development, and peeling of the semipermeable membrane on the film, the photoresist layer 114 thereon is thinned. An N-type thin film transistor fabrication region 108 is formed.
  • the P-type thin film transistor fabrication region 109 is doubled
  • the mask is completely blocked, so that the photoresist layer 114 of the P-type thin film transistor preparation region 109 is not exposed.
  • the thickness thereof remains unchanged, and a P-type thin film transistor preparation region 109 is formed.
  • the photoresist-free region 107 described in this embodiment is used to fabricate an isolation region of a thin film transistor.
  • the design of the isolation region can define N-type thin film transistor fabrication regions 108 on both sides thereof. And a P-type thin film transistor fabrication region 109.
  • the N-type thin film transistor preparation region 108 will be used as an N-type thin In the fabrication region of the film transistor, the P-type thin film transistor preparation region 109 will be used as a P-type thin film transistor. Production area.
  • the N-type thin film transistor fabrication region 108 is removed by a plasma ashing process.
  • Photoresist layer 114 in the embodiment of the invention, plasma-ashed P-type thin film crystal
  • the photoresist layer 114 on the tube preparation region 109 is also correspondingly thinned.
  • the N-type is removed by an etching process.
  • remove the P by a photoresist stripping process The photoresist layer 114 of the thin film transistor fabrication region 109.
  • P-type thin after removing the photoresist layer 114 A P-type thin film transistor having a P-type active layer 106 is formed in the film transistor fabrication region 109.
  • the base substrate 101 is subjected to high temperature annealing oxidation treatment in an oxygen atmosphere.
  • the P-type active layer 106 formed after the multi-gray mask exposure process is still maintained. SnO to meet the characteristics of a P-type thin film transistor.
  • the N-type thin film crystal after oxidation treatment The semiconductor layer 104 in the tube preparation region 108, the material of which is oxidized to SnOx by SnO, wherein 1 ⁇ x ⁇ 2; The chemical characteristics of the semiconductor layer 104 in the N-type thin film transistor fabrication region 108 are converted to conform to the N-type thin The film transistor characteristics are used to fabricate an N-type active connected to the upper electrode 113 of the N-type thin film transistor. Layer 110; thereby, an N-type thin film transistor is formed in the N-type thin film transistor fabrication region 108.
  • a passivation layer 111 is disposed on the body tube preparation region 109 and the N-type thin film transistor preparation region 108. Passivation layer 111 completely covers the three, and fills the photoresist-free region 107, so that the photoresist-free region 107, P Thin film transistors and N-type thin film transistors have the same height and can be used to cover each of them
  • the device performs isolation protection.
  • the passivation layer 111 is usually made of an insulating material. According to the design The passivation layer 111 is patterned by a mask exposure process to form a connection on the passivation layer 111.
  • the contact hole 112 is respectively disposed in the P-type thin film transistor preparation region 109 or N Corresponding to the P-type active layer 106 or the N-type active layer 110 on both sides of the thin film transistor preparation region 108 In the passivation layer 111.
  • the contact at the P-type thin film transistor fabrication region The hole 112 passes through the diffusion protection layer 105 on both sides of the P-type thin film transistor preparation region 109, and the through-P type has The source layer 106; the passivation layer 111 in this embodiment may be a single layer or a plurality of layers.
  • the passivation layer 111 For example, a thermal growth process, an atmospheric pressure chemical vapor deposition process, a low pressure chemical vapor deposition process, etc. One of ion assisted chemical vapor deposition processes, or sputtering processes.
  • the passivation layer 111 It is one of SiOx or SiNx or a combination thereof.
  • the upper electrode layer is disposed on the passivation layer 111 by a sputtering process, according to the design. It is required to pattern the upper electrode layer through the mask exposure process to form a pre-designed distribution.
  • the active layer 106 or the N-type active layer 110 is in contact with the conduction.
  • the upper layer electrode 113 is Any of Mo, Al/Nd, Al/Nd/Mo, Mo/Al/Nd/Mo or Au/Ti or any group thereof Hehe.
  • the complementary thin film transistor prepared by the above steps can also drive the backplane in the true Annealing in air, nitrogen, or oxygen; annealing temperature controlled at 120-450 °C The annealing time is controlled within the range of 0.5 to 2 hours. So far, the complementary thin film crystal of the present embodiment The tube drive back plate is prepared.
  • a complementary thin film transistor driving backplane manufacturing method provided by at least one embodiment of the present invention, Simply by using a double-tuned mask in the multi-gray reticle exposure process to partially polish the substrate Exposure and development, N-type thin film transistor fabrication region and P-type thin film transistor can be simultaneously defined and formed Preparation area. Therefore, the P-type thin film transistor, the N-type thin film transistor, and the like can be clearly defined.
  • the fabrication area of the pixel electrode provides a reliable guarantee for the subsequent fabrication of each device. In this way, complementary Type thin film transistor driving backplane manufacturing process due to unclear definition of each device fabrication area The problem that the thin film transistor and the N-type thin film transistor interfere with each other is effectively solved.
  • this At least one embodiment of the invention can effectively improve the problem of low yield of the resulting product, and Effectively reduce the cost of preparation.
  • the diffusion protective layer of the P-type thin film transistor fabrication region is used as The mask of the P-type active layer in the high-temperature annealing treatment can be omitted by a single mask exposure The step of manufacturing a P-type active layer. Therefore, the embodiment of the present invention can simplify the preparation process and improve Production yield and effective reduction of production.
  • FIG. 7 is a schematic structural diagram of a complementary thin film transistor driving backplane according to an embodiment of the present invention.
  • the complementary thin film transistor driving back plate provided in this embodiment is obtained by the above preparation method, and the structure thereof The details are as follows.
  • the complementary thin film transistor driving backplane of the embodiment of the present invention includes: a base substrate 101 on which a plurality of P-type thin film transistor preparation regions 201 are disposed, a plurality of N-type thin film transistor preparation regions 202, and a P-type thin film transistor preparation region 201 and A photoresist-free region 203 between the N-type thin film transistor fabrication regions 202.
  • the P-type thin film transistor preparation region 201 is provided with a lower layer electrode 102 in order from bottom to top, continuous Growth medium layer 103, P-type active layer 106, diffusion protection layer 105, and passivation layer 111; P-type active An upper layer electrode 113 is formed on both sides of the layer 106, and the upper layer electrode 113 extends into the passivation layer. In the contact hole 112 on the 111, the upper end is provided with an electrode lead 204; the P-type active layer 106 and the lower layer The electrodes constitute a P-type thin film transistor.
  • the N-type thin film transistor preparation region 202 is provided with a lower layer electrode 102 in order from bottom to top, continuous a growth medium layer 103, an N-type active layer 110, and a passivation layer 111; the N-type active layer 110 is provided on both sides thereof
  • the upper electrode 113 that is in contact with the upper electrode 113 extends into the contact hole 112 of the passivation layer 111
  • the upper end is provided with an electrode receiving head 204; the N-type active layer 110 and the lower layer electrode 102 constitute a N Thin film transistor.
  • the photoresist-free region 203 is provided with a continuous growth dielectric layer 103 and a passivation layer in this order from bottom to top. 111, wherein the continuous growth dielectric layer 103 of the non-photoresist region 203 is respectively opposite to the P-type thin film crystal
  • the body tube preparation area 201 is connected to the continuous growth medium layer 103 in the N-type thin film transistor preparation area 202.
  • the passivation layer 111 of the photoresist-free region 203 is located in the P-type thin film transistor preparation region 201 One of the upper electrode 113 and the other adjacent to the N-type thin film transistor preparation region 202 Between the upper electrodes 113; the side of the passivation layer 111 of the photoresistless region 203 will be corresponding thereto One side of the N-type active layer 110 is pressed on the continuous growth medium layer 103, and the other side will correspond thereto.
  • a pixel electrode (not shown) may be disposed on the photoresist-free region 203, according to
  • the pixel electrode may be an active matrix light-emitting organic electroluminescent display tube (OLED).
  • An anode which may also be a pixel electrode of an active matrix liquid crystal display (TFT-LCD);
  • TFT-LCD active matrix liquid crystal display
  • At least one embodiment of the present invention also provides a display device including the above a complementary thin film transistor driving backplane; examples of the display device include active matrix light emitting organic Electroluminescent display tube or active matrix liquid crystal display.
  • the complementary thin film transistor driving backplane is further provided with an organic electroluminescent layer.
  • the complementary thin film transistor is driven on the backplane and the lower A liquid crystal panel and a backlight module may be separately disposed on both sides.
  • Organic electroluminescence in embodiments of the invention The specific structure of the layer, the liquid crystal panel and the backlight module will not be described here.

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Abstract

一种互补型薄膜晶体管驱动背板及其制备方法、显示装置，包括在衬底基板（101）上形成下层电极（102）；依次设置连续生长介质层（103）、半导体层（104）和扩散保护层（105）；依次形成无光刻胶区（107）、N型薄膜晶体管制备区（108）和P型薄膜晶体管制备区（109）；去除N型薄膜晶体管制备区（108）的光刻胶层（114）；去除N型薄膜晶体管制备区（108）的扩散保护层（105）；去除P型薄膜晶体管制备区（109）的光刻胶层（114）；对衬底基板（101）进行氧化处理；在衬底基板（101）上设置钝化层（111）；在钝化层（111）上形成上层电极（113）。

Description

互补型薄膜晶体管驱动背板及其制备方法、显示装置 技术领域
本发明的实施例涉及一种互补型薄膜晶体管驱动背板及其制备方法、显 示装置。
背景技术
对于薄膜晶体管(TFT，Thin-Film Transistor)液晶显示器，各个面板厂 家不断推出新的产品。对于氧化铟镓锌(IGZO)材料，也逐渐在显示产品中 得到应用。然而，该IGZO材料主要用于制造N型薄膜晶体管，但是其化学 特性无法满足互补型薄膜晶体管驱动背板的制造需要。具体地说，采用IGZO 制备驱动背板时，无法把周边驱动电路做在基板阵列上。因此，制造互补型 薄膜晶体管驱动背板以低温多晶硅技术为主，但其制备过程和设备较复杂、 制备成本高。因此，互补型薄膜晶体管驱动背板(主要集中在P型薄膜晶体 管)的制备，成为各大面板厂商和科研单位的研究热点。
发明内容
本发明的一些实施例提供了一种互补型薄膜晶体管驱动背板及其制备方 法、显示装置。
本发明的至少一个实施例提供的制备方法包括：在衬底基板上形成下层 电极；依次设置连续生长介质层、半导体层和扩散保护层；通过多灰阶光罩 曝光工序形成无光刻胶区、N型薄膜晶体管制备区和P型薄膜晶体管制备区； 通过等离子体灰化工序去除N型薄膜晶体管制备区的光刻胶层；去除N型薄 膜晶体管制备区的扩散保护层；去除P型薄膜晶体管制备区的光刻胶层；形 成具有P型有源层的P型薄膜晶体管；对衬底基板进行氧化处理；形成具有 N型有源层的N型薄膜晶体管；在衬底基板上设置钝化层；在钝化层上形成 上层电极。
本发明的至少一实施例提供一种互补型薄膜晶体管驱动背板，该互补型 薄膜晶体管驱动背板包括衬底基板，在该衬底基板上设置有多个P型薄膜晶 体管制备区、多个N型薄膜晶体管制备区，以及设置在P型薄膜晶体管制备 区与N型薄膜晶体管制备区之间的无光刻胶区。
本发明的至少一实施例还提供一种显示装置，包括如上所述的互补型薄 膜晶体管驱动背板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图1是本发明一实施例中所述互补型薄膜晶体管驱动背板的制备方法流 程示意图；
图2是本发明一实施例中所述制备方法的步骤1的结构示意图(主剖视 图)；
图3是本发明一实施例中所述制备方法的步骤2的结构示意图(主剖视 图)；
图4是本发明一实施例中所述制备方法的步骤3的结构示意图(主剖视 图)；
图5是本发明一实施例中所述制备方法的步骤4的结构示意图(主剖视 图)；
图6是本发明一实施例中所述制备方法的步骤5的结构示意图(主剖视 图)；
图7是本发明一实施例的互补型薄膜晶体管驱动背板结构示意图(主剖 视图)。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描 述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例，都属于本发明保护的范围。
在互补型薄膜晶体管驱动背板制备过程中，对互补型薄膜晶体管驱动背 板中的P型薄膜晶体管、N型薄膜晶体管及像素电极的区域不易界定，容易 造成互补型薄膜晶体管驱动背板生产良率低，并且制造步骤过于繁琐，光罩 掩膜使用次数过多，因而制备成本过高。
图1为本发明的至少一实施例的所述互补型薄膜晶体管驱动背板的制备 方法流程示意图，参见图1所示，该方法包括如下步骤：
参见图2所示，选择衬底基板101，在衬底基板101上通过溅射工艺设 置下电极层，按照设计要求通过光罩曝光工序对下电极层进行图形化处理， 形成按照预设计的分布图案分布的多个下层电极102。本实施例中所述的衬 底基板可采用通常的玻璃、硅等材料，但所选用的材料不限于这两种，只要 具有好的透光度和一定的硬度的材料均可制成衬底基板。本实施例中所述下 层电极为Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo或Au/Ti中任一材料或它 们的任意组合；形成于衬底基板101上的各个下层电极102将被用作P型薄 膜晶体管或N型薄膜晶体管的栅极。
参见图3所示，在下层电极102上由下至上依次设置连续生长介质层 103、半导体层104和扩散保护层105。本实施例中，连续生长介质层103或 扩散保护层105可为单层也可为多层。例如，连续生长介质层103将设置在 衬底基板101上的所有下层电极102全部覆盖，并在连续生长介质层103上 依次设置半导体层104和扩散保护层105。半导体层104的材料例如为SnO (氧化亚锡)材料。本实施例中，半导体层104例如采用溅射工艺、溶胶- 凝胶工序、真空蒸镀工序、喷涂工序其中一种制得。SnO具有高空穴迁移率， 结构和物性稳定的特点，符合P型薄膜晶体管特性。
本发明的实施例中连续生长介质层103可以采用热生长工序、常压化学 气相沉积工序、低压化学气相沉积工序、等离子辅助体化学气相淀积工序、 或溅射工艺其中一种制得。连续生长介质层103为SiOx或SiNx其中之一或 它们的组合。
本发明的实施例中扩散保护层105可以采用热生长工序、常压化学气相 沉积工序、低压化学气相沉积工序、等离子辅助体化学气相淀积工序、或溅 射工艺其中一种制得。扩散保护层105为SiOx或SiNx其中之一或它们的组 合。
参见图4所示，在扩散保护层105上设置光刻胶层114；例如通过多灰 阶光罩曝光工序在衬底基板上分别形成无光刻胶区107、N型薄膜晶体管制 备区108和P型薄膜晶体管制备区109。例如，本实施例中通过多灰阶光罩 曝光工序依次形成所述无光刻胶区107，N型薄膜晶体管制备区108和P型 薄膜晶体管制备区109。
在本发明的实施例中，根据位于衬底基板101上的无光刻胶区107的设 计位置通过多灰阶光罩曝光工序进行曝光、显影、刻蚀以去除无光刻胶区107 的设计位置处的光刻胶层114、扩散保护层105和半导体层104，以此形成无 光刻胶区107。相应地，该无光刻胶区107一侧为P型薄膜晶体管制备区109 的设计位置，另一侧为N型薄膜晶体管制备区108的设计位置，该无光刻胶 区107成为两个晶体管间的隔离区。例如，根据所述N型薄膜晶体管制备区 108的设计位置和P型薄膜晶体管制备区109的设计位置，例如可以采用双 调掩膜板进行多灰阶光罩曝光工序，所述双调掩膜板对所述无光刻胶区107 不进行遮挡。另一方面，N型薄膜晶体管制备区的设计位置可以通过双调掩 膜板上的半透膜进行部分曝光、显影、剥离后，其上的光刻胶层114变薄， 形成N型薄膜晶体管制备区108。同时，对P型薄膜晶体管制备区109被双 调掩膜板完全遮挡，使P型薄膜晶体管制备区109的光刻胶层114未被曝光、 显影，剥离后，其厚度也保持不变，形成P型薄膜晶体管制备区109。
本实施例中所述的无光刻胶区107用来制作薄膜晶体管的隔离区，通过 形成隔离区的设计可以定义出分别位于其两侧的N型薄膜晶体管制备区108 和P型薄膜晶体管制备区109。N型薄膜晶体管制备区108将被用作N型薄 膜晶体管的制作区域，P型薄膜晶体管制备区109将被用作P型薄膜晶体管 的制作区域。
参见图4所示，通过等离子体灰化工序去除N型薄膜晶体管制备区108 的光刻胶层114，在本发明的实施例中，经等离子体灰化后的P型薄膜晶体 管制备区109上的光刻胶层114也相应变薄。之后，通过刻蚀工序去除N型 薄膜晶体管制备区108的扩散保护层105。然后，通过光刻胶剥离工序去除P 型薄膜晶体管制备区109的光刻胶层114。在去除光刻胶层114后的P型薄 膜晶体管制备区109内形成具有P型有源层106的P型薄膜晶体管。
参见图5所示，在氧气环境中对衬底基板101进行高温退火氧化处理， 在N型薄膜晶体管制备区108内形成完整的具有N型有源层110的N型薄 膜晶体管。在本发明的实施例中，在氧化处理过程中由于有扩散保护层105 的保护，因此位于P型薄膜晶体管制备区109的P型薄膜晶体管没有经受氧 化处理，其内的经过多灰阶光罩曝光工序后形成的P型有源层106依旧保持 为符合P型薄膜晶体管的特性的SnO。但是，经氧化处理后的N型薄膜晶体 管制备区108内的半导体层104，其材料由SnO被氧化成SnOx，其中1<x<2； N型薄膜晶体管制备区108内的半导体层104的化学特性转变为符合N型薄 膜晶体管特性，被用于制作N型薄膜晶体管中连接上层电极113的N型有源 层110；以此，在N型薄膜晶体管制备区108内形成N型薄膜晶体管。
参见图6所示，在位于衬底基板上101的无光刻胶区107、P型薄膜晶 体管制备区109和N型薄膜晶体管制备区108上设置钝化层111。该钝化层 111完全覆盖于三者之上，并将无光刻胶区107填充，使无光刻胶区107、P 型薄膜晶体管和N型薄膜晶体管具有同样高度，并可起到对包覆在其内的各 器件进行隔离保护的作用。钝化层111通常采用绝缘材料制成。按照设计要 求通过光罩曝光工序对钝化层111进行图形化处理，在钝化层111上形成接 触孔112；该接触孔112分别设置在与位于P型薄膜晶体管制备区109或N 型薄膜晶体管制备区108两侧的P型有源层106或N型有源层110相对应处 的钝化层111中。例如，如图6所示，位于P型薄膜晶体管制备区处的接触 孔112穿过P型薄膜晶体管制备区109两侧的扩散保护层105，直通P型有 源层106；本实施例中所述钝化层111可为单层也可为多层。所述钝化层111 例如采用热生长工序、常压化学气相沉积工序、低压化学气相沉积工序、等 离子辅助体化学气相淀积工序、或溅射工艺其中一种制得。所述钝化层111 为SiOx或SiNx其中之一或它们的组合。
参见图7所示，在钝化层111上通过溅射工艺设置上电极层，按照设计 要求通过光罩曝光工序对上电极层进行图形化处理，形成按照预设计的分布 图案分布的多个上层电极113。所述上层电极113下部均伸入接触孔并与P 型有源层106或N型有源层110接触导通。本实施例中所述上层电极113为 Mo、Al/Nd、Al/Nd/Mo、Mo/Al/Nd/Mo或Au/Ti中任一材料或它们的任意组 合。例如，还可对通过上述步骤制备得到的互补型薄膜晶体管驱动背板在真 空、氮气、或氧气的环境下进行退火处理；退火温度控制在120～450℃范围 内，退火时间控制在0.5～2小时范围内。至此，本实施例的互补型薄膜晶体 管驱动背板制备完毕。
本发明的至少一个实施例提供的互补型薄膜晶体管驱动背板制备方法， 只需通过在多灰阶光罩曝光工序中使用一次双调掩膜板对衬底基板进行部分 曝光、显影，即可同时定义并形成N型薄膜晶体管制备区和P型薄膜晶体管 制备区。由此，可清晰的界定区分出如P型薄膜晶体管、N型薄膜晶体管及 像素电极的制作区域；为之后的各器件的制作提供了可靠保障。这样，互补 型薄膜晶体管驱动背板制造工序中由于各器件制作区域界定不清而导致的P 型薄膜晶体管与N型薄膜晶体管相互干扰的问题得到了有效解决。因此，本 发明的至少一个实施例可有效改善由此产生的产品制造良率低的问题，并且 有效降低了制备成本。同时，利用P型薄膜晶体管制备区的扩散保护层作为 高温退火氧化处理中P型有源层的掩膜板，可省去需单独通过一次光罩曝光 工序制造P型有源层的步骤。因此，本发明的实施例可简化制备工序、提高 生产良率、有效降低生产升本。
图7是本发明一实施例提供的互补型薄膜晶体管驱动背板结构示意图， 本实施例提供的互补型薄膜晶体管驱动背板通过上述制备方法制得，其结构 具体如下所述。
参见图7所示，本发明实施例的互补型薄膜晶体管驱动背板包括：一个 衬底基板101，在该衬底基板101上设置有多个P型薄膜晶体管制备区201、 多个N型薄膜晶体管制备区202，以及设置在P型薄膜晶体管制备区201与 N型薄膜晶体管制备区202之间的无光刻胶区203。
所述P型薄膜晶体管制备区201由下至上依次设有下层电极102、连续 生长介质层103、P型有源层106、扩散保护层105和钝化层111；P型有源 层106两侧设有与其接触的上层电极113，该上层电极113伸入所述钝化层 111上的接触孔112内，其上端设有电极接引头204；P型有源层106和下层 电极组成了P型薄膜晶体管。
所述N型薄膜晶体管制备区202由下至上依次设有下层电极102、连续 生长介质层103、N型有源层110和钝化层111；N型有源层110两侧设有与 其接触的上层电极113，该上层电极113伸入所述钝化层111上的接触孔112 内，其上端设有电极接引头204；N型有源层110和下层电极102组成了N 型薄膜晶体管。
所述无光刻胶区203由下至上依次设有连续生长介质层103和钝化层 111，其中无光刻胶区内203的连续生长介质层103两端分别与P型薄膜晶 体管制备区201和N型薄膜晶体管制备区202内的连续生长介质层103连接 成一体，该无光刻胶区内203的钝化层111位于P型薄膜晶体管制备区201 中其中一个上层电极113和与其相邻的N型薄膜晶体管制备区202中另一个 上层电极113之间；无光刻胶区内203的钝化层111一侧将与其对应的所述 N型有源层110一侧压制于连续生长介质层103上，另一侧将与其相对应的 所述P型薄膜晶体管制备区201一侧的扩散保护层105连同P型有源层106 一同压制于连续生长介质层103上。
本实施例中在无光刻胶区203上可设有像素电极(图中未显示)，根据 不同的应用，该像素电极可以是有源矩阵发光有机电致显示管(OLED)中 的阳极，也可以是有源矩阵液晶显示器(TFT-LCD)的像素电极；该像素电 极通过与上层电极113的电极接引头204连接，分别与P型有源层106和N 型有源层连接110。
本发明的至少一个实施例还提供一种显示装置，该显示装置包括如上所 述的互补型薄膜晶体管驱动背板；该显示装置的示例包括有源矩阵发光有机 电致显示管或有源矩阵液晶显示器。
在一个实施例中，当显示装置为有源矩阵发光有机电致显示管时，在该 互补型薄膜晶体管驱动背板上还设有有机电致发光层。在一个实施例中，当 显示装置为有源矩阵液晶显示器时，在该互补型薄膜晶体管驱动背板上、下 两侧还可分别设有液晶面板和背光模组。本发明的实施例中的有机电致发光 层、液晶面板和背光模组的具体结构，此处不再过多赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范 围，本发明的保护范围由所附的权利要求确定。
本申请要求于2013年12月24日递交的中国专利申请第201310723714.0 号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims (9)

  1. 一种互补型薄膜晶体管驱动背板的制备方法，包括：
    在衬底基板上形成下层电极；
    依次设置连续生长介质层、半导体层和扩散保护层；
    形成无光刻胶区、N型薄膜晶体管制备区和P型薄膜晶体管制备区；
    去除N型薄膜晶体管制备区的光刻胶层；
    去除N型薄膜晶体管制备区的扩散保护层；
    去除P型薄膜晶体管制备区的光刻胶层；形成具有P型有源层的P型薄 膜晶体管；
    对衬底基板进行氧化处理；形成具有N型有源层的N型薄膜晶体管；
    在衬底基板上设置钝化层；
    在钝化层上形成上层电极。
  2. 如权利要求1所述互补型薄膜晶体管驱动背板的制备方法，还包括对 制备后的互补型薄膜晶体管驱动背板进行退火处理。
  3. 如权利要求2所述互补型薄膜晶体管驱动背板的制备方法，其中，退 火温度在120～450℃范围内，退火时间在0.5～2小时范围内。
  4. 如权利要求1-3任一项所述的互补型薄膜晶体管驱动背板的制备方 法，其中，所述半导体层材料为SnO材料。
  5. 如权利要求4所述的互补型薄膜晶体管驱动背板的制备方法，其中， 经氧化处理后的N型薄膜晶体管制备区内的半导体层，其材料由SnO被氧 化成SnOx，其中1<x<2，被用作N型薄膜晶体管中的N型有源层；在氧化 处理过程中，由于有扩散保护层的保护，P型薄膜晶体管的P型有源层没有 经受氧化处理。
  6. 如权利要求1-5任一项所述的互补型薄膜晶体管驱动背板的制备方 法，其中，形成所述半导体层采用溅射工艺、溶胶-凝胶工序、真空蒸镀工序、 喷涂工序其中一种制得。
  7. 如权利要求1-6任一项所述的互补型薄膜晶体管驱动背板的制备方 法，其中，对所述上电极层进行图形化处理，形成多个上层电极。
  8. 一种互补型薄膜晶体管驱动背板，包括：
    衬底基板，
    在该衬底基板上设置的多个P型薄膜晶体管制备区、多个N型薄膜晶体 管制备区，以及
    设置在P型薄膜晶体管制备区与N型薄膜晶体管制备区之间的无光刻胶 区。
  9. 一种显示装置，包括如权利要求8所述的互补型薄膜晶体管驱动背板。
PCT/CN2014/078571 2013-12-24 2014-05-27 互补型薄膜晶体管驱动背板及其制备方法、显示装置 WO2015096382A1 (zh)

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