CN103197998A - Device and method for testing power sequence of PMU (power management unit) - Google Patents

Abstract

The invention provides a device and a method for testing the power sequence of a PMU. The device comprises the PMU to be tested and an SOC (system on chip) for testing, wherein two power output pins of the PMU to be tested are connected to two detection interrupting pins of the SOC through a level detection circuit; the SOC determines corresponding timing sequences through detecting the voltage change of an NPN triode collector, receives interruptions, records the system time of each interruption in an interruption callback function, and stores the record in a record array; and after the execution of all the interruptions is finished, the array data and preset data are compared, and the correctness of the power sequence of the PMU to be tested is determined. According to the device and the method, the interruption pins of a test plate processor are used for detecting the power output timing sequence of the PMU to be tested, so that the testing efficiency is improved greatly, and meanwhile, the testing accuracy is guaranteed.

Description

PMU electrifying timing sequence testing device and method

[technical field]

The present invention relates to a kind of proving installation and method thereof of computer motherboard, specifically refer to PMU electrifying timing sequence testing device and method.

[background technology]

PMU(power management unit), Power Management Unit, be a kind of height integrated, at the power management scheme of portable use, being about to the discrete some class power management devices of tradition is incorporated within the single encapsulation, can realize higher power supply conversion efficiency and more low-power consumption like this, and package count still less is to adapt to the plate level space that dwindles.PMU will cooperate the electrifying timing sequence of CPU (system level chip), the electric sequence of some voltage and between the time interval precedence relationship and time requirement are arranged.

At present, mainly use observation oscilloscope to detect power supply (powering on) sequential of PMU chip by the test man, efficient is very low, and accuracy also seldom arrives assurance.

In view of this, the inventor furthers investigate at the defective of prior art, and has this case to produce.

[summary of the invention]

One of technical matters to be solved by this invention is to provide a kind of advantages of simplicity and high efficiency PMU electrifying timing sequence testing device.

Two of technical matters to be solved by this invention is to provide a kind of advantages of simplicity and high efficiency PMU electrifying timing sequence method of testing.

The present invention one of solves the problems of the technologies described above by the following technical programs:

The PMU electrifying timing sequence testing device comprises PMU to be measured and the SOC that is used for testing, and two power supply output pins of described PMU to be measured are connected to two interruption detection pin of described SOC respectively by a level sensitive circuit;

Described level sensitive circuit comprises one first resistance, one second resistance, one the 3rd resistance, a NPN triode; Each power supply output pin of described PMU to be measured connects described first resistance, and the described first resistance other end divides two-way, and one the road is connected to the base stage of described NPN triode, and another road connects described second resistance, the described second resistance other end ground connection; The grounded emitter of described NPN triode, the collector of described NPN triode divides two-way, and one road interruption that is connected to described SOC detects pin, and another road is connected to described the 3rd resistance, and described the 3rd resistance other end is connected to power supply;

Described SOC, judge corresponding sequential by the change in voltage that detects described NPN transistor collector respectively, described SOC receives interruption, system time when in interrupting call back function, noting each road then and interrupting, be stored in the record array, all interrupt all complete after with array data and preset data comparison, judge the correctness of described PMU electrifying timing sequence to be measured.

The present invention solve the problems of the technologies described above by the following technical programs two:

Use the electrifying timing sequence method of testing of above-mentioned PMU electrifying timing sequence testing device, comprise the steps:

Step 1: the GPIO of SOC is made as fracture in the negative edge, and interrupt counter count is clear 0, the time interocclusal record array timeDate[] clear 0;

Step 2: power on for PMU to be measured;

Step 3: 1 microsecond of delaying time, time++;

Step 4: judge Count 〉=the survey power supply number n that needs to be measured? be, change step 5 over to, not, change step 6 over to;

Step 5: timeDate[relatively] whether in setting range, be, then change step 7 over to, not, then change step 8 over to;

Step 6: judge time〉the timeouts value? be, change step 8 over to, not, forward step 3 to;

Step 7:PMU electrifying timing sequence is qualified, and ret=SUCCESS changes step 9 over to;

Step 8:PMU electrifying timing sequence is defective, and ret=ERROR changes step 9 over to;

Step 9: finish test.

The invention has the advantages that: utilize the interrupt pin of test board processor to detect the power supply output timing of PMU to be measured, when having increased substantially testing efficiency, also guaranteed the accuracy of test.

[description of drawings]

The invention will be further described in conjunction with the embodiments with reference to the accompanying drawings.

Fig. 1 is the hardware configuration synoptic diagram of proving installation of the present invention.

Fig. 2 is method of testing schematic flow sheet of the present invention.

[embodiment]

As shown in Figure 1, the PMU electrifying timing sequence testing device comprises PMU to be measured and the SOC that is used for testing, and two power supply output pins of PMU are connected to two interruption detection pin of SOC respectively by first level sensitive circuit, second level sensitive circuit.

First level sensitive circuit comprises resistance R 1, R2, R3, NPN triode Q1; One of them power supply output pin of PMU connects resistance R 1, and resistance R 1 other end divides two-way, and one the road is connected to the base stage of NPN triode Q1, and another road connects resistance R 3, resistance R 3 other end ground connection; The grounded emitter of NPN triode Q1, the collector of NPN triode Q1 divides two-way, and one road interruption that is connected to SOC detects pin, and another road is connected to resistance R 2, and resistance R 2 other ends are connected to power supply.

Second level sensitive circuit comprises resistance R 4, R5, R6, NPN triode Q2; One of them power supply output pin of PMU connects resistance R 4, and resistance R 4 other ends divide two-way, and one the road is connected to the base stage of NPN triode Q2, and another road connects resistance R 6, resistance R 6 other end ground connection; The grounded emitter of NPN triode Q2, the collector of NPN triode Q2 divides two-way, and one road interruption that is connected to SOC detects pin, and another road is connected to resistance R 5, and resistance R 5 other ends are connected to power supply.

SOC judges corresponding sequential by the change in voltage that detects described NPN transistor collector respectively, described SOC receives interruption, system time when in interrupting call back function, noting each road then and interrupting, be stored in the record array, all interrupt all complete after with array data and preset data comparison, judge the correctness of described PMU electrifying timing sequence to be measured.

Concrete PMU electrifying timing sequence method of testing comprises the steps: as shown in Figure 2

Step 1: the GPIO of SOC is made as fracture in the negative edge, and interrupt counter count is clear 0, the time interocclusal record array timeDate[] clear 0;

Step 2: power on for PMU to be measured;

Step 3: 1 microsecond of delaying time, time++;

Step 4: judge Count 〉=the survey power supply number n that needs to be measured? be, change step 5 over to, not, change step 6 over to;

Step 5: timeDate[relatively] whether in setting range, be, then change step 7 over to, not, then change step 8 over to;

Step 6: judge time〉the timeouts value? be, change step 8 over to, not, forward step 3 to;

Step 7:PMU electrifying timing sequence is qualified, and ret=SUCCESS changes step 9 over to;

Step 8:PMU electrifying timing sequence is defective, and ret=ERROR changes step 9 over to;

Step 9: finish test.

The present invention utilizes the interrupt pin of test board processor to detect the power supply output timing of PMU to be measured, when having increased substantially testing efficiency, has also guaranteed the accuracy of test.

The above only is preferable enforcement use-case of the present invention, is not for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.

Claims (2)

1.PMU electrifying timing sequence testing device is characterized in that: comprise PMU to be measured and the SOC that is used for testing, two power supply output pins of described PMU to be measured are connected to two interruption detection pin of described SOC respectively by a level sensitive circuit;

Described level sensitive circuit comprises one first resistance, one second resistance, one the 3rd resistance, a NPN triode; Each power supply output pin of described PMU to be measured connects described first resistance, and the described first resistance other end divides two-way, and one the road is connected to the base stage of described NPN triode, and another road connects described second resistance, the described second resistance other end ground connection; The grounded emitter of described NPN triode, the collector of described NPN triode divides two-way, and one road interruption that is connected to described SOC detects pin, and another road is connected to described the 3rd resistance, and described the 3rd resistance other end is connected to power supply;

Described SOC, judge corresponding sequential by the change in voltage that detects described NPN transistor collector respectively, described SOC receives interruption, system time when in interrupting call back function, noting each road then and interrupting, be stored in the record array, all interrupt all complete after with array data and preset data comparison, judge the correctness of described PMU electrifying timing sequence to be measured.

2. a right to use requires the electrifying timing sequence method of testing of 1 described PMU electrifying timing sequence testing device, it is characterized in that: comprise the steps:

Step 1: the GPIO of SOC is made as fracture in the negative edge, and interrupt counter count is clear 0, the time interocclusal record array timeDate[] clear 0;

Step 2: power on for PMU to be measured;

Step 3: 1 microsecond of delaying time, time++;

Step 4: judge Count 〉=the survey power supply number n that needs to be measured? be, change step 5 over to, not, change step 6 over to;

Step 5: timeDate[relatively] whether in setting range, be, then change step 7 over to, not, then change step 8 over to;

Step 6: judge time〉the timeouts value? be, change step 8 over to, not, forward step 3 to;

Step 7:PMU electrifying timing sequence is qualified, and ret=SUCCESS changes step 9 over to;

Step 8:PMU electrifying timing sequence is defective, and ret=ERROR changes step 9 over to;

Step 9: finish test.

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