CN109828167A - A kind of method and apparatus positioning Intel Platform Server electrifying timing sequence exception - Google Patents
A kind of method and apparatus positioning Intel Platform Server electrifying timing sequence exception Download PDFInfo
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- CN109828167A CN109828167A CN201811624978.XA CN201811624978A CN109828167A CN 109828167 A CN109828167 A CN 109828167A CN 201811624978 A CN201811624978 A CN 201811624978A CN 109828167 A CN109828167 A CN 109828167A
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Abstract
The invention discloses a kind of methods for positioning Intel Platform Server electrifying timing sequence exception, comprising: when detect Intel Platform Server direct current test occur abnormal when, exported at positioning abnormal level and by the signal at abnormal level with conducting wire；Oscillograph is connected to conducting wire, to receive and show the signal at abnormal level, wherein the variation of signal is carried out crawl preservation by oscillograph.The present invention by oscillograph can the variation to signal saved in real time, state before signal is not known about in the case where avoiding the occurrence of abnormal problem and make false judgment, to improve the efficiency of research and development of server, reduce research and development cost.In addition, during reappearing abnormal problem, being paid close attention in real time without staff when the signal at abnormal level is exported with conducting wire, alleviating research staff's working strength.In addition, the present invention also provides the devices of corresponding positioning Intel Platform Server electrifying timing sequence exception.
Description
Technical field
The present invention relates to field of computer technology, it particularly relates to a kind of positioning Intel Platform Server electrifying timing sequence
Abnormal method and apparatus.
Background technique
With the continuous expansion of server application, server system is just becoming more and more huger, and server power supply is also more next
It is more complicated.So that server master board in DC (abbreviation of Direct Current, i.e. direct current) test process, encounter power supply it is different
Questions and prospect, the especially CPLD (letter of Complex Programmable Logic Device cannot be accurately positioned in reason condition
Claim, i.e. Complex Programmable Logic Devices) it is whether abnormal, cause the server R&D cycle elongated, causes huge economic loss.
At present in Intel Platform Server DC test process, encounters and power on abnormal problem, it is main to be worked as by instrument determination
Preceding server exception level, then search cause the reason of the level exception go forward side by side go targetedly modify, then carry out again
DC test.If occurring exception again, step is solved the problems, such as before continuing to repeat, and is passed through until DC is tested, and electrifying timing sequence is just
Often.
Prior art disadvantage is: abnormal electrical power supply situation is encountered, because not can determine that state before level exception, so that
It can only targetedly modify extremely to current level, cannot accurately find abnormal root, therefore handle and solve the exception institute
Take time length, influences the Project-developing period, brings huge economic loss.
For problem above-mentioned in the related technology, currently no effective solution has been proposed.
Summary of the invention
For the problem that processing solves abnormal required time length in the related technology, low efficiency, the present invention proposes a kind of positioning
The method and apparatus of Intel Platform Server electrifying timing sequence exception, can quickly handle exception.
The technical scheme of the present invention is realized as follows:
According to an aspect of the invention, there is provided a kind of method for positioning Intel Platform Server electrifying timing sequence exception,
Include:
When detect the Intel Platform Server direct current test occur abnormal when, position at abnormal level and
Signal at the abnormal level is exported with conducting wire；
Oscillograph is connected to the conducting wire, to receive and show the signal at the abnormal level, wherein the oscillography
The variation of the signal is carried out crawl preservation by device.
In some embodiments, the method also includes:
The direct current electrical testing is carried out, again to reappear the exception.
In some embodiments, the method also includes:
The exception is checked and handled until the Intel Platform Server restores to operate normally.
In some embodiments, wherein the crawl upper limit threshold of variation of the oscillograph to the signal is set, and
When the variation of the signal is less than the upper limit threshold, the oscillograph grabs the signal and saves.
According to another aspect of the present invention, a kind of device for positioning Intel Platform Server electrifying timing sequence exception is provided,
Include:
Detection module tests whether exception in direct current for detecting the Intel Platform Server；
Locating module, for positioning at abnormal level and exporting the signal at the abnormal level with conducting wire；
Oscillograph is connected to the conducting wire, to receive and show the signal at the abnormal level, wherein described to show
The variation of the signal is carried out crawl preservation by wave device.
In some embodiments, wherein the oscillograph has the crawl upper limit threshold of the variation to the signal, and
When the variation of the signal is less than the upper limit threshold, the oscillograph grabs the signal and saves.
The present invention by oscillograph can the variation to signal saved in real time, in the case where avoiding the occurrence of abnormal problem
State before not knowing about signal and make false judgment, to improve the efficiency of research and development of server, reduce research and development cost.This
Outside, it when the signal at abnormal level being exported with conducting wire, during reappearing abnormal problem, is closed in real time without staff
Note, alleviates research staff's working strength.
Detailed description of the invention
It in order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, below will be to institute in embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is the method for positioning Intel Platform Server electrifying timing sequence exception according to an embodiment of the invention；
Fig. 2 is the method for positioning Intel Platform Server electrifying timing sequence exception according to another embodiment of the invention；
Fig. 3 is the device of positioning Intel Platform Server electrifying timing sequence exception according to an embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art's every other embodiment obtained belong to what the present invention protected
Range.
The present invention provides a kind of methods for positioning Intel Platform Server electrifying timing sequence exception, can be fast and accurately
The reason of navigating to upper electrical anomaly in Intel Platform Server DC test process shortens processing and solves the abnormal time, improve
Server efficiency of research and development substantially reduces research and development cost.
Referring to Fig. 1, in embodiment provided by the present invention, when providing a kind of positioning Intel Platform Server and powering on
The method of sequence exception, comprising:
S101: when detect Intel Platform Server direct current test occur abnormal when, position at abnormal level and
Signal at abnormal level is exported with conducting wire；
S102: being connected to conducting wire for oscillograph, to receive and show the signal at abnormal level, wherein oscillograph will be believed
Number variation carry out crawl preservation.
Based on above embodiments, oscillograph can the variation to signal saved in real time, avoid the occurrence of abnormal problem
In the case of do not know about signal before state and make false judgment, to improve the efficiency of research and development of server, reduce research and development
Cost.In addition, during reappearing abnormal problem, being not necessarily to staff when the signal at abnormal level is exported with conducting wire
Concern in real time, alleviates research staff's working strength.
Referring to fig. 2, in some embodiments, method further include: S103: direct current electrical testing is carried out, again to reappear exception.
In some embodiments, method further include: S104: checking and it is abnormal to handle until Intel Platform Server restores
It operates normally.
In some embodiments, method includes: oscillograph to be arranged to the crawl upper limit threshold of the variation of signal, and believing
Number variation be less than upper limit threshold when, oscillograph to signal grab save.
Referring to Fig. 3, on the other hand, according to an embodiment of the invention, additionally providing on a kind of positioning Intel Platform Server
The device of electric timing exception, comprising:
Detection module 10 tests whether exception in direct current for detecting the Intel Platform Server；
Locating module 11, for positioning at abnormal level and exporting the signal at abnormal level with conducting wire；
Oscillograph 12 is connected to conducting wire, to receive and show the signal at abnormal level, wherein oscillograph is by signal
Variation carry out crawl preservation.
In some embodiments, device includes:
Oscillograph 12 has the crawl upper limit threshold of the variation to signal, and is less than upper limit threshold in the variation of signal
When, oscillograph 12 grabs signal and saves.
To sum up, by means of above-mentioned technical proposal of the invention, the variation of signal can be carried out by oscillograph 12 real-time
The reason of saving, can fast and accurately navigating to upper electrical anomaly in Intel Platform Server DC test process, shortens processing
The abnormal time is solved, server efficiency of research and development is improved, substantially reduces research and development cost.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of method for positioning Intel Platform Server electrifying timing sequence exception characterized by comprising
When detect the Intel Platform Server direct current test occur abnormal when, position at abnormal level and by institute
The signal at abnormal level is stated to be exported with conducting wire；
Oscillograph is connected to the conducting wire, to receive and show the signal at the abnormal level, wherein the oscillograph will
The variation of the signal carries out crawl preservation.
2. the method according to claim 1, wherein the method also includes:
The direct current electrical testing is carried out, again to reappear the exception.
3. according to the method described in claim 2, it is characterized in that, the method also includes:
The exception is checked and handled until the Intel Platform Server restores to operate normally.
4. the method according to claim 1, wherein wherein, variation of the oscillograph to the signal is arranged
Crawl upper limit threshold, and the variation of the signal be less than the upper limit threshold when, the oscillograph grabs the signal
It goes bail for and deposits.
5. a kind of device for positioning Intel Platform Server electrifying timing sequence exception characterized by comprising
Detection module tests whether exception in direct current for detecting the Intel Platform Server；
Locating module, for positioning at abnormal level and exporting the signal at the abnormal level with conducting wire；
Oscillograph is connected to the conducting wire, to receive and show the signal at the abnormal level, wherein the oscillograph
The variation of the signal is subjected to crawl preservation.
6. device according to claim 5, which is characterized in that wherein, the oscillograph has the variation to the signal
Crawl upper limit threshold, and the variation of the signal be less than the upper limit threshold when, the oscillograph grabs the signal
It goes bail for and deposits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811624978.XA CN109828167A (en) | 2018-12-28 | 2018-12-28 | A kind of method and apparatus positioning Intel Platform Server electrifying timing sequence exception |
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| CN201811624978.XA CN109828167A (en) | 2018-12-28 | 2018-12-28 | A kind of method and apparatus positioning Intel Platform Server electrifying timing sequence exception |
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Application publication date: 20190531 |