Nothing Special   »   [go: up one dir, main page]

CN101447442B - 包括在基底上放置半导体芯片的制造装置的方法 - Google Patents

包括在基底上放置半导体芯片的制造装置的方法 Download PDF

Info

Publication number
CN101447442B
CN101447442B CN2008101763832A CN200810176383A CN101447442B CN 101447442 B CN101447442 B CN 101447442B CN 2008101763832 A CN2008101763832 A CN 2008101763832A CN 200810176383 A CN200810176383 A CN 200810176383A CN 101447442 B CN101447442 B CN 101447442B
Authority
CN
China
Prior art keywords
substrate
semiconductor chip
electrode
dielectric substance
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008101763832A
Other languages
English (en)
Other versions
CN101447442A (zh
Inventor
R·奥特伦巴
X·施勒格尔
R·费希尔
T·L·谭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN101447442A publication Critical patent/CN101447442A/zh
Application granted granted Critical
Publication of CN101447442B publication Critical patent/CN101447442B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及包括在基底上放置半导体芯片的制造装置的方法。公开了一种制造装置的方法。一个实施例提供具有从基底突出的第一元件的基底。半导体芯片具有在第一表面上的第一电极，和与第一表面相反的第二表面上的第二电极。半导体芯片被放置在基底的第一元件上，半导体芯片的第一表面朝向基底。半导体芯片的第二电极电连接到基底，且基底被至少部分移除。

Description

包括在基底上放置半导体芯片的制造装置的方法
技术领域
本发明涉及一种制造装置的方法，该方法包括在基底上放置半导体芯片，并涉及一种装置，该装置包括在基底上放置的半导体芯片。
背景技术
例如，可以在基底上放置功率半导体芯片。功率半导体芯片适用于电流和/或电压的切换或控制。功率半导体芯片可以被配置成功率晶体管、功率二极管或IGBT(绝缘栅双极型晶体管)。
发明内容
根据本发明的实施例，提供一种制造装置的方法，该方法包括：
提供基底，该基底具有从基底的顶表面向上突出的第一元件；
提供半导体芯片，该半导体芯片具有在第一表面上的第一电极和在与第一表面相反的第二表面上的第二电极；
将半导体芯片放置在基底的第一元件上，其中半导体芯片的第一表面朝向基底的顶表面，使得半导体芯片的第一电极位于从基底的顶表面向上突出的第一元件上；
将半导体芯片的第二电极电耦接到从基底向上突出的第二元件；以及
至少部分地移除基底，并且在移除基底时不移除第一元件和第二元件。
根据本发明的实施例，该方法还包括通过研磨或蚀刻来移除基底。
根据本发明的实施例，基底是由金属或金属合金或陶瓷材料或纸材料制成的。
根据本发明的实施例，该方法还包括通过印刷来制造第一元件。
根据本发明的实施例，该方法还包括通过喷墨印刷来制造第一元件。
根据本发明的实施例，该方法还包括在将半导体芯片放置在基底上后，用电介质材料覆盖基底。
根据本发明的实施例，该方法还包括在半导体芯片和基底之间放置电介质材料。
根据本发明的实施例，半导体芯片具有位于第一表面上的第三电极，且第三电极电耦接到从基底突出的第三元件，并且其中在移除基底时不移除第三元件。
根据本发明的实施例，半导体芯片是功率半导体芯片。
附图说明
附图被包括以提供对实施例的进一步理解，并被结合和组成本说明书的一部分。附图示出了实施例，并和描述一起用于帮助解释实施例的原理。其它实施例和实施例的许多预期的优势可以被容易地理解，因为参考以下具体的说明它们将变得更好理解。附图中的元件并不是必须互相成比例。相同的附图标记表示相应的类似部件。
图1A至1D示意性地示出了根据一个示例性实施例的方法。
图2A至2D示意性地示出了根据又一示例性实施例的又一方法。
图3A至3D示意性地示出了根据再一示例性实施例的再一方法。
图4A至4D示意性地示出了根据又一示例性实施例的又一方法。
具体实施方式
在以下具体的说明中，参考构成说明书的一部分且其中以图示的方式示出了特定实施例的附图，本发明可以在所述特定实施例中被实施。在这方面，方向术语，如“顶部”、“底部”、“前”、“后”、“在前(leading)”、“尾随(trailing)”等，参考所描述的图中的方向来使用。由于实施例的组件可以许多不同的方向放置，使用方向术语是为了解释而不是在任何方面限制。可以理解，在不偏离本发明的范围内，可以使用其它的实施例，且可以进行结构或逻辑上的改变。因此，以下具体的说明不是为了限制，且本发明的范围是由所附权利要求限定的。
可以理解，这里描述的各种示例实施例的特征可以互相结合，除非另外特别指出。
以下将描述具有半导体芯片的装置。半导体芯片可以是非常不同的类型并可以包括，例如，集成电或电光电路。这些半导体芯片例如可以被配置成功率MOSFET，例如，功率晶体管、功率二极管或IGBT(绝缘栅双极型晶体管)。此外，半导体芯片可以包括控制电路，微处理器或微电子机械组件。在一个实施例中，可以涉及垂直类型的半导体芯片，其被这样制造从而电流可以在与半导体芯片的主表面基本垂直的方向上流动。在具有垂直结构的半导体芯片中，通过其传导电流的电极被布置在半导体芯片的至少两个表面上，这些表面被布置在半导体芯片的两个相反的侧面上。在一个实施例中，功率晶体管、功率二极管和IGBT可以具有垂直结构。例如，功率晶体管的源和漏电极、功率二极管的阳极和阴极电极以及IGBT的发射极电极和集电极电极可以位于相应的功率半导体芯片的相反的表面上。
以下描述的装置可以包括用于控制其它集成电路的集成电路，例如，功率晶体管、功率二极管或IGBT的集成电路。半导体芯片不需要用特定的半导体材料制造，此外可以包括不是半导体的无机/或有机材料，例如，绝缘体、塑料或金属。而且，半导体芯片可以是封装的或未封装的。
半导体芯片可以具有电极(或接触衬垫)，来允许与半导体芯片进行电接触。电极可以由任意导电材料组成，以金属为例，比如铜、铝或金，金属合金或导电有机材料。在一个扩散焊接(diffusionsoldering)的实施例中，可以使用芯片接合技术将半导体芯片安装在基底上。
以下阐述的基底可以是任何合适的材料，包括金属、金属合金和有机材料。基底可以是任意的形状、尺寸或材料。在装置的制造过程中，基底可以以这样的方式被提供：其它的基底被布置在附近并用连接装置连接到该基底，目的是为了分开这些基底。在一个实施例中，如以下描述的基底可以被配置成引线框(leadframe)，具有至少一个芯片衬垫(die pad)和多个引线，被布置成用这些引线与半导体芯片的电极接触，来将该装置电连接到装置外的电接触。但是，基底也可以仅由芯片衬垫组成而没有任何引线。基底可以用金属或金属合金、铜、铁镍或其它材料制造。而且，可以用导电材料，例如，铜、银或镍磷来镀到基底上。
以下描述的电介质材料可以是电绝缘或主要电绝缘的材料。例如，电介质材料可以是模制材料，例如，热塑性或热固性材料。可以使用各种技术来放置模制材料，例如压缩模制或喷射模制。此外，电介质材料可以是聚合材料，可以在低于50℃的温度，例如，室温下被放置。聚合材料可以通过模版印刷来放置。电介质材料还可以包括任何电介质填充剂材料，在一个实施例中是SiO2、Al2O3或者AlN。电介质材料可以具有的机械特性是，在通常的使用条件下，保证使用该电介质材料制造的芯片封装高度的机械稳定性。
此处描述的用于组装半导体芯片封装的方法可以包括在一个较大的基底上同时组装若干芯片封装，并通过在封装之间适当的边界线处分开基底，来单个化个体的芯片封装。这里描述的半导体芯片封装可以包括多于一个的半导体芯片。此外，使用这里描述的方法组装的半导体芯片封装可以被模制材料完全覆盖，或用模制材料部分地覆盖，暴露基底、半导体芯片和/或电极连接结构的一部分。在一个实施例中，半导体芯片封装可以具有元件，在一个实施例中是金属元件，将封装内的半导体芯片的电极电耦接到基底，这些元件至少部分地从模制材料中暴露。这样暴露的元件可以被用来在其上附加散热单元，所述散热单元适于消散在操作期间在半导体封装内产生的热量。将封装内的半导体芯片的电极电耦接到基底并从模制材料中暴露的金属元件，在装置的操作期间可以被维持在地电位。
可以使用一个或多个导电元件来将半导体芯片电连接到其它部件，例如基底。导电元件可以是键合引线(bond wire)，或者也可以是其它的导电结构，例如线夹(clip)。线夹可以，例如，通过冲压或模压金属条而形成。
以下描述的装置包括外部接触元件。外部接触元件可从装置的外部访问，并允许从装置的外部与半导体芯片来进行电接触。此外，外部接触元件可以具有导热性并作为散热器，用于消散由半导体芯片产生的热量。外部接触元件可以由任何期望的导电材料组成，以金属为例，例如铜、铝或金，铝合金或导电有机材料。外部接触元件或其表面还可以构成组装平面，以将装置安装到另一元件上或将另一元件安装到装置上。
图1A至1D示意性地示出了根据一个示例性实施例的方法。根据图1A，提供了具有突出元件110的基底10。此外，在基底10上还提供了与突出元件110邻近的突出元件111和112。尽管为了清楚起见在图1中将突出元件的数目限制为3个，基底10上可以提供任意数目的突出元件。突出元件110、111和112可以通过印刷，例如喷墨印刷来制造，或者可以是通过放置(placing)过程施加到基底10上的小预制板(pre-shaped plate)。在喷墨印刷的情况下，使用的墨可以包括导电颗粒。在基底10上放置预制板的情况下，板可以用金属或金属合金，例如铜、铝或铁镍制造。可以通过焊接，例如扩散焊接，或胶合，将板附着到基底10上。突出元件110、111和112的高度可以在10nm至100μm范围内。可以根据基底10上的结构化的样式来布置突出元件110、111和112。可以用这样的方式将突出元件110、111和112施加到基底10上，即与它们被施加于其上的基底10的上表面相对的，突出元件110、111和112表面，可以形成与基底10的上表面平行的、基本平坦的表面。基底10本身可以用金属或金属合金制造。在一个实施例中，可以使用金属或金属合金以外的其它材料，例如陶瓷或纸制品。
在第一表面20a上具有第一电极21且在第二表面20b上具有第二电极22的半导体芯片20以这样的方式被放置在基底10上，即第一电极21被放置在突出元件110上。在一个实施例中，半导体芯片20可以是在第一表面20a上具有第三电极23的垂直功率半导体芯片，在这种情况下该垂直功率半导体芯片可以以这样的方式被放置，即第三电极23被放置在突出元件111上。半导体芯片20可以是功率半导体芯片，例如，功率晶体管、功率二极管或IGBT。在本实施例中，半导体芯片是具有漏电极22、源电极21和栅电极23的功率MOSFET。突出元件112可以以这样的方式被布置，即由表面20a定义的半导体芯片20的轮廓不与突出元件112重叠。突出元件110和111的区域可以分别大于电极21和23的区域，且突出元件110和111可以部分地延伸超过表面20a定义的半导体芯片20的轮廓。突出元件110、111和112可以被分别布置为半导体芯片20的电极21、22和23的接触衬垫。半导体芯片20可以通过回流焊接、扩散焊接或使用导电粘合剂的粘接键合(adhesive bonding)，被加到突出元件110和111上。
根据图1B，电介质薄膜120以结构化的方式放置在半导体芯片20、突出元件111、112的部分、和基底10之上。在一个实施例中，可以用印刷技术或物理或化学气相沉积技术来放置电介质薄膜120。电介质薄膜120可以被布置为暴露半导体芯片20的第二电极22的部分。导电薄膜130然后被放置到电介质薄膜120以及电介质薄膜120暴露的区域上。在一个实施例中，导电薄膜130可以被布置以形成第二电极22和突出元件112之间的电连接。电绝缘电介质薄膜120可以被布置以阻止导电薄膜130和突出元件110和111之间的电接触。导电薄膜130可以由金属材料组成，例如铜、金、银、镍或任何其它金属合成物，并可以被电化地(galvanically)放置到电介质薄膜120上。
根据图1C，半导体芯片20、电介质薄膜120、导电薄膜130和基底10用模制材料30覆盖。模制材料30可以被布置以覆盖其上安装了半导体芯片20的基底10的上表面，并可以被布置为留下基底10的下表面未被覆盖。在一个实施例中，模制材料30可以被布置为使导电薄膜130至少部分地被暴露。导电薄膜130被暴露的部分可以被用来将散热器连接到导电薄膜130，加快在半导体芯片20的操作期间产生的热量的消散。模制材料30可以被布置以填充突出元件110、111和半导体芯片20的表面20a之间的空间。
根据图1D，基底10随后被至少部分地移除。在一个实施例中，基底10可以以这样的方式被移除，即突出元件110、111和112留在得到的装置100中，但是模制材料30在最初覆盖基底10的表面处暴露。基底10可以以这样的方式被移除，即突出元件110、111和112与暴露的模制材料30的表面形成基本上平坦的表面。可以用研磨、蚀刻、烧蚀、减薄、焚化、焦烧或任何其它适用于基底材料的合适的方法来移除基底10。
图2A至2D示意性地示出了根据又一示例性实施例的又一方法的步骤。根据图2A，将半导体芯片20放置在基底10上与图1A示出的放置过程类似。图1A和图2A之间的区别在于，图2A中的突出元件210、211和212是基底10的组成部分，即，突出元件210、211和212和基底10是由同一片制成的。在一个实施例中，如果基底10是由例如铜、镍、铁镍或其它金属等金属材料或金属合金制成的，突出元件210、211和212可以通过冲压、轧压或模压(embossing)方法来产生。对本领域技术人员来说，很明显在一个装置中，突出元件210、211和212中的一些可以是基底10的组成部分，而其它的突出元件可以被作为不是初始连接到到基底10的、分离的元件来施加，如图1A所示。
根据图2B，电介质材料30然后被施加到半导体芯片20和基底10，至少部分地覆盖半导体芯片20和基底10。在一个实施例中，电介质材料30可以以这样的方式被施加，即至少一个通孔221在突出元件212上形成。或者，通孔221可以在放置电介质材料30之后形成，例如，通过激光束钻孔。电介质材料30可以被布置以覆盖半导体芯片20的第二表面20b。电介质材料30还可以被布置为使得半导体芯片20的第二表面20b被暴露。可以使用模版印刷或模制工艺，例如，底部填充模制，来施加电介质材料30。电介质材料30可以由聚合物组成，并可以，例如，包括环氧化物、聚亚安酯或硅树脂。此外，电介质材料可以包括由金属、金属氧化物、半导体、半导体氧化物、陶瓷和/或金刚石制成的填充剂材料。在一个实施例中，电介质材料30可以包括SiO2、Al2O3或AlN。但是，也可以用不包括填充剂材料的电介质材料30。电介质材料30可以在低于50℃的温度下，在一个实施例中是在室温，是液体，从而电介质材料30可以不用加热地放置。此后电介质材料30可以被加热以硬化电介质材料30。或者，可以使用在室温是固体，在放置前被加热的电介质材料30。
根据图2C，通过将导电元件230施加到电介质材料30来提供半导体芯片20的第二电极22和突出元件212之间的电连接。通孔221可以用被用来形成导电元件230的材料231来填充，在一个实施例中是铜、镍或其它金属或金属合金。根据图2B，如果用电介质材料30完全覆盖第二表面20b，在形成导电元件230之前，电介质材料30可以被部分地从第二电极22上移除。未朝向半导体芯片20的导电元件230的表面可以从电介质材料30暴露。在一个实施例中，导电元件230被暴露的表面可以被连接到散热器(未示出)，以消散在半导体芯片20的操作期间产生的热量。例如，可以通过，电沉积工艺或其它电镀工艺来完成施加导电元件230及用导电材料231填充通孔221。
与图1D类似，图2D示出了从得到的装置200移除基底的过程。
应该注意，图1A至图1D中示出的方法和图2A至图2D中示出的方法的组合也是可能的。例如，在根据图2A将半导体芯片20放置在基底10上后，有可能遵循根据图1B至1D的方法。或者，例如，有可能在执行根据图2A至2D的方法期间，根据图1B放置电介质层120。以上描述的方法的其它组合也是可行的。
图3A至3D示意性地示出了根据又一实施例的又一方法的步骤。根据图3A，与图1和图2中的半导体芯片20类似的半导体芯片20被放置在基底10上，第一表面20a朝向基底10。但是，与图1和图2不同，图3A中的半导体芯片20这样被放置在基底10上，即具有两个电极21和23的表面20b不朝向基底10。基底10具有突出元件11。为了清楚的目的，图3中示出的突出元件的数量限制在1个，但是，突出元件的数量可以大于1个。突出元件11和基底10可以是由同一片制造。在一个实施例中，元件11的主要突出方向可以与半导体芯片20相对于基底10的主要突出方向一致。基底10由导电材料制成，例如铜或铁镍。半导体芯片20以这样的方式被放置在基底10上，即突出元件11从由半导体芯片20的表面20b限定的轮廓之外的基底突出。在一个实施例中，突出元件11可以具有与半导体芯片20的厚度类似的高度，这样半导体芯片20的表面20b和不朝向基底10的突出元件11的上表面形成基本上平坦的表面。在突出元件11的高度与半导体芯片20的高度不相似的情况下，高度差可以随后被补偿，例如，通过电介质层或其它适当的手段。在一个实施例中，突出元件11的高度可以在50至500μm的范围内。突出元件11可以通过冲压、轧压或模压工艺形成，或可以通过弯曲基底10的边缘部分而形成。
根据图3B，电介质材料30被放置在基底10上。电介质材料30可以被布置以覆盖基底10，但是使半导体芯片20的表面20b暴露。电介质材料30也可以被布置以覆盖基底10的边缘表面，在一个实施例中是突出元件11的边缘表面。不朝向基底10的突出元件11的上表面可以从电介质材料30暴露。电介质材料30可以被布置以覆盖基底10与朝向半导体芯片20的表面相对的下表面。或者，基底10的下表面可以被暴露。散热器(未示出)可以连接到基底10被暴露的表面，以消散在半导体芯片20的操作过程中产生的热量。
根据图3C，电介质层320(或光阻层)被放置在电介质材料30、半导体芯片20和突出元件11上。电介质层320可以被结构化以形成多个开口321，在一个实施例中为，在半导体芯片20的第一电极21上的，在半导体芯片20的第三电极23和突出元件11上的各开口321。也可以通过选择性地放置电介质层320来形成开口321。
根据图3D，导电薄膜330放置在电介质层320上。在一个实施例中，导电薄膜330可以被结构化以覆盖各开口321并在各开口321上形成导电衬垫。导电薄膜320可以通过电沉积工艺放置，并可以具有5到500μm范围内的厚度。在电极21和23上的导电衬垫可以在由表面20b定义的半导体芯片20的轮廓上延伸。或者，导电层薄膜可以通过印刷工艺制造，例如，喷墨印刷。在这种情况下，电介质层320可以被略去。
图4A至4D示意性地示出了根据又一示例性实施例的又一方法。根据图4A，与图3A描述的半导体芯片20类似的半导体芯片20以第一表面20a在基底10上被放置。
根据图4B，电介质材料30在基底10上放置。电介质材料30可以以这样的方式放置，即半导体芯片20的第二表面20b被暴露。电介质材料30的放置可以通过印刷工艺，例如模版印刷，或者模制工艺。在一个实施例中，电介质材料30可以在被放置时具有低于50℃的温度，例如电介质材料可以在室温放置。被放置后，电介质材料30可以在较高温度被固化。该电介质材料可以具有与以上描述的装置300的电介质材料相同的特性。还可以通过蚀刻、激光束钻孔或其它合适的方法来部分移除电介质材料30以形成通孔。这些通孔可以用导电材料410来填充，例如，铜、镍或任何其它金属或金属合金。用导电材料410填充可以用电沉积工艺来完成。或者，由导电材料410制成的突出结构可以在放置电介质材料30之前形成。可以通过在基底10上安装金属凸块或通过电沉积来形成突出结构。在放置电介质材料30后，导电材料410随后被嵌入电介质材料30内。在一个实施例中，导电材料410的突出程度可以基本上与半导体芯片20的厚度相同，这样半导体芯片20的表面20b和导电材料410的结构的上表面可以基本上形成一个平坦的表面。在半导体芯片20和导电材料410的结构具有不同的高度的情况下，高度差可以以适当的方式补偿，例如，一层适当的材料。突出结构的高度可以在50至500μm范围内。
电介质材料30可以包括填充剂材料，在一个实施例中是SiO2。也可以使用其它的填充剂材料，如Al2O3和AlN。在电介质材料30内的填充剂材料的部分可以被调整至想要的电介质材料的热机械(thermomechanical)特性，例如热导率和热膨胀系数。可以使用较大量的填充剂材料来产生电介质材料30较高的热导率。电介质材料30还可以在基底10上的多层来放置，其中电介质材料30的每层可以包括不同部分的填充剂材料。这些层可以在基底10上以逐层的方式被布置。
根据图4C，光阻层420(或任何其它电介质层)随后在半导体芯片20、导电材料410和电介质材料30上放置。为了在结构410和电极21和23上构建开口，可以使用光刻法来结构化光阻层420。
金属种子层(metallic seed layer)421，如钛或钯，随后可以被施加到各开口以及光阻层420的一部分上。金属种子层421可以被施加到装置400的部分表面上，可以用作电极21，23及导电材料410的接触衬垫表面。金属种子层421可以，例如，无电(electroless)或通过溅射(sputerring)来放置，且具有在20至300nm范围内的厚度。
根据图4D，导电薄膜430随后在金属种子层421上放置。在一个实施例中，导电薄膜430的放置可以由电沉积完成。导电薄膜430可以具有大于5μm的厚度。在一个实施例中，由导电层形成的接触衬垫的延伸区域可以分别大于电极21，23的表面的区域和/或导电材料410的暴露表面的区域。接触衬垫可以在半导体芯片20的表面20b限定的半导体芯片20的轮廓上延伸。导电薄膜430可以由金属材料形成，在一个实施例中是铜、镍或任何其它合适的金属或金属合金。
作为电沉积的替代，导电薄膜430可以通过印刷工艺来生成，例如喷墨印刷。在这种情况下，电介质层420和/或种子层421可以被略去。
应该注意，在图1至4中详述的方法的工艺的组合也是可能的。本领域技术人员将进一步理解，图1至4中描述的方法可以在一个公共基底上，对于多于一个的半导体芯片来完成。有可能在公共基底上形成根据图1至4的方法的、彼此靠近的装置，并通过切片(dicing)或任何其它单个化工艺来分开这些装置。在一个实施例中，对本领域技术人员来说，在批量工艺中使用图1至图4示出的方法是显而易见的，其中至少两个装置可以同时形成，然后被互相分开。
此外，虽然针对若干实施中的仅一个公开了本发明的实施例的特定特征或方面，这种特征或方面可以按所期望的以及对任何给定的或特定的应用有利，与其它实施的一个或多个其它的特征或方面结合。而且，在具体的说明书或权利要求中使用“包括”、“具有”、“有”或其任何其它变体所涵盖的范围内，这种术语旨在以与术语“包含”类似的方式是包括性的。可能使用了术语“连接”和“耦接”及其派生词。应该理解，使用这些术语以指示两个元件互相合作或互相作用，而不考虑它们是否处于直接的物理或电接触，或它们彼此没有直接接触。而且，应该理解，本发明的实施例可以在离散电路、部分集成电路或完全集成电路或编程工具中实施。而且，术语“示例”仅指作为一个例子，而不是最好的或最佳的。也应该理解，为了简明起见且易于理解，此处描述的特征和/或元件是用相对于彼此的特定尺寸示出的，而实际的尺寸可以明显与这里示出的不一样。
尽管这里示出和描述了特定实施例，本领域普通技术人员将会理解，在不脱离本发明的范围内，各种替换和/或等价实施方式可以替代示出和描述的特定实施例。本申请旨在涵盖此处讨论的特定实施例的任何改变或变体。因此，本发明是由权利要求及其等价物所限定的。

Claims (9)

1.一种制造装置的方法，包括：
提供基底，该基底具有从基底的顶表面向上突出的第一元件；
提供半导体芯片，该半导体芯片具有在第一表面上的第一电极和在与第一表面相反的第二表面上的第二电极；
将半导体芯片放置在基底的第一元件上，其中半导体芯片的第一表面朝向基底的顶表面，使得半导体芯片的第一电极位于从基底的顶表面向上突出的第一元件上；
将半导体芯片的第二电极电耦接到从基底向上突出的第二元件；以及
至少部分地移除基底，并且在移除基底时不移除第一元件和第二元件。
2.如权利要求1所述的方法，包括通过研磨或蚀刻来移除基底。
3.如权利要求1所述的方法，其中基底是由金属或金属合金或陶瓷材料或纸材料制成的。
4.如权利要求1所述的方法，包括通过印刷来制造第一元件。
5.如权利要求4所述的方法，包括通过喷墨印刷来制造第一元件。
6.如权利要求1所述的方法，包括在将半导体芯片放置在基底上后，用电介质材料覆盖基底。
7.如权利要求6所述的方法，包括在半导体芯片和基底之间放置电介质材料。
8.如权利要求1所述的方法，其中半导体芯片具有位于第一表面上的第三电极，且第三电极电耦接到从基底突出的第三元件，并且其中在移除基底时不移除第三元件。
9.如权利要求1所述的方法，其中半导体芯片是功率半导体芯片。
CN2008101763832A 2007-11-26 2008-11-25 包括在基底上放置半导体芯片的制造装置的方法 Active CN101447442B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/944,724 US7727813B2 (en) 2007-11-26 2007-11-26 Method for making a device including placing a semiconductor chip on a substrate
US11/944724 2007-11-26

Publications (2)

Publication Number Publication Date
CN101447442A CN101447442A (zh) 2009-06-03
CN101447442B true CN101447442B (zh) 2011-11-16

Family

ID=40586091

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008101763832A Active CN101447442B (zh) 2007-11-26 2008-11-25 包括在基底上放置半导体芯片的制造装置的方法

Country Status (3)

Country Link
US (1) US7727813B2 (zh)
CN (1) CN101447442B (zh)
DE (1) DE102008057707B4 (zh)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021907B2 (en) 2008-06-09 2011-09-20 Stats Chippac, Ltd. Method and apparatus for thermally enhanced semiconductor package
US8441804B2 (en) * 2008-07-25 2013-05-14 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US8138587B2 (en) * 2008-09-30 2012-03-20 Infineon Technologies Ag Device including two mounting surfaces
TWI411073B (zh) * 2010-08-13 2013-10-01 Unimicron Technology Corp 嵌埋被動元件之封裝基板及其製法
DE102010042567B3 (de) * 2010-10-18 2012-03-29 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen eines Chip-Package und Chip-Package
US9093416B2 (en) 2011-11-28 2015-07-28 Infineon Technologies Ag Chip-package and a method for forming a chip-package
US8815651B2 (en) * 2011-12-30 2014-08-26 Infineon Technologies Ag Method for manufacturing an electronic device by reducing thickness of electronic members attached to a carrier
US20130229777A1 (en) 2012-03-01 2013-09-05 Infineon Technologies Ag Chip arrangements and methods for forming a chip arrangement
JP5558595B2 (ja) * 2012-03-14 2014-07-23 株式会社東芝 半導体装置及び半導体装置の製造方法
US11189537B2 (en) 2012-03-21 2021-11-30 Infineon Technologies Ag Circuit package, an electronic circuit package, and methods for encapsulating an electronic circuit
DE102013203350A1 (de) * 2013-02-28 2014-08-28 Osram Opto Semiconductors Gmbh Elektronisches Bauelement und Verfahren zu seiner Herstellung
US9437516B2 (en) 2014-01-07 2016-09-06 Infineon Technologies Austria Ag Chip-embedded packages with backside die connection
DE102014108295A1 (de) * 2014-06-12 2015-12-17 Osram Opto Semiconductors Gmbh Licht emittierendes Halbleiterbauelement
DE102014113697A1 (de) 2014-09-23 2016-04-07 Infineon Technologies Austria Ag Verfahren mit Inkjet-Prozessen und deren Anwendung
DE102014219794B4 (de) 2014-09-30 2020-06-18 Osram Opto Semiconductors Gmbh Elektrisches Bauelement und Verfahren zum Erzeugen eines elektrischen Bauelements
US9824976B1 (en) * 2016-08-16 2017-11-21 Infineon Technologies Americas Corp. Single-sided power device package
US11367669B2 (en) * 2016-11-21 2022-06-21 Rohm Co., Ltd. Power module and fabrication method of the same, graphite plate, and power supply equipment
JP7025181B2 (ja) * 2016-11-21 2022-02-24 ローム株式会社 パワーモジュールおよびその製造方法、グラファイトプレート、および電源装置
DE102018104144B4 (de) * 2018-02-23 2022-12-15 Technische Universität Chemnitz Verfahren zum Kontaktieren und Paketieren eines Halbleiterchips
DE102019102784A1 (de) * 2019-02-05 2020-08-06 Infineon Technologies Ag Halbleitervorrichtungen mit Radar-Halbleiterchip und zugehörige Herstellungsverfahren
US11133245B2 (en) 2019-10-25 2021-09-28 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US11437247B2 (en) 2020-07-20 2022-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
CN112864030B (zh) * 2021-01-18 2022-08-09 北京师范大学 光电探测芯片的封装方法和封装结构

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696033A (en) * 1995-08-16 1997-12-09 Micron Technology, Inc. Method for packaging a semiconductor die
JP2891665B2 (ja) * 1996-03-22 1999-05-17 株式会社日立製作所 半導体集積回路装置およびその製造方法
JPH10163368A (ja) * 1996-12-02 1998-06-19 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
US5830800A (en) * 1997-04-11 1998-11-03 Compeq Manufacturing Company Ltd. Packaging method for a ball grid array integrated circuit without utilizing a base plate
KR20010009350A (ko) * 1999-07-09 2001-02-05 윤종용 기판이 없는 칩 스케일 패키지 및 그 제조방법
US6573123B2 (en) * 1999-09-07 2003-06-03 Sai Man Li Semiconductor chip package and manufacturing method thereof
DE19954941C2 (de) 1999-11-16 2003-11-06 Fraunhofer Ges Forschung Verfahren zum Integrieren eines Chips innerhalb einer Leiterplatte
US6348399B1 (en) * 2000-07-06 2002-02-19 Advanced Semiconductor Engineering, Inc. Method of making chip scale package
JP2002076576A (ja) * 2000-08-23 2002-03-15 Nec Corp 配線パターン形成方法およびその方法に用いられる原版
CN1265451C (zh) * 2000-09-06 2006-07-19 三洋电机株式会社 半导体装置及其制造方法
US20020175400A1 (en) * 2001-05-26 2002-11-28 Gerber Mark A. Semiconductor device and method of formation
US6569709B2 (en) * 2001-10-15 2003-05-27 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
US7061077B2 (en) 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7217594B2 (en) 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
WO2004077547A2 (de) 2003-02-28 2004-09-10 Siemens Aktiengesellschaft Verbindungstechnik für leistungshalbleiter mit grossflächigen anschlüssen
US6867481B2 (en) 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
DE102004021054B4 (de) 2004-04-29 2014-09-18 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu seiner Herstellung
TWI249209B (en) * 2004-12-22 2006-02-11 Siliconware Precision Industries Co Ltd Semiconductor package with support structure and fabrication method thereof
DE102005057401B4 (de) * 2005-11-30 2009-10-08 Infineon Technologies Ag Halbleiterbauteil und Verfahren zu dessen Herstellung
DE102005061015B4 (de) * 2005-12-19 2008-03-13 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauteils mit einem vertikalen Halbleiterbauelement
DE102006021959B4 (de) * 2006-05-10 2011-12-29 Infineon Technologies Ag Leistungshalbleiterbauteil und Verfahren zu dessen Herstellung
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US20090127682A1 (en) * 2007-11-16 2009-05-21 Advanced Semiconductor Engineering, Inc. Chip package structure and method of fabricating the same

Also Published As

Publication number Publication date
CN101447442A (zh) 2009-06-03
DE102008057707A1 (de) 2009-06-04
DE102008057707B4 (de) 2018-05-09
US20090137086A1 (en) 2009-05-28
US7727813B2 (en) 2010-06-01

Similar Documents

Publication Publication Date Title
CN101447442B (zh) 包括在基底上放置半导体芯片的制造装置的方法
CN101393899B (zh) 半导体器件
CN102867804B (zh) 包括具有突出体的接触片的半导体器件及其制造方法
CN103178030A (zh) 包括安装在dcb衬底上的分立器件的模块及制造模块的方法
KR102214418B1 (ko) 전력 반도체 스위칭 장치 및 이를 포함하는 장치
CN101253627B (zh) 电路装置及其制造方法
CN105612613B (zh) 半导体装置
CN102403296A (zh) 半导体模块及其制造方法
CN104051377A (zh) 功率覆盖结构及其制作方法
CN110021590B (zh) 电源芯片集成模块、其制造方法及双面散热电源模块封装
CN104637832B (zh) 半导体装置及其制造方法
CN104051376A (zh) 功率覆盖结构及其制作方法
CN104051363A (zh) 芯片封装和用于制造该芯片封装的方法
CN108155168B (zh) 电子器件
JP4785139B2 (ja) 回路装置およびその製造方法
CN104425402A (zh) 密封的半导体器件
CN104392985A (zh) 包括衬底的多芯片器件
CN104064529A (zh) 半导体器件、半导体模块以及制造半导体器件和半导体模块的方法
US20210143103A1 (en) Power module and method for manufacturing power module
CN103377951A (zh) 半导体器件的制造方法和半导体器件
US9818730B2 (en) Semiconductor arrangement, method for producing a number of chip assemblies, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement
US10304751B2 (en) Electronic sub-module including a leadframe and a semiconductor chip disposed on the leadframe
CN104037152A (zh) 芯片载体结构、芯片封装及其制造方法
US20160021780A1 (en) Carrier, Semiconductor Module and Fabrication Method Thereof
JP2012238737A (ja) 半導体モジュール及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant