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CN107305861B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN107305861B
CN107305861B CN201610260314.4A CN201610260314A CN107305861B CN 107305861 B CN107305861 B CN 107305861B CN 201610260314 A CN201610260314 A CN 201610260314A CN 107305861 B CN107305861 B CN 107305861B
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via hole
semiconductor element
substrate
semiconductor
semiconductor device
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CN107305861A (zh
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S.库马
邱进添
陈火亮
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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SanDisk SemiConductor Shanghai Co Ltd
SanDisk Information Technology Shanghai Co Ltd
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Priority to CN201610260314.4A priority Critical patent/CN107305861B/zh
Priority to US15/394,986 priority patent/US10304816B2/en
Priority to TW105144304A priority patent/TWI645509B/zh
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Abstract

公开了一种半导体装置及半导体装置的制造方法。半导体装置包括：基板，具有在其表面上的接合垫；至少两个半导体元件，每个半导体元件具有第一表面和与第一表面相反的第二表面，经由贴附在各个半导体元件的第二表面上的元件贴附材料层在基板的表面上将至少两个半导体元件上下堆叠；整体通路孔，其完全的通过至少两个半导体元件和元件贴附材料层延伸，并沿整体通路孔的延伸方向具有实质上一致的直径，且与基板的表面上的接合垫对准；以及连续的导电材料，填充在整体通路孔中，并与基板的接合垫物理的和电气的接触。

Description

半导体装置及其制造方法
技术领域
本技术涉及半导体装置。
背景技术
对便携式消费电子产品的需求的强劲增长推动了对大容量存储器器件的需要。非易失性半导体存储器器件，诸如闪存存储卡，正变得广泛用于满足对数字信息存储和交换的日益增长的需求。它们的便携性、多功能性和坚固的设计，以及其高可靠性和大容量，已经使这样的存储器件理想地用于各种各样的电子器件中，包含例如数码相机、数字音乐播放器、视频游戏控制台、PDA和蜂窝电话。
发明内容
在本技术的方面中，一种制造半导体装置的方法包括如下步骤。提供至少两个半导体元件，每个所述半导体元件具有第一表面和与所述第一表面相反的第二表面。在每个所述半导体元件中形成通路孔，所述通路孔完全通过各个所述半导体元件从所述第一表面至所述第二表面延伸。在每个所述半导体元件的第二表面上贴附元件贴附材料层。在每个所述半导体元件中在对应于所述通路孔的位置移除所述元件贴附材料。在基板的表面上将所述至少两个半导体元件上下对准并经由所述元件贴附材料层堆叠，使所述半导体元件的通路孔彼此对准以形成整体通路孔，所述整体通路孔完全通过所述至少两个半导体元件和所有元件贴附材料层延伸，所述整体通路孔沿所述整体通路孔的延伸方向具有实质上一致的直径。最终，通过一次金属填充工艺使用导电材料来填充所述整体通路孔。
在实施例中，每个所述半导体元件提供有位于所述第一表面上并标记所述通路孔的位置的对准标记。对准标记包括在各个所述半导体元件的第一表面上的通路孔的位置的垫。
在实施例中，通过干法反应离子蚀刻工艺或激光钻孔工艺来直接形成完全通过各个所述半导体元件延伸的所述通路孔。可替代的，通过干法反应离子蚀刻工艺或激光钻孔工艺形成部分的通过各个所述半导体元件的盲通孔，随后通过在所述半导体元件的第二表面上的背侧研磨工艺，以形成完全的通过所述各个半导体元件的所述通路孔，从而形成所述通路孔。
在实施例中，所述基板还包括在所述基板的表面上的接合垫。在基板的表面上对准和堆叠所述至少两个半导体元件的步骤中，将所述至少两个半导体元件的通路孔与所述基板的表面上的接合焊垫对准，且所述整体通路孔中的导体材料与所述基板的表面上的接合焊垫物理的和电气的接触。
在实施例中，所述每个半导体元件是裸芯或晶片。
在本技术的另一方面中，一种制造半导体装置的方法包括如下步骤。提供至少两个半导体元件。每个所述半导体元件具有第一表面和与所述第一表面相反的第二表面。在每个所述半导体元件的第二表面上贴附元件贴附材料层。在基板的表面上将所述至少两个半导体元件上下对准并经由所述元件贴附材料层堆叠。形成整体通路孔，所述整体通路孔完全的通过所述至少两个半导体元件和所述元件贴附材料层延伸，并沿所述整体通路孔的延伸方向具有实质上一致的直径。通过一次金属填充工艺将导电材料填充在所述整体通路孔中。
在本技术的另一方面中，一种半导体装置包括：基板，具有在所述基板的表面上的接合垫；至少两个半导体元件，每个所述半导体元件具有第一表面和与所述第一表面相反的第二表面，所述至少两个半导体元件经由贴附在各个所述半导体元件的第二表面上的元件贴附材料层在所述基板的表面上上下堆叠；整体通路孔，其完全的通过所述至少两个半导体元件和所述元件贴附材料层延伸，并沿所述整体通路孔的延伸方向具有实质上一致的直径，且所述整体通路孔与所述基板的表面上的接合垫对准，以及连续的导电材料，填充在所述整体通路孔中，并与所述基板的接合垫物理的和电气的接触。
在本技术的另一方面中，每个所述半导体元件是裸芯或晶片。所述裸芯包括控制器裸芯或存储器裸芯。所述半导体装置还包括设置在所述整体通路孔的内侧壁上的连续的金属籽层。所述半导体装置还包括包封堆叠在所述基板的表面上的所述至少两个半导体元件的模塑料。
附图说明
图1是具有TSV结构的半导体装置的制造方法的流程图。
图2A至图2J是示出了图1所示的制造方法的不同阶段的示意性侧视图。
图3是根据本技术的第一实施例的具有TSV结构的半导体装置的制造方法的流程图。
图4A至图4F是示出了图3所示的制造方法的不同阶段的示意性侧视图。
图5是根据本技术的第二实施例的具有TSV结构的半导体装置的制造方法的流程图。
图6A至图6E是示出了图5所示的制造方法的不同阶段的示意性侧视图。
图7是根据本技术的实施例的半导体装置的示意性侧视图。
具体实施方式
现在参照图3至图7来描述实施例，其涉及半导体装置的制造方法及半导体装置。应该理解的是，本技术可以按照很多不同形式来实施，而不应被解释为限于本文所阐述的实施方式。而是，提供这些实施例以使得本公开将是彻底的和完整的，并且将本技术充分地传达给本领域的技术人员。实际上，本技术旨在覆盖这些实施例的替代、变型和等同，其包括在由所附权利要求限定的本发明的范围和精神之内。此外，在本技术的以下详细描述中，许多具体的细节被阐述以便提供本发明的彻底理解。然而，本领域的普通技术人员将清楚，本发明可以没有这样的具体细节来实践。.
如本文可使用的术语“左”、“右”、“顶部”、“底部”、“上”、“下”、“垂直”和/或“水平”仅是为了方便且为说明性目的，并不意味着限制本发明的描述，这是由于所参考的项目可在位置和方向进行交换。而且，如本文所使用的，冠词“一”和“一个”旨在包括单数和复数的形式，除非文中另外明确的指出。术语“实质上”和/或“大约”意味着对于给定的应用，规定的尺寸或参数可以在可接受的制造公差内来改变。在一个实施例中，可接受的制造公差为±0.25％。
在所有的附图中，相同或类似的元件由具有相同的末尾两位数字的相同样式来标记。
尽管已知各种封装配置，半导体存储装置可以制造为三维系统级封装(3D-SiP)的形式。硅通孔(TSV)互连是一种已知的3D-SiP技术，用于短互连距离和高速度。TSV是在半导体裸芯中生成垂直通孔，并通过电镀工艺在垂直通孔中沉积导电材料以实施互连的技术。
图1是具有TSV结构的半导体装置的制造方法的流程图。图2A至图2J是示出了图1所示的制造方法的不同阶段的示意性侧视图。
如图1所示，本方法以制备基板的步骤S110开始。如图2A所示，基板110包括在基板110的上表面上的接合垫112，以及形成在基板110的上表面上并覆盖接合垫112的氧化物层120。接合垫112电连接至将在后续的工艺中被设置在基板110上半导体裸芯。氧化物层120作为用于贴附半导体裸芯的接合层。
接下来，如图2B至图2D所示，在步骤S120中，通孔132形成在半导体裸芯130中，且随后在步骤S130中，绝缘层134形成在通孔132的侧壁上，接下来是背侧研磨步骤S140，以减少半导体裸芯130的厚度，从而在半导体裸芯130中形成通路孔130。
接下来，如图2E所示，在步骤S150中，半导体裸芯130被堆叠并经由接合氧化物层120贴附在基板110上，使半导体裸芯130的通路孔132与埋设在氧化物接合层120的下面的基板110的接合垫112对准。半导体裸芯130在基板110上的对准通常是通过包括图像捕捉装置的图案识别系统来实施，图案识别系统识别位于半导体裸芯130和基板110上的基准标记。这些基准标记可以由相对于施加在基板上的涂层具有图像对比度的金属垫制成。图案识别系统利用基准标记来对准和校准半导体裸芯130相对于基板110的坐标信息。由于在上述制造工艺中接合垫112被接合氧化物层120覆盖，其对于图案识别系统的图像捕捉装置不可见，因此不能用来作为基准标记。在这种情况下，额外的基准标记(未示出)形成在基板110上，以便通过图案识别系统来对准半导体裸芯130和基板110。
接下来，在步骤S160中，移除在接合垫112上的氧化物接合层120，以暴露接合垫112的表面，如图2F所示。接下来，在步骤S170中，籽层140形成在绝缘层134的暴露的表面上，如图2G所示。随后如图2H所示，在步骤S180中，通过电镀工艺将导电材料层150沉积在籽层140上，以使导电材料填充通路孔132。如果封装体包括单一的半导体裸芯130，用于在这样的封装体中形成TSV结构的工艺在此结束。如果封装体包括多于一个半导体裸芯130，则工艺进行至步骤S190，在步骤S190中，半导体裸芯130上的导电材料150的层被移除，从而导电材料150仅在与通孔132和接合垫112相对应的位置保留。且导电材料150被额外的氧化物接合层120覆盖，如图2I所示。随后对额外的半导体裸芯130重复上文所述的步骤S120至S180。最终的结构在图2J中示出。
如图2J所示，封装体100包括彼此对准的多个叠置的TSV结构，这可能导致失准问题。此外，由于多次电镀工艺，在涉及多次热循环的多个步骤中沉积TSV结构，这会在TSV结构的区域中形成过度的应力，减弱半导体裸芯130的机械强度。由于多次沉积产生的界面缺陷，多个叠置的TSV结构还可能增加了上面的半导体裸芯和下面的半导体裸芯中的TSV结构之间的界面电阻。
将参照图3至图4F来描述根据本技术的第一实施例的半导体装置的制造方法。图3是根据本技术的第一实施例的具有TSV结构的半导体装置的制造方法的流程图。图4A至图4F是示出了图3中所示的制造方法的不同阶段的示意性侧视图。
如图3和图4A所示，本方法以制备基板的步骤S310开始。图4A是基板410的示意性侧视图。基板410可以是线路板，例如是柔性印刷电路板(FPCB)，或用于支承设置在其上的任何半导体元件的临时载具。例如，基板410可以包括形成在绝缘芯层的一个表面或两个表面上的导电图案。基板410包括接合垫412，接合垫412用于与将要设置在基板410上的半导体元件电连接。例如，接合垫412位于基板410的上表面上，并且可以是形成在上表面上的导电图案的一部分。接合垫412例如由铜、铝、铜上镀金、铝上镀金制成。
接下来，如图4B所示，在步骤S320中，通路孔432形成在每个半导体元件430中。通路孔432在如图4B所示的Z方向上从半导体元件430的上表面至相反的下表面完全的通过半导体元件430延伸。半导体元件430可以包括具有裸芯的阵列的晶片，或从这样的晶片单体化的单独的裸芯。例如，半导体元件430可以是具有实质上相同的尺寸的存储器裸芯。每个半导体元件430可以提供有对准标记431，对准标记431表示将要形成通路孔432的位置。例如，对准标记431是位于通路孔432将要形成在半导体元件430的表面上的位置的接合垫，如图4B(a)所示。对准标记431的数目和布置不限于图4B(a)所示的实施例。对准标记431允许用于后续的形成通路孔432的工艺的精确和快速的对准。
接下来，通路孔432形成在由对准标记431标识的位置。可以通过干法反应离子蚀刻(DRIE)工艺或激光钻孔工艺，直接形成在Z方向上完全通过半导体元件430延伸的通路孔432，如图4B(c)所示。可替代的，通路孔432也可以如下形成：通过在Z方向上形成部分的通过半导体元件430延伸的盲通孔432’，如图4B(b)所示，接下来通过背侧研磨工艺减少半导体元件430的厚度，从而形成在Z方向上完全通过半导体元件430延伸的通路孔432，如图4B(c)所示。干法反应离子蚀刻(DRIE)工艺或激光钻孔工艺，或者背侧研磨工艺对于本领域技术人员来说是已知的，且将不再进一步详细的描述。在半导体元件430中位于相对应的对准位置的通路孔432具有实质上相同的直径。通路孔432在半导体元件430中的数目和布置不限于图4B所示的实施例，且可以被相应的调整。
接下来，在步骤S330中，元件贴附材料层440贴附在每个半导体元件430的下表面上，如图4C所示。元件贴附材料层440可以包括在两个表面上施加有粘合剂的聚合物基底。元件贴附材料层440例如是用于常规裸芯贴附工艺的裸芯贴附膜(DAF)，因此将不再进一步详细的描述。接下来，在步骤S340中，在对应于半导体元件430的通路孔432的位置移除元件贴附材料层440，如图4D所示。可以通过本领域技术人员已知的任何干法蚀刻工艺来移除元件贴附材料，干法蚀刻工艺例如是激光烧蚀工艺或激光钻孔工艺，且将不再进一步详细的描述。
接下来，在步骤S350中，在形成有接合垫412的基板410的表面上将至少两个半导体元件430上下对准并经由贴附在各个半导体元件430的下表面上的元件贴附材料层440堆叠。每个半导体元件430设置为使得每个半导体元件430的通路孔432与基板410的表面上的接合垫412对准。可以通过上文所述的典型的图案识别系统，例如利用通路孔432和接合垫412作为基准标记来实施对准。按照这种方法，在步骤S350之后，整体通路孔434形成为完全通过至少两个半导体元件430和裸芯贴附材料层440延伸，到达基板410上的接合垫412。由于位于堆叠的半导体元件430中的相对应的位置的对准的通路孔432具有相同的直径，由那些通路孔432构成的整体通路孔434沿整体通路孔434的延伸方向具有实质上一致的直径，如图4E所示。
在图3所示的第一实施例中，在对准和堆叠所有的半导体元件430的步骤S350之前，在步骤S340中，在对应于通路孔432的位置移除元件贴附材料层450的部分。本技术不限于此。在对准和堆叠所有的半导体元件430的步骤S350之后，可以在例如激光钻孔工艺的一次移除工艺中在通路孔432的位置移除用于所有的堆叠的半导体元件430的元件贴附材料层450的部分，以便形成整体通路孔434。
最终，在步骤S360中，通过一次金属填充工艺使用导电材料450填充整体通路孔434。导电材料450与基板410的表面上的接合垫412物理的和电气的接触，由此形成具有将半导体元件430和基板410电连接的TSV互连的半导体装置400。导电材料450可以包括金、铜或适合于互连和金属填充工艺的其它金属或合金。金属填充工艺可以是本领域技术人员已知的电镀工艺。在电镀工艺之前，连续的籽层(未示出)可以形成在整体通路孔434的侧壁上，以有助于该电镀工艺。由导电材料450制成的TSV互连的数目和布置不限于图4F所示出的实施例，且可以被相应的调整。具有TSV互连的半导体装置400还可以在后续的本领域技术人员已知的模塑工艺中被包封。
根据图3所示的本技术的第一实施例，可以通过典型的图案识别系统将半导体元件430的通路孔432与基板410的表面上的暴露的接合垫412容易的对准，由此改善对准精度。与半导体装置100中的接合半导体裸芯130的氧化物接合层120相比，通过例如DAF的聚合物的元件贴附材料层440来贴附半导体装置400中的半导体元件430，由于元件贴附材料450的聚合物性质和薄厚度，由此允许低温工艺并减少半导体装置400的总厚度。此外，根据本技术，在制造工艺期间仅对半导体装置400执行一次金属填充工艺，由此减少了热循环的数量，这进而减少了TSV结构周围的残余应力并改善了半导体装置400的机械强度。另外，由导电材料450在半导体装置400中形成的TSV结构是在一次金属填充工艺中形成的连续结构，而没有图2J所示的半导体装置100中的界面缺陷，由此改善了导电率和信号传输。半导体元件430可以是晶片或裸芯，由此本技术的实施例可以应用于裸芯至裸芯互连、晶片至晶片互连、或裸芯至晶片互连。
在第一实施例中，在基板410上对准和堆叠半导体元件430的步骤之前，通路孔432分别形成在单独的半导体元件430中。本技术不限于此。将参照图5至图6E来描述根据本技术的第二实施例的半导体装置的制造方法。图5是根据本技术的第二实施例的具有TSV结构的半导体装置的制造方法的流程图。图6A至图6E是示出了图5所示的制造方法的不同阶段的示意性侧视图。
如图5和图6A所示，本方法以制备基板的步骤S510开始。图6A是基板610的示意性侧视图。基板610与第一实施例描述的基板410实质上相同，因此这里将不再重复描述。
接下来，如图6B所示，在步骤S520中，元件贴附材料层640贴附在每个半导体元件630的表面上。每个半导体元件630可以提供有对准标记631，对准标记631表示通路孔将要形成的位置。半导体元件630和元件贴附材料层640的其它方面与第一实施例中的半导体元件430和元件贴附材料层440实质上相同，因此这里将不再重复描述。
接下来，在步骤S530中，在形成有接合垫612的基板610上将至少两个半导体元件630上下对准并经由元件贴附材料层640堆叠。通过典型的图案识别系统，利用每个半导体元件630上的对准标记631和基板610上的接合垫612作为基准标记来实施对准，如图6C所示。
接下来，在步骤S540中，通过本领技术人员已知的干法反应离子蚀刻(DRIE)工艺或激光钻孔工艺，在对准标记631的位置，使整体通路孔630形成为完全的通过所有的半导体元件630和所有的元件贴附材料层640延伸，以到达接合垫612，如图6D所示。
最终，在步骤S550中，通过一次金属填充工艺使用导电材料650填充整体通路孔634。导电材料650与基板610的表面上的接合垫612物理的和电气的连接，由此形成具有将半导体元件630和基板610电连接的TSV互连的半导体装置400，如图6E所示。具有TSV互连的半导体装置600还可以在后续的本领域技术人员已知的模塑工艺中被包封。本技术的第二实施例的其它方面与本技术的第一实施例实质上相同，因此这里将不再重复描述。
根据图5所示的本技术的第二实施例，在对准和堆叠半导体元件630的步骤之后，形成半导体装置600的整体通路孔634，由此避免本技术的第一实施例中的各个半导体元件的单独的通路孔的对准失准的危险。在这种情况下，整体通路孔可以具有更光滑的内表面，用于进一步改善形成在整体通路孔内的连续的导电材料的均匀性。然而，与本技术的第一实施例相比，在第二实施例的单一的步骤S540中形成的通路孔634的大高宽比(aspectratio)增加了工艺复杂性并减少了工艺公差。
图4F和图6E分别示出了根据本技术的实施例的分别包括两个半导体元件和单一的TSV互连的半导体装置400和半导体装置600。本技术不限于此，且可以包括更多的半导体元件和TSV互连。图7是根据本技术的实施例的半导体装置700的示意性侧视图。
如图7所示，半导体装置700包括基板710，基板710在其表面上具有多个接合垫712。基板710可以是例如柔性印刷电路板(FPCB)的线路板。特别的，基板710包括施加在绝缘芯层的两个表面上的导电图案，其没有详细的示出。绝缘芯层可以由各种电介质材料制成，电介质材材料例如是聚酰亚胺层压板、包括FR4和FR5的环氧树脂、双马来酰亚胺三嗪(BT)、或预浸料(PP)材料。
半导体装置700还包括多个半导体元件730，经由贴附在每个半导体元件730的下表面上的各个元件贴附材料层740在基板710的表面上将多个半导体元件730上下的堆叠。半导体元件730可以是晶片或裸芯，由此本技术的实施例可以应用于裸芯至裸芯互连，晶片至晶片互连、或裸芯至晶片互连。本实施例中的半导体元件的数量不限于如图7中所示的四个，且在需要时可被调整。
半导体装置700还包括多个整体通路孔734。每个整体通路孔734完全的通过所有的半导体元件730和所有的元件贴附材料层740延伸。每个整体通路孔734沿各个整体通路孔734的延伸方向具有实质上一致的直径，并与基板719的表面上的相对应的接合垫712对准。通过例如电镀工艺的单一的金属填充步骤，将导电材料750填充在各个整体通路孔734中，以形成各个TSV互连。在这种情况下，导电材料750与基板710的相对应的接合垫712物理的和电气的接触，并贯通整体通路孔734是连续的而没有额外的界面。半导体装置700还可以包括形成在每个整体通路孔734的侧壁上的籽层(未示出)，以有助于电镀工艺。本实施例中的TSV互连的数量不限于如图7所示的两个，且在需要时可被调整。另外，半导体装置700还可以包括在基板710上包封半导体元件730的模塑料760。
根据本技术的实施例，通过堆叠在基板上的半导体元件形成具有实质上相同的直径的整体通路孔，用于TSV互连，由此改善具有TSV互连的半导体装置的结构完整性和机械强度。另外，与具有通过多次电镀工艺形成的TSV结构的半导体装置相比，通过单一的金属填充步骤填充在整体通路孔中的连续的导电材料由于较少的界面缺陷改善了导电率。.
为了说明和描述的目的，已经呈现了本发明的前面的详细描述。其不旨在穷尽或限制本发明为公开的精确形式。根据上述教导的许多变型和变化是可能的。选择所描述的实施例是为了最好的说明本发明的原理及其实际应用，从而使本领域的技术人员能最好地利用在各种实施例中的本发明和各种变型以适合于预期的特定用途。本发明的范围由所附的权利要求限定。

Claims (8)

1.一种制造半导体装置的方法，包括如下步骤：
提供至少两个半导体元件，每个所述半导体元件具有第一表面和与所述第一表面相反的第二表面；
在所述至少两个半导体元件中的每一个中形成通路孔，所述通路孔完全的通过各个所述半导体元件从所述第一表面至所述第二表面延伸；
在所述至少两个半导体元件中的每一个的第二表面上形成元件贴附材料层，所述通路孔不被所述元件贴附材料覆盖；
在基板的表面上将所述至少两个半导体元件上下对准并经由所述元件贴附材料层堆叠，使所述半导体元件的通路孔彼此对准以形成整体通路孔，所述整体通路孔完全通过所述至少两个半导体元件和所有元件贴附材料层延伸，所述整体通路孔沿所述整体通路孔的延伸方向具有实质上一致的直径；以及
通过一次金属填充工艺使用导电材料来填充所述整体通路孔。
2.如权利要求1所述的方法，其中每个所述半导体元件提供有位于所述第一表面上并标记所述通路孔的位置的对准标记。
3.如权利要求2所述的方法，其中所述对准标记包括在各个所述半导体元件的第一表面上的通路孔的位置的垫。
4.如权利要求1所述的方法，其中通过干法反应离子蚀刻工艺或激光钻孔工艺来直接形成完全通过各个所述半导体元件延伸的所述通路孔。
5.如权利要求1所述的方法，其中通过干法反应离子蚀刻工艺或激光钻孔工艺形成部分的通过各个所述半导体元件的盲通孔，随后通过在所述半导体元件的第二表面上的背侧研磨工艺，以形成完全的通过所述各个半导体元件的所述通路孔，从而形成所述通路孔。
6.如权利要求1所述的方法，其中所述基板还包括在所述基板的表面上的接合垫，以及
在基板的表面上对准和堆叠所述至少两个半导体元件的步骤中，将所述至少两个半导体元件的通路孔与所述基板的表面上的接合焊垫对准，且所述整体通路孔中的导电材料与所述基板的表面上的接合焊垫物理的和电气的接触。
7.如权利要求1所述的方法，其中所述金属填充工艺是电镀工艺。
8.如权利要求1所述的方法，其中每个所述半导体元件是裸芯或晶片。
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