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US20110248408A1 - Package substrate and fabricating method thereof - Google Patents

Package substrate and fabricating method thereof Download PDF

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Publication number
US20110248408A1
US20110248408A1 US13/064,437 US201113064437A US2011248408A1 US 20110248408 A1 US20110248408 A1 US 20110248408A1 US 201113064437 A US201113064437 A US 201113064437A US 2011248408 A1 US2011248408 A1 US 2011248408A1
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US
United States
Prior art keywords
forming
wafer
wiring layer
cavity
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/064,437
Inventor
Seung Wook Park
Young Do Kweon
Jang Hyun KIM
Tae Seok Park
Su Jeong Suh
Jae Gwon Jang
Nam Jung Kim
Seung Kyu Lim
Kwang Keun Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Sungkyunkwan University Foundation for Corporate Collaboration
Original Assignee
Samsung Electro Mechanics Co Ltd
Sungkyunkwan University Foundation for Corporate Collaboration
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd, Sungkyunkwan University Foundation for Corporate Collaboration filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD., SUNGKYUNKWAN UNIVERSITY FOUNDATION FOR CORPORATE COLLABORATION reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KWEON, YOUNG DO, PARK, SEUNG WOOK, JANG, JAE GWON, KIM, JANG HYUN, KIM, NAM JUNG, LEE, KWANG KEUN, LIM, SEUNG KYU, PARK, TAE SEOK, SUH, SU JEONG
Publication of US20110248408A1 publication Critical patent/US20110248408A1/en
Priority to US14/063,672 priority Critical patent/US8951835B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19015—Structure including thin film passive components
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T436/00—Chemistry: analytical and immunological testing
    • Y10T436/17—Nitrogen containing
    • Y10T436/170769—N-Nitroso containing [e.g., nitrosamine, etc.]

Definitions

  • the present invention relates to a package substrate and a method fabricating thereof, and more particularly, to a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing component mounting density, and a method fabricating thereof.
  • An embedded process which is one method of implementing the fine circuit pattern, has a structure in which a circuit is impregnated with an insulating material, and may improve the flatness and strength of a product and have less circuit damage, whereby the method is appropriate for implementing the fine circuit pattern.
  • a substrate has been configured by mounting or stacking packages or devices directly on the substrate.
  • the packages when the packages are mounted on double sides or a single side of the substrate, the entire package area may be reduced.
  • the substrate having the electronic device embedded therein is fabricated according to the related art, there is a risk that the electronic device may be damaged due to use of adhesive tape, or the like, and a fabricating process of the substrate is significantly complicated.
  • An aspect of the present invention provides a package substrate capable of corresponding to a fine pitch, while securing an interval between packages required when electronic devices are stacked on a bottom package, by forming metal bumps on an upper surface of the bottom package and bonding each of solder balls coupled to a lower surface of a top package and solder balls coupled to an lower surface of the electronic devices to the metal bumps, and a method fabricating thereof.
  • a package substrate including: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filling the through-hole; and one or more electronic device connected to the via.
  • the via may be connected to the electronic device or an external device through solder bumps.
  • the chip may be a multilayer ceramic capacitor (MLCC).
  • MLCC multilayer ceramic capacitor
  • the electronic device may be at least one selected from a resistor and an inductor.
  • the wafer may be made of silicon.
  • the package substrate may further include an insulating layer formed to cover the chip and the electronic device and exposing a portion of the first and second wiring layers.
  • a method of fabricating a package substrate including: forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region; forming a through-hole penetrating through the wafer and a via filling the through-hole; forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity; and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.
  • the method may further include a polishing at least one of the upper surface and a lower surface of the wafer before the forming of the cavity.
  • the forming of the cavity may include: forming a first insulating film on the upper surface of the wafer; forming a first insulating pattern for forming the cavity by etching the first insulating film; and forming the cavity by etching the wafer using the first insulating pattern.
  • the forming of the cavity by etching the wafer may include wet etching of the wafer using a potassium hydroxide (KOH) solution.
  • KOH potassium hydroxide
  • the forming of the through-hole may include: forming a first photosensitive resin layer on the upper surface or a lower surface of the wafer; forming a first photosensitive pattern by exposing and developing the first photosensitive resin layer; and forming the through-hole by etching the wafer using the first photosensitive pattern.
  • the forming of the via may include: forming a second insulating film on a surface of the wafer including the through-hole and the cavity; forming a plating seed layer on the second insulating film; and filling the through-hole with a conductive material using an electroplating method.
  • the forming of the first wiring layer and the second wiring layer may include: forming a second photosensitive pattern on a region in the wafer, in which the first wiring layer and the second wiring layer are not formed; forming a wiring material on the upper surface of the wafer; removing the second photosensitive pattern and the wiring material formed on the second photosensitive pattern using a lift-off method.
  • the method may further include bonding the chip to each of the first wiring layer and the second wiring layer by allowing the wafer to reflow, after the mounting of the chip in the cavity.
  • the chip may be a multilayer ceramic capacitor (MLCC).
  • MLCC multilayer ceramic capacitor
  • the electronic device may be at least one selected from a resistor and an inductor.
  • the method may further include forming an insulating layer exposing a portion of the first and second wiring layers and covering the chip and the electronic device.
  • the method may further include connecting the via to the electronic device or an external device through solder bumps.
  • FIG. 1 is a top plan view schematically showing a package substrate according to an exemplary embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1 ;
  • FIGS. 3A through 3K are cross-sectional views schematically showing a method of fabricating a package substrate according to an exemplary embodiment of the present invention.
  • FIGS. 1 and 2 a package substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2 .
  • FIG. 1 is a top plan view schematically showing a package substrate 1 according to an exemplary embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1 .
  • a package substrate is configured to include a wafer 10 having a cavity C formed in an upper surface thereof, the cavity including a chip mounting region T, a first wiring layer 13 a and a second wiring layer 13 b formed to be spaced apart from the first wiring layer 13 a , which are formed to be extended in the cavity C, a chip M positioned in the chip mounting region T to be connected to the first wiring layer 13 a and the second wiring layer 13 b , a through-hole H penetrating through the wafer 10 , a via V filled in the through-hole H, and one or more electronic devices R and L connected to the via V.
  • the package substrate 1 may further include an insulating layer 14 covering the chip M and the electronic devices R and L and exposing a portion of the first wiring layer 13 a and the second wiring layer 13 b.
  • the wafer 10 may be made of silicon, and the via V may be connected to the electronic devices R and L or an external device 16 through solder bumps 15 .
  • the chip M may be a multilayer ceramic capacitor (MLCC), and the electronic devices R and L may be at least one selected from a resistor and an inductor.
  • MLCC multilayer ceramic capacitor
  • the chip M and the electronic devices R and L are not limited thereto.
  • FIGS. 3A through 3K a method of fabricating a package substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A through 3K .
  • FIGS. 3A through 3K are cross-sectional views schematically showing a method of fabricating a package substrate according to an exemplary embodiment of the present invention.
  • a method of fabricating a package substrate 1 includes forming a cavity in at least one region of an upper surface of a wafer 10 , the cavity including a chip mounting region T, forming a through-hole H penetrating through the wafer 10 and a via V filled in the through-hole H, forming a first wiring layer 13 a and a second wiring layer 13 b spaced apart from the first wiring layer 13 a , which are extended in the cavity C, and a mounting a chip M in the cavity C to be connected to the first wiring layer 13 a and the second wiring layer 13 b.
  • a first insulating film (not shown) is formed on the upper surface of the wafer 10 and is then etched to form a first insulating pattern 11 a for forming the cavity C.
  • the first insulating film may be made of silicon nitride (Si 3 N 4 ); however, a material of forming the first insulating film is not limited thereto.
  • a reactive ion etching (RIE) method may be used; however, an etching method thereof is not limited thereto.
  • the cavity C is formed in the upper surface of the waver 10 by using the first insulating pattern 11 a as a mask.
  • the wafer 10 may be subject to wet etching using a potassium hydroxide (KOH) solution by using the first insulating pattern 11 a as the mask; however, solution used in the wet etching is not limited thereto.
  • KOH potassium hydroxide
  • a first photosensitive resin layer (not shown) is formed on a lower surface of the wafer and is then exposed and developed to form a first photosensitive pattern 11 b.
  • the wafer 10 is etched using the first photosensitive pattern as a mask to form the through-hole H.
  • a RIE method may be used; however, an etching method thereof is not limited thereto.
  • a second insulating film 12 a is formed on a surface of the wafer 10 including the through-hole H and the cavity C, and a plating seed layer (not shown) is formed on the second insulating film 12 a .
  • the second insulating film 12 a may be made of silicon oxide (SiO 2 ); however, a material of the second insulating film 12 a is not limited thereto.
  • the via V is formed by filling the through-hole H with a conductive material using an electroplating method.
  • a second photosensitive pattern 12 b is formed on a region in the wafer 10 , in which the first wiring layer 13 a and the second wiring layer 13 b are not formed. Then, as shown in FIG. 3H , a wiring material 13 is formed on the upper surface of the wafer 10 .
  • the second photosensitive pattern 12 b and the wiring material 13 formed on the second photosensitive pattern 12 b are simultaneously removed by a liftoff method.
  • the wafer 10 is immersed into an organic solvent and then slightly shaken, the second photosensitive pattern 12 b is dissolved, and/or the organic solvent is penetrated into an interface between the wafer 10 and the second photosensitive pattern 12 b , whereby the second photosensitive pattern 12 b and the wiring material 13 formed on the second photosensitive pattern 12 b may be simultaneously removed.
  • the first wiring layer 13 a and the second wiring layer 13 b may be formed in portions in which they are intended to be formed.
  • the chip M is mounted in the cavity C, and the wafer 10 then reflows to individually bond the chip M to the first wiring layer 13 a and the chip M to the second wiring layer 13 b .
  • the chip M may be the multilayer ceramic capacitor (MLCC).
  • the via V is connected to the electronic devices R and L or the external device 16 through the solder bumps 15 to complete the package substrate as shown in FIGS. 1 and 2 .
  • package substrate capable of having the passive device having a predetermined capacity embedded therein, while reducing the pattern size and increasing the component mounting density, and a method fabricating thereof may be provided.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the priority of Korean Patent Application No. 10-2010-0032244 filed on Apr. 8, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a package substrate and a method fabricating thereof, and more particularly, to a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing component mounting density, and a method fabricating thereof.
  • 2. Description of the Related Art
  • In accordance with the recent development of the electronic industry, the demand for compact, multi-functional electronic components has rapidly increased.
  • In accordance with this trend, there has been a demand for a package substrate having a high density circuit pattern. Therefore, various methods of implementing a fine circuit pattern have been designed and used.
  • An embedded process, which is one method of implementing the fine circuit pattern, has a structure in which a circuit is impregnated with an insulating material, and may improve the flatness and strength of a product and have less circuit damage, whereby the method is appropriate for implementing the fine circuit pattern.
  • In the case of the embedding process according to the related art, a substrate has been configured by mounting or stacking packages or devices directly on the substrate. In this case, when the packages are mounted on double sides or a single side of the substrate, the entire package area may be reduced.
  • Accordingly, various researches into an embedded process or structure for an active device and an LRC device have been conducted.
  • However, in the case in which the substrate having the electronic device embedded therein is fabricated according to the related art, there is a risk that the electronic device may be damaged due to use of adhesive tape, or the like, and a fabricating process of the substrate is significantly complicated.
    • SUMMARY OF THE INVENTION
  • An aspect of the present invention provides a package substrate capable of corresponding to a fine pitch, while securing an interval between packages required when electronic devices are stacked on a bottom package, by forming metal bumps on an upper surface of the bottom package and bonding each of solder balls coupled to a lower surface of a top package and solder balls coupled to an lower surface of the electronic devices to the metal bumps, and a method fabricating thereof.
  • According to an aspect of the present invention, there is provided a package substrate, including: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filling the through-hole; and one or more electronic device connected to the via.
  • The via may be connected to the electronic device or an external device through solder bumps.
  • The chip may be a multilayer ceramic capacitor (MLCC).
  • The electronic device may be at least one selected from a resistor and an inductor.
  • The wafer may be made of silicon.
  • The package substrate may further include an insulating layer formed to cover the chip and the electronic device and exposing a portion of the first and second wiring layers.
  • According to another aspect of the present invention, there is provided a method of fabricating a package substrate, including: forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region; forming a through-hole penetrating through the wafer and a via filling the through-hole; forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity; and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.
  • The method may further include a polishing at least one of the upper surface and a lower surface of the wafer before the forming of the cavity.
  • The forming of the cavity may include: forming a first insulating film on the upper surface of the wafer; forming a first insulating pattern for forming the cavity by etching the first insulating film; and forming the cavity by etching the wafer using the first insulating pattern.
  • The forming of the cavity by etching the wafer may include wet etching of the wafer using a potassium hydroxide (KOH) solution.
  • The forming of the through-hole may include: forming a first photosensitive resin layer on the upper surface or a lower surface of the wafer; forming a first photosensitive pattern by exposing and developing the first photosensitive resin layer; and forming the through-hole by etching the wafer using the first photosensitive pattern.
  • The forming of the via may include: forming a second insulating film on a surface of the wafer including the through-hole and the cavity; forming a plating seed layer on the second insulating film; and filling the through-hole with a conductive material using an electroplating method.
  • The forming of the first wiring layer and the second wiring layer may include: forming a second photosensitive pattern on a region in the wafer, in which the first wiring layer and the second wiring layer are not formed; forming a wiring material on the upper surface of the wafer; removing the second photosensitive pattern and the wiring material formed on the second photosensitive pattern using a lift-off method.
  • The method may further include bonding the chip to each of the first wiring layer and the second wiring layer by allowing the wafer to reflow, after the mounting of the chip in the cavity.
  • The chip may be a multilayer ceramic capacitor (MLCC).
  • The electronic device may be at least one selected from a resistor and an inductor.
  • The method may further include forming an insulating layer exposing a portion of the first and second wiring layers and covering the chip and the electronic device.
  • The method may further include connecting the via to the electronic device or an external device through solder bumps.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1 is a top plan view schematically showing a package substrate according to an exemplary embodiment of the present invention;
  • FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1; and
  • FIGS. 3A through 3K are cross-sectional views schematically showing a method of fabricating a package substrate according to an exemplary embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
  • The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the shapes and dimensions may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like components.
  • Hereinafter, a package substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.
  • FIG. 1 is a top plan view schematically showing a package substrate 1 according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II′ of FIG. 1.
  • A package substrate according to an exemplary embodiment of the present invention is configured to include a wafer 10 having a cavity C formed in an upper surface thereof, the cavity including a chip mounting region T, a first wiring layer 13 a and a second wiring layer 13 b formed to be spaced apart from the first wiring layer 13 a, which are formed to be extended in the cavity C, a chip M positioned in the chip mounting region T to be connected to the first wiring layer 13 a and the second wiring layer 13 b, a through-hole H penetrating through the wafer 10, a via V filled in the through-hole H, and one or more electronic devices R and L connected to the via V.
  • Herein, the package substrate 1 may further include an insulating layer 14 covering the chip M and the electronic devices R and L and exposing a portion of the first wiring layer 13 a and the second wiring layer 13 b.
  • Herein, the wafer 10 may be made of silicon, and the via V may be connected to the electronic devices R and L or an external device 16 through solder bumps 15.
  • In addition, the chip M may be a multilayer ceramic capacitor (MLCC), and the electronic devices R and L may be at least one selected from a resistor and an inductor. However, the chip M and the electronic devices R and L are not limited thereto.
  • Hereinafter, a method of fabricating a package substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A through 3K.
  • FIGS. 3A through 3K are cross-sectional views schematically showing a method of fabricating a package substrate according to an exemplary embodiment of the present invention.
  • A method of fabricating a package substrate 1 according to an exemplary embodiment of the present invention includes forming a cavity in at least one region of an upper surface of a wafer 10, the cavity including a chip mounting region T, forming a through-hole H penetrating through the wafer 10 and a via V filled in the through-hole H, forming a first wiring layer 13 a and a second wiring layer 13 b spaced apart from the first wiring layer 13 a, which are extended in the cavity C, and a mounting a chip M in the cavity C to be connected to the first wiring layer 13 a and the second wiring layer 13 b.
  • As shown in FIG. 3A, a first insulating film (not shown) is formed on the upper surface of the wafer 10 and is then etched to form a first insulating pattern 11 a for forming the cavity C. Herein, the first insulating film may be made of silicon nitride (Si3N4); however, a material of forming the first insulating film is not limited thereto. In addition, as an etching method of the first insulating film, a reactive ion etching (RIE) method may be used; however, an etching method thereof is not limited thereto.
  • Then, as shown in FIG. 3B, the cavity C is formed in the upper surface of the waver 10 by using the first insulating pattern 11 a as a mask. Herein, the wafer 10 may be subject to wet etching using a potassium hydroxide (KOH) solution by using the first insulating pattern 11 a as the mask; however, solution used in the wet etching is not limited thereto.
  • Thereafter, as shown in FIG. 3C, a first photosensitive resin layer (not shown) is formed on a lower surface of the wafer and is then exposed and developed to form a first photosensitive pattern 11 b.
  • Next, as shown in FIG. 3D, the wafer 10 is etched using the first photosensitive pattern as a mask to form the through-hole H. Herein, as an etching method of the wafer 10, a RIE method may be used; however, an etching method thereof is not limited thereto.
  • Thereafter, as shown in FIG. 3E, a second insulating film 12 a is formed on a surface of the wafer 10 including the through-hole H and the cavity C, and a plating seed layer (not shown) is formed on the second insulating film 12 a. Herein, the second insulating film 12 a may be made of silicon oxide (SiO2); however, a material of the second insulating film 12 a is not limited thereto.
  • Then, as shown in FIG. 3F, the via V is formed by filling the through-hole H with a conductive material using an electroplating method.
  • Next, as shown in FIG. 3G, a second photosensitive pattern 12 b is formed on a region in the wafer 10, in which the first wiring layer 13 a and the second wiring layer 13 b are not formed. Then, as shown in FIG. 3H, a wiring material 13 is formed on the upper surface of the wafer 10.
  • Then, as shown in FIG. 3I, the second photosensitive pattern 12 b and the wiring material 13 formed on the second photosensitive pattern 12 b are simultaneously removed by a liftoff method. When the wafer 10 is immersed into an organic solvent and then slightly shaken, the second photosensitive pattern 12 b is dissolved, and/or the organic solvent is penetrated into an interface between the wafer 10 and the second photosensitive pattern 12 b, whereby the second photosensitive pattern 12 b and the wiring material 13 formed on the second photosensitive pattern 12 b may be simultaneously removed. Accordingly, the first wiring layer 13 a and the second wiring layer 13 b may be formed in portions in which they are intended to be formed.
  • Thereafter, as shown in FIG. 3J, the chip M is mounted in the cavity C, and the wafer 10 then reflows to individually bond the chip M to the first wiring layer 13 a and the chip M to the second wiring layer 13 b. Herein, the chip M may be the multilayer ceramic capacitor (MLCC).
  • Next, as shown in FIG. 3K, after the electronic devices R and L are mounted, and the insulating layer 14 exposing a portion of the first wiring layer 13 a and the second wiring layer 13 b and covering the chip M and the electronic devices R and L is formed. In addition, the via V is connected to the electronic devices R and L or the external device 16 through the solder bumps 15 to complete the package substrate as shown in FIGS. 1 and 2.
  • As set forth above, according to an exemplary embodiment of the present invention, package substrate capable of having the passive device having a predetermined capacity embedded therein, while reducing the pattern size and increasing the component mounting density, and a method fabricating thereof may be provided.
  • While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, various substitution, modifications and alteration may be made within the scope of the present invention may be made by those skilled in the art without departing from the spirit of the prevent invention defined by the accompanying claims.

Claims (18)

1. A package substrate, comprising:
a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region;
a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity;
a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer;
a through-hole penetrating through the wafer and a via filling the through-hole; and
one or more electronic device connected to the via.
2. The package substrate of claim 1, wherein the via is connected to the electronic device or an external device through solder bumps.
3. The package substrate of claim 1, wherein the chip is a multilayer ceramic capacitor (MLCC).
4. The package substrate of claim 1, wherein the electronic device is at least one selected from a resistor and an inductor.
5. The package substrate of claim 1, wherein the wafer is made of silicon.
6. The package substrate of claim 1, further comprising an insulating layer formed to cover the chip and the electronic device and exposing a portion of the first and second wiring layers.
7. A method of fabricating a package substrate, comprising:
forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region;
forming a through-hole penetrating through the wafer and a via filling the through-hole;
forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity; and
mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer.
8. The method of claim 7, further comprising a polishing at least one of the upper surface and a lower surface of the wafer before the forming of the cavity.
9. The method of claim 7, wherein the forming of the cavity includes:
forming a first insulating film on the upper surface of the wafer;
forming a first insulating pattern for forming the cavity by etching the first insulating film; and
forming the cavity by etching the wafer using the first insulating pattern.
10. The method of claim 9, wherein the forming of the cavity by etching the wafer includes wet etching of the wafer using a potassium hydroxide (KOH) solution.
11. The method of claim 7, wherein the forming of the through-hole includes:
forming a first photosensitive resin layer on the upper surface or a lower surface of the wafer;
forming a first photosensitive pattern by exposing and developing the first photosensitive resin layer; and
forming the through-hole by etching the wafer using the first photosensitive pattern.
12. The method of claim 7, wherein the forming of the via includes:
forming a second insulating film on a surface of the wafer including the through-hole and the cavity;
forming a plating seed layer on the second insulating film; and
filling the through-hole with a conductive material using an electroplating method.
13. The method of claim 7, wherein the forming of the first wiring layer and the second wiring layer includes:
forming a second photosensitive pattern on a region in the wafer, in which the first wiring layer and the second wiring layer are not formed;
forming a wiring material on the upper surface of the wafer;
removing the second photosensitive pattern and the wiring material formed on the second photosensitive pattern using a lift-off method.
14. The method of claim 7, further comprising bonding the chip to each of the first wiring layer and the second wiring layer by allowing the wafer to reflow, after the mounting of the chip in the cavity.
15. The method of claim 7, wherein the chip is a multilayer ceramic capacitor (MLCC).
16. The method of claim 7, wherein the electronic device is at least one selected from a resistor and an inductor.
17. The method of claim 7, further comprising forming an insulating layer exposing a portion of the first and second wiring layers and covering the chip and the electronic device.
18. The method of claim 7, further comprising connecting the via to the electronic device or an external device through solder bumps.
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CN102214628A (en) 2011-10-12
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US20140051212A1 (en) 2014-02-20
CN102214628B (en) 2014-04-09
US8951835B2 (en) 2015-02-10

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