The extensible bootloader for embedded system with application engine, write once, run everywhere.

ARM Linux 的学习历程。包括应用、驱动、设备树，GCC, Make, CMake, Bash, Vim, Git 等等大集合内容。文章遵守 CC BY NC SA 4.0 协议。

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

HF-RISC SoC

Hisilicon Kernel v4.4.35 for SoC Hi3798Cv200 / Hi3798Mv200. (Check Wiki Page for More Info)

L1 R2: WCH Cortex-M0 ETH/BLE SoC（CH579/CH578/CH577)

L4：Cortex A5 GSM SoC RDA8810

OpenWrt with support for the Xiaomi Mi WiFi Router 3 a/k/a MIR3. Based on current stable release v18.06.2 with Linux Kernel 4.14.95.

L1 R1: Telink 48MHz BLE SoC (TLSR8258/TLSR8253/TLSR8251)

L1 R1：WCH RISC-V4A BLE SoC (CH583/CH582/CH581)

L2 R2：phyplus 96MHz Cortex-M0 BLE SoC (PHY6222/PHY6252)

Very simple Cortex-M1 SoC design based on ARM DesignStart

Firmware examples for the RTL8762C BLE SoC

L2 R2: WCH RISC-V BLE SoC (CH573/CH571)

A custom C API for instrumenting Jetson TX1’s SoM and SoC

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

A parser to make binary tables used by HiSilicon SoC bootloader(u-boot) early low level function init_registers() human readable

L2 R2：WCH 144MHz RISC-V4C BLE SoC(CH32V208)

BMS - Control the charger and fuel gauge using STM32L4