Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures
Totally Self-Checking (TSC) design for widely used hash function: SHA-1Totally Self-Checking (TSC) design for widely used hash function: SHA-256Appropriate for use in security-critical applicationsEfficient hardware implementations Many cryptographic ...
A practical automated timing and physical design implementation methodology for the synchronous asynchronous interface and multi-voltage domain in high-speed synthesis
In a high-speed synthesis design environment, designers struggle to ensure that multi-clock and multi-power interfaces are designed, placed, connected and timed correctly. Identifying and applying proper timing constraints such as "no cycle stealing" at ...
Co-Processor for evolutionary full decision tree induction
In this paper a co-processor for the hardware aided decision tree induction using evolutionary approach (EFTIP) is proposed. EFTIP is used for hardware acceleration of the fitness evaluation task since this task is proven in the paper to be the ...
Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors
Simultaneous Multi-Threading (SMT) processors increase performance by allowing concurrent execution of multiple independent threads with sharing of key datapath components and better utilization of the resources. An SMT processor usually maintains a ...
On designing endurance aware erasure code for SSD-based storage systems
DPD-factor and GDP-pattern are proposed for comparing the endurance of erasure codes.EA-EO is designed as a modification of EVENODD with smaller DPD-factor.A code with smaller DPD-factor can provide higher endurance for systems.A code with sequential ...
Implementation of an improved chaotic encryption algorithm for real-time embedded systems by using a 32-bit microcontroller
Chaotic encryption algorithm is implemented in 32 bit microcontroller to protect text.Security analysis shows the effectiveness of the encryption for real-time applications.Performance and resources analysis justify the implementation of the system.The ...
An area efficient multi-mode quadruple precision floating point adder
Most of the scientific and engineering applications require accurate computations. Double precision floating point computations are not enough for many applications like climate modelling, computational physics, etc. Efficient design of quadruple ...
A new countermeasure against side-channel attacks based on hardware-software co-design
This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a ...
ABaT-FS
Traditional memory design aims to improve bandwidth and reduce power by trading off memory width and frequency scaling (FS). In this context, we propose A B a T - F S , a hardware scheduling mechanism that, for the first time, performs FS on ranks in ...
A new zero value attack combined fault sensitivity analysis on masked AES
Recently, a new kind of fault-based attacks called fault sensitivity analysis (FSA) has been proposed, which has significant advantage over the traditional Differential Fault Attacks (DFA). However, the masking countermeasure could resist original FSA ...