A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications
Energy-efficient design is the prime requirement for modern portable devices as these devices employ compute intensive image/video processing cores which produces output for human consumption. The limited perception of human sense can be exploited to ...
Parallelization of scalable elliptic curve cryptosystem processors in GF(2m)
The parallelization of scalable elliptic curve cryptography (ECC) processors (ECPs) is investigated in this paper. The proposed scalable ECPs support all 5 pseudo-random curves or all 5 Koblitz curves recommended by the National Institute of Standards ...
Quantum circuit physical design flow for the multiplexed trap architecture
Physical design is the second process in the design flow of quantum circuits that receives a netlist as input and generates a layout at a target technology. Quantum physical design problem is intractable. This process tackles the operation scheduling, ...
A novel pseudo random number generator based cryptographic architecture using quantum-dot cellular automata
Pseudo random number generator (PRNG) based hardware cryptographic architecture is presented in quantum-dot cellular automata (QCA) technology. Major achievement is the production of cipher texts using random number generator instead of fixed keys. The ...
QTL
QTL is a new variant of generalized Feistel network structure algorithm.QTL has the same program for encryption and decryption processes.QTL achieves high security and compact implementation in hardware. We propose a new ultra-lightweight block cipher, ...
Study on PUF based secure protection for IC design
The rapid progress in integrated circuit (IC) technology makes the gates in a single chip increase by Moore's law. The complexity in design and verification grows accordingly. To address this issue, intellectual property (IP) reuse is prevalently used ...
Analyzing fault behavior of shared data in parallel applications
Multicore architectures are becoming the most promising computing platforms thanks to their high performance. The soft error rate in multicore systems increases by the trend in the transistor sizes and the reduction of the voltage of the transistors. ...
Improving the Area Efficiency of ACO-Based Routing by Directional Pheromone in Large-Scale NoCs
The concept of Directional Pheromone (DP) is proposed.There are two techniques used in the DP routing algorithm for improving performance.Detailed hardware architecture of ACO-DP routing is presented. Ant Colony Optimization (ACO) is a distributed ...
DRTL
Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer's peak temperature and traffic to prolong chip's service life. In this paper, we propose a ...
Efficient VLSI design of adaptive rood pattern search algorithm for motion estimation of high definition videos
Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (ARPS) is one of the most popular fast ...
Design and implementation of instruction indirection for embedded software obfuscation
Tamper-aware use of the Instruction Register File (IRF) is presented.Two heuristic algorithms are presented to find sub-optimal IRF assignments against tampering.For a small IRF, our precision-oriented algorithm obtained the optimal assignments in most ...
GCM implementations of Camellia-128 and SMS4 by optimizing the polynomial multiplier
In some scenarios, the cryptographic primitives should support more than one functionality. Authenticated Encryption/Verified Decryption (AEVD) combines encryption and authentication at the same time, which is useful in communication protocols (DNS, ...
Configurable network-on-chip router macrocells
This paper presents a configurable architecture for Network-on-Chip (NoC) router macrocells, and a methodology to streamline their design and configuration. The methodology addresses the typical problems experienced by design and verification engineers ...
A low-cost, fault-tolerant and high-performance router architecture for on-chip networks
The router as the main component of on-chip networks has a key role in making connections between the processing cores. Thus, regarding the unreliable silicon, preserving the routers in operational states has a great effect on the network performance. ...
Low power fixed priority scheduling sporadic task with shared resources in hard real time systems
We consider a scheduling problem of the sporadic task that shares resources.We present a new scheduling policy based on a fixed-priority scheduling.The energy management problem is considered in a real time system.Two techniques are presented to solve a ...
A comparison of heuristic algorithms for custom instruction selection
Extensible processors with custom function units (CFU) that implement parts of the application code can make good trade-off between performance and flexibility. In general, deciding profitable parts of the application source code that run on CFU ...
Implementation of harmony search on embedded platform
Harmony Search (HS) is relatively a new population-based meta-heuristic optimization algorithm that imitates the music improvisation process of musicians to search for a perfect state of harmony. HS has attracted a lot of attention by showing excellent ...
A runtime fault-tolerant routing algorithm based on region flooding in NoCs
Aiming towards permanent link failure on NoCs, we propose an integrated software-hardware framework to provide reliability. A MPI-like fault-tolerant communication is introduced to detect link failure at runtime and automatically start healthy path ...
Reliability-oriented scheduling for static-priority real-time tasks in standby-sparing systems
The advent of complicated embedded systems with regard to relentless technology scaling and integration of more components into a single chip, have caused these systems to be less reliable. Moreover, these advancements have accompanied with a drastic ...
A compact digital gamma-tone filter processor
- Areli Rojo-Hernandez,
- Giovanny Sanchez-Rivera,
- Gerardo Avalos-Ochoa,
- Hector Perez-Meana,
- Leslie S. Smith
Area consumption is one of the most important design constrains in the development of compact digital systems. Several authors have proposed making compact Cochlear Implant processors using Gamma-tone filter banks. These model aspects of the cochlea ...