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Microprocessors & Microsystems

Volume 107, Issue C

Jun 2024

Elsevier Science Publishers B. V.
PO Box 211 1000 AE Amsterdam
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Volume 107, Issue C Jun 2024
ISSN:0141-9331
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editorial
Editorial Board
June 2024https://doi.org/10.1016/S0141-9331(24)00063-2
research-article
Low latency FPGA implementation of NTT for Kyber
- Mohamed Saoudi
  Department of Electrical Engineering, Ecole Supérieure Ali Chabati (ESAC), Algiers, Algeria
  ,
- Akram Kermiche
  Department of Electrical Engineering, Ecole Supérieure Ali Chabati (ESAC), Algiers, Algeria
  ,
- Omar Hocine Benhaddad
  Department of Electrical Engineering, Ecole Supérieure Ali Chabati (ESAC), Algiers, Algeria
  ,
- Nadir Guetmi
  Department of Electrical Engineering, Ecole Supérieure Ali Chabati (ESAC), Algiers, Algeria
  ,
- Boufeldja Allailou
  Department of Electrical Engineering, Ecole Supérieure Ali Chabati (ESAC), Algiers, Algeria
June 2024https://doi.org/10.1016/j.micpro.2024.105059
research-article
ExTern: Boosting RISC-V core performance using ternary encoding
- Farhad EbrahimiAzandaryani
  Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Martensstr. 3, Erlangen, 91058, Germany
  ,
- Dietmar Fey
  Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Martensstr. 3, Erlangen, 91058, Germany
June 2024https://doi.org/10.1016/j.micpro.2024.105058
research-article
Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads
- Juan Encinas
  Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Calle José Gutiérrez Abascal 2, Madrid, 28006, Spain
  ,
- Alfonso Rodríguez
  Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Calle José Gutiérrez Abascal 2, Madrid, 28006, Spain
  ,
- Andrés Otero
  Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Calle José Gutiérrez Abascal 2, Madrid, 28006, Spain
  ,
- Eduardo de la Torre
  Centro de Electrónica Industrial, Universidad Politécnica de Madrid, Calle José Gutiérrez Abascal 2, Madrid, 28006, Spain
June 2024https://doi.org/10.1016/j.micpro.2024.105050
research-article
ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography
- Sudhanshu Janwadkar
  Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India
  ,
- Rasika Dhavse
  Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology, Surat, India
June 2024https://doi.org/10.1016/j.micpro.2024.105048

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Latest Issue

Editorial Board

Low latency FPGA implementation of NTT for Kyber

ExTern: Boosting RISC-V core performance using ternary encoding

Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography

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