research-article

ABaT-FS

Author:

Mario Donato MarinoAuthors Info & Claims

Microprocessors & Microsystems, Volume 45, Issue PB

Pages 339 - 354

https://doi.org/10.1016/j.micpro.2016.06.013

Published: 01 September 2016 Publication History

Abstract

Traditional memory design aims to improve bandwidth and reduce power by trading off memory width and frequency scaling (FS). In this context, we propose A B a T - F S, a hardware scheduling mechanism that, for the first time, performs FS on ranks in scalable memory systems which employ Double Data Rate (DDR) synchronous dynamic random access memories (SDRAM). A B a T - F S is able to utilize different rank frequencies via controlling FS intensity - defined as the ratio between the amount of time FS is applied and the total selected scheduled cycle. We propose a design space exploration of A B a T - F S with different FS intensities aiming to determine the behavior of system implications such as bandwidth, rank temperature, and power utilization. Our findings show that for 100% of FS intensity, bandwidth increases proportionally while rank temperature is increased of about +23.7°C%, and energy-per-bit magnitude is decreased in up to 67%.

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Cited By

Marino MWeng TLi K(2018)Exploiting dynamic transaction queue size in scalable memory systemsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.5555/3197793.319780922:6(2065-2077)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.5555/3197793.3197809
Marino MLi K(2017)System implications of LLC MSHRs in scalable memory systemsMicroprocessors & Microsystems10.1016/j.micpro.2016.12.00752:C(355-364)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2016.12.007

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cover image Microprocessors & Microsystems

Microprocessors & Microsystems Volume 45, Issue PB

September 2016

137 pages

ISSN:0141-9331

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Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 September 2016

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Cited By

Marino MWeng TLi K(2018)Exploiting dynamic transaction queue size in scalable memory systemsSoft Computing - A Fusion of Foundations, Methodologies and Applications10.5555/3197793.319780922:6(2065-2077)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.5555/3197793.3197809
Marino MLi K(2017)System implications of LLC MSHRs in scalable memory systemsMicroprocessors & Microsystems10.1016/j.micpro.2016.12.00752:C(355-364)Online publication date: 1-Jul-2017
https://dl.acm.org/doi/10.1016/j.micpro.2016.12.007

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