Memory binding for performance optimization of control-flow intensive behavioral descriptions
This paper presents a memory binding algorithm for behaviors, used in application-specific integrated circuits (ASICs), that are characterized by the presence of conditionals and deeply nested loops that access memory extensively through arrays. Unlike ...
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed
This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related ...
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about performance estimation of bus-based communication architectures assuming that task partitioning and scheduling on processing elements are already determined. Since communication overhead is dynamic and unpredictable ...
Physical resource binding for a Coarse-Grain reconfigurable array using evolutionary algorithms
One of the challenges of designing for coarse-grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work ...
Combined circuit and architectural level variable supply-voltage scaling for low power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to reduce energy by lowering the operating voltage and the clock frequency ...
Dual-edge triggered storage elements and clocking strategy for low-power systems
This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock ...
Toward a multiple clock/voltage island design style for power-aware processors
Enabled by the continuous advancement in fabrication technology, present-day synchronous microprocessors include more than 100 million transistors and have clock speeds well in excess of the 1-GHz mark. Distributing a low-skew clock signal in this ...
Power complexity of multiplexer-based optoelectronic crossbar switches
The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no ...
Design and analysis of an ultrawide-band distributed CMOS mixer
This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-...
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control
This work presents a novel approach to optimize digital integrated circuits yield referring to speed, dynamic power and leakage power constraints. The method is based on process parameter estimation circuits and active control of body bias performed by ...