research-article

Dual-edge triggered storage elements and clocking strategy for low-power systems

Authors:

Nikola Nedovic,

Vojin G. OklobdzijaAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 5

Pages 577 - 590

https://doi.org/10.1109/TVLSI.2005.844302

Published: 01 May 2005 Publication History

Abstract

This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The presented analysis estimates the timing penalty and power savings of a system based on DETSE, and gives design guidelines for high-performance and low-power application. In addition, the paper presents a class of dual-edge triggered flip-flops with clock load, delay, and internal power consumption comparable to the fastest single-edge triggered storage elements (SETSE). Our simulated results show that by halving the clock frequency, dual-edge clocking strategy can save about 50% of the power consumed by the clock distribution network, and relax the design of clock distribution system, while paying virtually no penalty in throughput.

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Cited By

Bonetti APreyss NTeman ABurg A(2017)Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer NodesACM Transactions on Design Automation of Electronic Systems10.1145/305474422:4(1-20)Online publication date: 20-May-2017
https://dl.acm.org/doi/10.1145/3054744
Alioto MConsoli EPalumbo G(2011)Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204137719:5(737-750)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2041377
Alioto MConsoli EPalumbo G(2011)Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204137619:5(725-736)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2041376
Show More Cited By

Index Terms

Dual-edge triggered storage elements and clocking strategy for low-power systems
1. Hardware
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 13, Issue 5

May 2005

126 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 2005.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 May 2005

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Cited By

Bonetti APreyss NTeman ABurg A(2017)Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer NodesACM Transactions on Design Automation of Electronic Systems10.1145/305474422:4(1-20)Online publication date: 20-May-2017
https://dl.acm.org/doi/10.1145/3054744
Alioto MConsoli EPalumbo G(2011)Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204137719:5(737-750)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2041377
Alioto MConsoli EPalumbo G(2011)Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204137619:5(725-736)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2041376
Alioto MConsoli EPalumbo G(2010)Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuitsProceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation10.5555/1950238.1950247(62-72)Online publication date: 7-Sep-2010
https://dl.acm.org/doi/10.5555/1950238.1950247
Alioto MConsoli EPalumbo G(2010)General strategies to design nanometer flip-flops in the energy-delay spaceIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203353857:7(1583-1596)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TCSI.2009.2033538
Alioto MConsoli EPalumbo G(2010)Flip-flop energy/performance versus clock slope and impact on the clock network designIEEE Transactions on Circuits and Systems Part I: Regular Papers10.1109/TCSI.2009.203011357:6(1273-1286)Online publication date: 1-Jun-2010
https://dl.acm.org/doi/10.1109/TCSI.2009.2030113
Chiou LLuo S(2009)Energy-efficient dual-edge-triggered level converting flip flops with symmetry in setup times and insensitivity to output parasiticsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200795917:11(1659-1663)Online publication date: 1-Nov-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2007959
Karimiyan HSayedi SSaidi H(2009)Low-power dual-edge triggered state retention scan flip-flopProceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-11802-9_20(156-164)Online publication date: 9-Sep-2009
https://dl.acm.org/doi/10.1007/978-3-642-11802-9_20
Zhao PMcNeely JGolconda PBayoumi MBarcenas RKuang W(2007)Low-power clock branch sharing double-edge triggered flip-flopIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89362315:3(338-345)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.893623
Bui HSavaria YQu GIsmail YNarayanan VZhou H(2006)High speed differential pulse-width control loop based on frequency-to-voltage convertersProceedings of the 16th ACM Great Lakes symposium on VLSI10.1145/1127908.1127923(53-56)Online publication date: 30-Apr-2006
https://dl.acm.org/doi/10.1145/1127908.1127923

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