research-article

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

Authors:

Nattawut Thepayasuwan,

Alex DoboliAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 13, Issue 5

Pages 525 - 538

https://doi.org/10.1109/TVLSI.2004.842910

Published: 01 May 2005 Publication History

Abstract

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.

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Cited By

Subramanian VGilberti MDoboli APescaru D(2013)A goal-oriented programming framework for grid sensor networks with reconfigurable embedded nodesACM Transactions on Embedded Computing Systems10.1145/2362336.236234611:4(1-30)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1145/2362336.2362346
Lee CKim SHa S(2010)A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow SpecificationJournal of Signal Processing Systems10.1007/s11265-009-0351-658:2(193-213)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1007/s11265-009-0351-6
Subramanian VGilberti MDoboli ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Online adaptation policy design for grid sensor networks with reconfigurable embedded nodesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874929(1273-1278)Online publication date: 20-Apr-2009
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Index Terms

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

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cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 13, Issue 5

May 2005

126 pages

ISSN:1063-8210

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Copyright © 2005.

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IEEE Educational Activities Department

United States

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Published: 01 May 2005

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Cited By

Subramanian VGilberti MDoboli APescaru D(2013)A goal-oriented programming framework for grid sensor networks with reconfigurable embedded nodesACM Transactions on Embedded Computing Systems10.1145/2362336.236234611:4(1-30)Online publication date: 1-Jan-2013
Lee CKim SHa S(2010)A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow SpecificationJournal of Signal Processing Systems10.1007/s11265-009-0351-658:2(193-213)Online publication date: 1-Feb-2010
Subramanian VGilberti MDoboli ABenini LDe Micheli GAl-Hashimi BMueller W(2009)Online adaptation policy design for grid sensor networks with reconfigurable embedded nodesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874929(1273-1278)Online publication date: 20-Apr-2009
Pasricha SDutt N(2008)On-Chip Communication ArchitecturesundefinedOnline publication date: 29-Apr-2008
Meyer BThomas DHa SChoi KDutt NTeich J(2007)Simultaneous synthesis of buses, data mapping and memory allocation for MPSoCProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289822(3-8)Online publication date: 30-Sep-2007
Kallakuri SDoboli A(2007)Customization of arbitration policies and buffer space distribution using continuous-time Markov decision processesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89500315:2(240-245)Online publication date: 1-Feb-2007

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