Fast factorization architecture in soft-decision Reed-Solomon decoding
Reed-Solomon (RS) codes are among the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to its hard-decision counterpart, soft-decision decoding offers considerably higher error-correcting ...
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-...
VLSI Architectural design tradeoffs for sliding-window Log-MAP decoders
Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying ...
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
This paper demonstrates the design of efficient asynchronous bundled-data pipelines for the matrix-vector multiplication core of discrete cosine transforms (DCTs). The architecture is optimized for both zero and small-valued data, typical in DCT ...
Self-reset logic for fast arithmetic applications
A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also ...
A digit-serial multiplier for finite field GF(2m)
In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2m) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and ...
A reconfigurable, power-efficient adaptive Viterbi decoder
Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for ...
Design of multigigabit multiplexer-loop-based decision feedback equalizers
This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ...
Memory sub-banking scheme for high throughput MAP-based SISO decoders
The sliding window (SW) approach has been proposed as an effective means of reducing the memory requirements as well as the decoding latency of the maximum a posteriori (MAP) based soft-input soft-output (SISO) decoder in a Turbo decoder. In this paper, ...
Instruction code mapping for performance increase and energy reduction in embedded computer systems
In this paper, we present a novel and fast constructive technique that relocates the instruction code in such a manner into the main memory that the cache is utilized more efficiently. The technique is applied as a preprocessing step, i.e., before the ...
A novel wavelet transform-based transient current analysis for fault detection and localization
Transient current (IDD) testing has been often cited and investigated as an alternative and/or supplement to quiescent current (IDDQ) testing. In this correspondence, we present a novel integrated method for fault detection and localization using ...