Article

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation

Authors:

Swaroop Ghosh,

Swarup Bhunia,

Kaushik RoyAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 619 - 624

https://doi.org/10.1145/1233501.1233628

Published: 05 November 2006 Publication History

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Abstract

Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-V_th etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variationtolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.

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De VKahng AKarnik TLiu BMaleki MWang L(2015)Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignACM Journal on Emerging Technologies in Computing Systems10.1145/274634112:3(1-19)Online publication date: 21-Sep-2015
https://dl.acm.org/doi/10.1145/2746341
Dhoot CChau LChowdhury SMooney V(2014)Low Power Motion Estimation Based on Probabilistic ComputingIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2013.227362724:1(1-14)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1109/TCSVT.2013.2273627
Liu BWang LPortillo J(2013)Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2013.6674733(653-656)Online publication date: Aug-2013
https://doi.org/10.1109/MWSCAS.2013.6674733
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A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
1. Hardware

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Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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De VKahng AKarnik TLiu BMaleki MWang L(2015)Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI DesignACM Journal on Emerging Technologies in Computing Systems10.1145/274634112:3(1-19)Online publication date: 21-Sep-2015
https://dl.acm.org/doi/10.1145/2746341
Dhoot CChau LChowdhury SMooney V(2014)Low Power Motion Estimation Based on Probabilistic ComputingIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2013.227362724:1(1-14)Online publication date: 1-Jan-2014
https://dl.acm.org/doi/10.1109/TCSVT.2013.2273627
Liu BWang LPortillo J(2013)Variable latency VLSI design based on timing analysis, delay ATPG, and completion prediction2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2013.6674733(653-656)Online publication date: Aug-2013
https://doi.org/10.1109/MWSCAS.2013.6674733
Wan LChen DShanbhag NPoncino MChou PAmerasekera A(2012)CCPProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333695(135-140)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333695
Paul SMahmoodi HBhunia S(2010)Low-overhead F calibration at multiple operating points using delay-sensitivity-based path selectionACM Transactions on Design Automation of Electronic Systems10.1145/1698759.169876915:2(1-34)Online publication date: 2-Mar-2010
https://dl.acm.org/doi/10.1145/1698759.1698769
Ndai PRafique NThottethodi MGhosh SBhunia SRoy K(2010)TrifectaIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200749118:1(53-65)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2007491
Wan LChen DRoychowdhury J(2009)DynaTuneProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687430(172-179)Online publication date: 2-Nov-2009
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Stefano BBertozzi DBenini LMacii ESciuto D(2008)Process variation tolerant pipeline design through a placement-aware multiple voltage island design styleProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403610(967-972)Online publication date: 10-Mar-2008
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Nisar MChatterjee A(2008)Guided Probabilistic Checksums for Error Control in Low Power Digital-FiltersProceedings of the 2008 14th IEEE International On-Line Testing Symposium10.1109/IOLTS.2008.50(239-244)Online publication date: 7-Jul-2008
https://dl.acm.org/doi/10.1109/IOLTS.2008.50
Stefano BBertozzi DBenini LMacii E(2008)Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style2008 Design, Automation and Test in Europe10.1109/DATE.2008.4484806(967-972)Online publication date: Mar-2008
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