research-article

Design of robustly testable combinational logic circuits

Authors:

S. Kundu,

S. M. Reddy,

N. K. JhaAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 10, Issue 8

Pages 1036 - 1048

https://doi.org/10.1109/43.85740

Published: 01 November 2006 Publication History

Abstract

An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable

Cited By

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Pomeranz IReddy S(2019)Double-single stuck-at faultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201328128:3(426-432)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2009.2013281
Gharaybeh MAgrawal VBushnell MParodi C(2019)False-Path Removal Using Delay Fault SimulationJournal of Electronic Testing: Theory and Applications10.1023/A:100831663186816:5(463-476)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1008316631868
Ghosh SBhunia SRoy KHassoun S(2006)A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233628(619-624)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233628
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Index Terms

Design of robustly testable combinational logic circuits
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
2. Hardware

Index terms have been assigned to the content through auto-classification.

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 10, Issue 8

November 2006

124 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Pomeranz IReddy S(2019)Double-single stuck-at faultsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201328128:3(426-432)Online publication date: 3-Jan-2019
https://dl.acm.org/doi/10.1109/TCAD.2009.2013281
Gharaybeh MAgrawal VBushnell MParodi C(2019)False-Path Removal Using Delay Fault SimulationJournal of Electronic Testing: Theory and Applications10.1023/A:100831663186816:5(463-476)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1008316631868
Ghosh SBhunia SRoy KHassoun S(2006)A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolationProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233628(619-624)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233628
Wu WLee CWu MChen JAbadir M(2000)Oscillation Ring Delay Test for High Performance MicroprocessorsJournal of Electronic Testing: Theory and Applications10.1023/A:100836542831416:1-2(147-155)Online publication date: 1-Feb-2000
https://dl.acm.org/doi/10.1023/A%3A1008365428314
Pomeranz IReddy S(1999)On n-Detection Test Sets and Variable n-Detection Test Sets for Transition FaultsProceedings of the 1999 17TH IEEE VLSI Test Symposium10.5555/832299.836515Online publication date: 26-Apr-1999
https://dl.acm.org/doi/10.5555/832299.836515
Tekumalla RMenon P(1997)Delay Testing with Clock ControlProceedings of the 1997 IEEE International Test Conference10.5555/844384.845862Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.5555/844384.845862
Chen CGupta SPennino TYoffa E(1996)A satisfiability-based test generator for path delay faults in combinational circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240557(209-214)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240557
Ke WMenon P(1995)Synthesis of Delay-Verifiable Combinational CircuitsIEEE Transactions on Computers10.1109/12.36453344:2(213-222)Online publication date: 1-Feb-1995
https://dl.acm.org/doi/10.1109/12.364533

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Design of Parity Testable Combinational Circuits

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