research-article

A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification

Authors:

Shumaila Qamar,

Wasi Haider Butt,

Muhammad Waseem Anwar,

Muhammad Qasim KhanAuthors Info & Claims

ICSCA '20: Proceedings of the 2020 9th International Conference on Software and Computer Applications

Pages 339 - 343

https://doi.org/10.1145/3384544.3384547

Published: 17 April 2020 Publication History

Abstract

Universal Verification Methodology (UVM) is getting attention of researchers and functional verification community due to its advance flexibility, reusability and reliability features for design verification of multifaceted embedded systems. This is the reason that different tool vendors like Mentor Graphics support UVM-based simulation for design verification. Similarly, researchers frequently explore / utilize UVM to enhance the verification capabilities for embedded systems. In this context, there is a strong need to summarize the latest advancements, tools and techniques for UVM standard. Therefore, this article performs a Systematic Literature Review (SLR) to identify 27 studies (i.e. 2017-2019) pertaining to UVM standard. Subsequently, 21 UVM-based frameworks and 9 tools are identified. Moreover, key benefits of UVM standard are investigated. Finally, a comparative analysis of UVM with OVM (Open Verification Methodology) is performed. It is concluded that UVM provides advanced phasing mechanism, reporting, callbacks, objections, sequence libraries and control over simulation as compared to OVM. Researchers and practitioners of domain can highly benefit from findings of this article.

References

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Digital Library

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Cited By

de Oliveira JKreutz M(2024)The Blind Spots of Two-Factor Authentication ToolsProceedings of the Third International Conference on Innovations in Computing Research (ICR’24)10.1007/978-3-031-65522-7_50(580-592)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-3-031-65522-7_50
Bindu A(2022)A rigorous approach to microprocessor verification using UVMi-manager’s Journal on Electronics Engineering10.26634/jele.13.1.1934413:1(39)Online publication date: 2022
https://doi.org/10.26634/jele.13.1.19344

Index Terms

A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification
1. Hardware
  1. Electronic design automation
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation

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cover image ACM Other conferences

ICSCA '20: Proceedings of the 2020 9th International Conference on Software and Computer Applications

February 2020

382 pages

ISBN:9781450376655

DOI:10.1145/3384544

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 17 April 2020

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ICSCA 2020

ICSCA 2020: 2020 9th International Conference on Software and Computer Applications

February 18 - 21, 2020

Langkawi, Malaysia

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Cited By

de Oliveira JKreutz M(2024)The Blind Spots of Two-Factor Authentication ToolsProceedings of the Third International Conference on Innovations in Computing Research (ICR’24)10.1007/978-3-031-65522-7_50(580-592)Online publication date: 1-Aug-2024
https://doi.org/10.1007/978-3-031-65522-7_50
Bindu A(2022)A rigorous approach to microprocessor verification using UVMi-manager’s Journal on Electronics Engineering10.26634/jele.13.1.1934413:1(39)Online publication date: 2022
https://doi.org/10.26634/jele.13.1.19344

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