research-article

The system verification methodology for advanced TLM verification

Authors:

Marcio F.S. Oliveira,

Christoph Kuznik,

Wolfgang Mueller,

Rolf Drechsler,

Wolfgang Ecker,

Volkan EsenAuthors Info & Claims

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 313 - 322

https://doi.org/10.1145/2380445.2380497

Published: 07 October 2012 Publication History

Abstract

The IEEE-1800 SystemVerilog [20] system description and verification language integrates dedicated verification features, like constraint random stimulus generation and functional coverage, which are the building blocks of the Universal Verification Methodology (UVM)[3], the emerging standard for electronic systems verification. In this article, we introduce our System Verification Methodology (SVM) as a SystemC library for advanced Transaction Level Modeling (TLM) testbench implementation. As such, we first present SystemC libraries for the support of verification features like functional coverage and constrained random stimulus generation. Thereafter, we introduce the SVM with advanced TLM support based on SystemC and compare it to UVM and related approaches. Finally, we demonstrate the application of our SVM by means of a testbench for a two wheel self-balancing electric vehicle.

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Cited By

Pieper PDrechsler RPieper PDrechsler R(2024)Hardware and Environment ModelingFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_3(21-106)Online publication date: 26-Mar-2024
https://doi.org/10.1007/978-3-031-51692-4_3
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Register-Transfer-Ebene KorrespondenzanalyseVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_8(221-248)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_8
Ghaniyoun MBarber KZhang YTeodorescu RMartínez JDuato JJohn L(2021)IntroSpectreProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00073(874-887)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00073
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Index Terms

The system verification methodology for advanced TLM verification
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Published In

cover image ACM Conferences

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2012

596 pages

ISBN:9781450314268

DOI:10.1145/2380445

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Naehyuck Chang
Seoul National University, Korea
,
Franco Fummi
University of Verona, Italy

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 October 2012

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ESWEEK'12

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ESWEEK'12: Eighth Embedded System Week

October 7 - 12, 2012

Tampere, Finland

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CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;

Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Pieper PDrechsler RPieper PDrechsler R(2024)Hardware and Environment ModelingFormal and Practical Techniques for the Complex System Design Process using Virtual Prototypes10.1007/978-3-031-51692-4_3(21-106)Online publication date: 26-Mar-2024
https://doi.org/10.1007/978-3-031-51692-4_3
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Register-Transfer-Ebene KorrespondenzanalyseVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_8(221-248)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_8
Ghaniyoun MBarber KZhang YTeodorescu RMartínez JDuato JJohn L(2021)IntroSpectreProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00073(874-887)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00073
Kulkarni RKoppad D(2021)High Quality Design-Verification of APB based Switch Interface2021 Fourth International Conference on Microelectronics, Signals & Systems (ICMSS)10.1109/ICMSS53060.2021.9673640(1-6)Online publication date: 18-Nov-2021
https://doi.org/10.1109/ICMSS53060.2021.9673640
Hovey GDi Vruno F(2019)A Framework for RFI Simulation and Performance Verification2019 RFI Workshop - Coexisting with Radio Frequency Interference (RFI)10.23919/RFI48793.2019.9111822(1-6)Online publication date: Sep-2019
https://doi.org/10.23919/RFI48793.2019.9111822
Herdt VLe HGrose DDrechsler R(2018)Towards fully automated TLM-to-RTL property refinement2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342253(1508-1511)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342253
Salah KMostafa H(2018)Constructing Effective UVM Testbench for DRAM Memory Controllers2018 New Generation of CAS (NGCAS)10.1109/NGCAS.2018.8572135(178-181)Online publication date: Nov-2018
https://doi.org/10.1109/NGCAS.2018.8572135
Drechsler RGrose D(2017)Verifying next generation electronic systems2017 International Conference on Infocom Technologies and Unmanned Systems (Trends and Future Directions) (ICTUS)10.1109/ICTUS.2017.8285965(6-10)Online publication date: Dec-2017
https://doi.org/10.1109/ICTUS.2017.8285965
Romenska YMaraninchi FFanucci LTeich J(2016)Efficient monitoring of loose-ordering properties for SystemC/TLMProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971938(559-562)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971938
Mohamed KMohamed K(2016)New Trends in SoC Verification: UVM, Bug Localization, Scan-C0068ain-Based Methodology, GA-Based Test GenerationIP Cores Design from Specifications to Production10.1007/978-3-319-22035-2_6(121-152)Online publication date: 2016
https://doi.org/10.1007/978-3-319-22035-2_6
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