The Design Of UVM Verification Platform Based On Data Comparison

This article is based on UVM (Universal Verification Methodology) to build a verification platform that can quickly verify the DUT (Design Under Test). The test platform skillfully uses the UVM components and flexible configuration scheme, which fully shows the strong advantages of the Universal Verification Methodology. The uniqueness of this verification platform is that it does not use UVM's reference model verification component. This verification platform is suitable for modules without algorithm models, such as high-speed interface to low-speed interface, Interrupt handling module, etc. A hierarchical register model is applied in the verification platform, which can configure registers quickly and flexibly. At the end of this article, the IP-level verification work of the Interrupt handling module and the coverage collection work are realized, which proves that the verification platform built in this article has higher flexibility and reusability. The verified Interrupt handling module is based on the AXI high-speed bus transmission protocol. The result of the verification is that the Interrupt handling module realizes the full and overflow of ring FIFO, and the bus meets the protocol requirements. At the same time, the coverage rate meets the verification requirements. Chip verification occupies an increasingly important position in the process of chip research and development, which is a key part of ensuring the smooth tapeout of chips.