Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis

Published: 08 November 2024 Publication History

Abstract

Due to the supply chain globalization of the semiconductor industry, securing heterogeneous System-on-Chip (SoC) is becoming necessary. A malicious alteration, inserting Hardware Trojan, infringement, or counterfeiting of design via Reverse Engineering (RE) is the primary reason. As RE allows attackers to uncover proprietary algorithms, design specifications, and other intellectual property, exploiting the design becomes easier. This has a havoc impact on the manufacturer’s revenue as well as erodes consumer trust in the authenticity of the devices. This enforces a robust framework from the topmost design abstraction level to protect against RE attacks. This article proposed a robust, architectural synthesis-driven dual-phase functional obfuscation framework for securing Register Transfer Level design. In this framework, obfuscation is achieved for both the datapath (DP) and control unit (CU) of design. Further, the robustness of obfuscated design is tested against sophisticated DP and CU level attacks. Moreover, to protect the design from brute force attack, a Consecutive Design Mis-Authentication Prevention Mechanism (CDMAP) is proposed. The proposed framework is validated using six standard Hardware Accelerator (HA) benchmarks and evaluated based on design overhead and robustness for different key sizes. A significant improvement is achieved in terms of security (∼1800 times) and (∼5.2 times) and strength of obfuscation (∼1.87 × 1056 times) and (∼5.94 × 1033 times) at a lower design cost of around (∼20.4%) and (∼10.4%) compared to two closely related approaches.

References

[1]
Mitali Sinha, Pramit Bhattacharyya, Sidhartha Sankar Rout, Neha Bhairavi Prakriya, and Sujay Deb. 2022. Securing an accelerator-rich system from flooding-based denial-of-service attacks. IEEE Transactions on Emerging Topics in Computing 10, 2 (2022), 855–869. DOI:
[2]
Christian Pilato, Siddharth Garg, Kaijie Wu, Ramesh Karri, and Francesco Regazzoni. 2017. Securing hardware accelerators: A new challenge for high-level synthesis. IEEE Embedded Systems Letters 10, 3 (2017), 77–80.
[3]
Dipanjan Roy and Anirban Sengupta. 2017. Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis. Future Generation Computer Systems 71 (2017), 89–101.
[4]
Encarnacin Castillo, Uwe Meyer-Baese, Antonio García, Luis Parrilla, and Antonio Lloris. 2007. IPP@ HDL: Efficient intellectual property protection scheme for IP cores. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, 5 (2007), 578–591.
[5]
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, and Gang Qu. 2016. Secure and low-overhead circuit obfuscation technique with multiplexers. In Proceedings of the 2016 International Great Lakes Symposium on VLSI. IEEE, 133–136.
[6]
Elias Kougianos Saraju P. Mohanty, and Nagarajan Ranganathan. 2008. Low-Power High-Level Synthesis for Nanoscale CMOS Circuits.
[7]
Michael Fingeroff. 2010. High-Level Synthesis Blue Book.
[8]
Dipanjan Roy and Anirban Sengupta. 2018. Obfuscated JPEG image decompression IP core for protecting against reverse engineering [hardware matter]. IEEE Consumer Electronics Magazine 7, 3 (2018), 104–109. DOI:
[9]
Alex Baumgarten, Akhilesh Tyagi, and Joseph Zambreno. 2010. Preventing IC piracy using reconfigurable logic barriers. IEEE Design & Test of Computers 27, 1 (2010), 66–75.
[10]
Travis Meade, Shaojie Zhang, and Yier Jin. 2016. Netlist reverse engineering for high-level functionality reconstruction. In Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference. IEEE, 655–660.
[11]
Jonathan Cruz, Pravin Gaikwad, and Swarup Bhunia. 2022. Analysis of hardware trojan resilience enabled through logic locking. In Proceedings of the 2022 Asian Hardware Oriented Security and Trust Symposium. 1–6. DOI:
[12]
Biresh Kumar Joardar, Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Hai Li, Partha Pratim Pande, and Krishnendu Chakrabarty. 2020. GRAMARCH: A GPU-ReRAM based heterogeneous architecture for neural image segmentation. In Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition. 228–233. DOI:
[13]
Mattia Tibaldi and Christian Pilato. 2023. A survey of FPGA optimization methods for data center energy efficiency. IEEE Transactions on Sustainable Computing 8, 3 (2023), 343–362. DOI:
[14]
Sheikh Ariful Islam and Srinivas Katkoori. 2018. High-level synthesis of key based obfuscated RTL datapaths. In Proceedings of the 2018 19th International Symposium on Quality Electronic Design. IEEE, 407–412.
[15]
Christian Pilato, Francesco Regazzoni, Ramesh Karri, and Siddharth Garg. 2018. TAO: Techniques for algorithm-level obfuscation during high-level synthesis. In Proceedings of the 55th Annual Design Automation Conference. 1–6.
[16]
Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, and Ramesh Karri. 2021. ASSURE: RTL locking against an untrusted foundry. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, 7 (2021), 1306–1318.
[17]
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, and Ramesh Karri. 2022. Optimizing the use of behavioral locking for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42, 2 (2022), 462–472.
[18]
Sakari Lahti, Panu Sjövall, Jarno Vanne, and Timo D. Hämäläinen. 2019. Are we there yet? A study on the state of high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 5 (2019), 898–911. DOI:
[19]
Wen Chen, Sandip Ray, Jayanta Bhadra, Magdy Abadir, and Li-C Wang. 2017. Challenges and trends in modern SoC design verification. IEEE Design & Test 34, 5 (2017), 7–22.
[20]
Christian Pilato, Donatella Sciuto, Benjamin Tan, Siddharth Garg, and Ramesh Karri. 2022. High-level design methods for hardware security: Is it the right choice? Invited. In Proceedings of the 59th ACM/IEEE Design Automation Conference. Association for Computing Machinery, New York, NY, USA, 1375–1378. DOI:
[21]
Aditya Anshul and Anirban Sengupta. 2023. A survey of high level synthesis based hardware security approaches for reusable IP cores [feature]. IEEE Circuits and Systems Magazine 23, 4 (2023), 44–62. DOI:
[22]
Yousra Alkabani and Farinaz Koushanfar. 2007. Active hardware metering for intellectual property protection and security. In Proceedings of the USENIX Security Symposium, Vol. 20. 1–20.
[23]
Farinaz Koushanfar and Gang Qu. 2001. Hardware metering. In Proceedings of the 38th Annual Design Automation Conference. 490–493.
[24]
Anirban Sengupta, Dipanjan Roy, and Saraju P. Mohanty. 2017. Triple-phase watermarking for reusable IP core protection during architecture synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 4 (2017), 742–755.
[25]
Farinaz Koushanfar, Inki Hong, and Miodrag Potkonjak. 2005. Behavioral synthesis techniques for intellectual property protection. ACM Transactions on Design Automation of Electronic Systems 10, 3 (2005), 523–545.
[26]
Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, and Swarup Bhunia. 2012. Hardware trojan detection by multiple-parameter side-channel analysis. IEEE Transactions on Computers 62, 11 (2012), 2183–2195.
[27]
Dakshi Agrawal, Selcuk Baktir, Deniz Karakoyunlu, Pankaj Rohatgi, and Berk Sunar. 2007. Trojan detection using IC fingerprinting. In Proceedings of the 2007 IEEE Symposium on Security and Privacy. IEEE, 296–310.
[28]
Kan Xiao, Domenic Forte, Yier Jin, Ramesh Karri, Swarup Bhunia, and Mohammad Tehranipoor. 2016. Hardware trojans: Lessons learned after one decade of research. ACM Transactions on Design Automation of Electronic Systems 22, 1 (2016), 1–23.
[29]
Masoud Rostami, Mehrdad Majzoobi, Farinaz Koushanfar, Dan S. Wallach, and Srinivas Devadas. 2014. Robust and reverse-engineering resilient PUF authentication and key-exchange by substring matching. IEEE Transactions on Emerging Topics in Computing 2, 1 (2014), 37–49. DOI:
[30]
G. Edward Suh and Srinivas Devadas. 2007. Physical unclonable functions for device authentication and secret key generation. In Proceedings of the 2007 44th ACM/IEEE Design Automation Conference. IEEE, 9–14.
[31]
Rajat Subhra Chakraborty and Swarup Bhunia. 2009. HARPOON: An obfuscation-based SoC design methodology for hardware protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 10 (2009), 1493–1502.
[32]
Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, and Ramesh Karri. 2012. Security analysis of logic obfuscation. In Proceedings of the 49th Annual Design Automation Conference. 83–89.
[33]
Muhammad Yasin, Jeyavijayan JV Rajendran, Ozgur Sinanoglu, and Ramesh Karri. 2016. On improving the security of logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, 9 (2016), 1411–1424. DOI:
[34]
Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, and Mark M. Tehranipoor. 2022. Advances in logic locking: Past, present, and prospects. IACR Cryptol. ePrint Arch. (2022), 260. Retrieved from https://eprint.iacr.org/2022/260
[35]
Yingjie Lao and Keshab K. Parhi. 2014. Obfuscating DSP circuits via high-level transformations. IEEE Transactions on Very Large Scale Integration Systems 23, 5 (2014), 819–830.
[36]
Anirban Sengupta, Deepak Kachave, and Dipanjan Roy. 2019. Low cost functional obfuscation of reusable IP cores used in CE hardware through robust locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 4 (2019), 604–616. DOI:
[37]
Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, and Ramesh Karri. 2020. Is register transfer level locking secure?. In Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition. 550–555. DOI:
[38]
Nimisha Limaye, Animesh B. Chowdhury, Christian Pilato, Mohammed T. M. Nabeel, Ozgur Sinanoglu, Siddharth Garg, and Ramesh Karri. 2021. Fortifying RTL locking against oracle-less (untrusted foundry) and oracle-guided attacks. In Proceedings of the 2021 58th ACM/IEEE Design Automation Conference. 91–96. DOI:
[39]
Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, and Ramesh Karri. 2023. Optimizing the use of behavioral locking for high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42, 2 (2023), 462–472. DOI:
[40]
Haimanti Chakraborty and Ranga Vemuri. 2024. RTL interconnect obfuscation by polymorphic switch boxes for secure hardware generation. In Proceedings of the 2024 25th International Symposium on Quality Electronic Design. 1–8. DOI:
[41]
Sheikh Ariful Islam, Love Kumar Sah, and Srinivas Katkoori. 2020. High-level synthesis of key-obfuscated RTL iP with design lockout and camouflaging. ACM Transactions on Design Automation of Electronic Systems 26, 1 (2020), 1–35.
[42]
Dipanjan Roy, Sabiya Jani Shaik, and Sonam Sharma. 2022. Securing hardware accelerator during high-level synthesis. In Proceedings of the 2022 IEEE International Symposium on Hardware Oriented Security and Trust. 177–180. DOI:
[43]
Pramod Subramanyan, Sayak Ray, and Sharad Malik. 2015. Evaluating the security of logic encryption algorithms. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust. 137–143. DOI:
[44]
Yang Xie and Ankur Srivastava. 2019. Anti-SAT: Mitigating SAT attack on logic locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, 2 (2019), 199–207. DOI:
[45]
Martin Finke. 2015. Equisatisfiable SAT encodings of arithmetical operations. Online Retrieved from http://www.martin-finke.de/documents/Masterarbeit_bitblast_Finke.pdf. (2015).
[46]
Supratik Chakraborty, Ashutosh Gupta, and Rahul Jain. 2017. Matching multiplications in bit-vector formulas. In Proceedings of the Verification, Model Checking, and Abstract Interpretation: 18th International Conference, VMCAI 2017, Paris, France, January 15–17, 2017, Proceedings 18. Springer, 131–150.
[47]
Dipanjan Roy, Sabiya Jani Shaik, and Sonam Sharma. 2023. Securing hardware accelerator against reverse engineering attack. In Proceedings of the 2023 IEEE International Conference on Consumer Electronics. IEEE, 1–6.
[48]
Express Benchmarks. Retrieved July 20, 2023 from https://web.ece.ucsb.edu/EXPRESS/benchmark/
[49]
NanGate 15 nm Library. Retrieved July 20, 2023 from http://www.nangate.com/?pageid=2328/
[50]
Xilinx Vivado. Retrieved July 20, 2023 from https://www.xilinx.com/support/download.html
[51]
Sarah Amir, Bicky Shakya, Xiaolin Xu, Yier Jin, Swarup Bhunia, Mark Tehranipoor, and Domenic Forte. 2018. Development and evaluation of hardware obfuscation benchmarks. Journal of Hardware and Systems Security 2, 2 (2018), 142–161.

Index Terms

  1. PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis

      Recommendations

      Comments

      Please enable JavaScript to view thecomments powered by Disqus.

      Information & Contributors

      Information

      Published In

      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 30, Issue 1
      January 2025
      198 pages
      EISSN:1557-7309
      DOI:10.1145/3697150
      Issue’s Table of Contents

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Journal Family

      Publication History

      Published: 08 November 2024
      Online AM: 17 October 2024
      Accepted: 01 October 2024
      Revised: 17 September 2024
      Received: 09 January 2024
      Published in TODAES Volume 30, Issue 1

      Check for updates

      Author Tags

      1. Architectural synthesis
      2. reverse engineering
      3. hardware security
      4. hardware obfuscation
      5. hardware accelerator

      Qualifiers

      • Research-article

      Funding Sources

      • SERB, Government of India
      • Ministry of Education, Government of India, through the Prime Minister Research Fellowship

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 81
        Total Downloads
      • Downloads (Last 12 months)81
      • Downloads (Last 6 weeks)77
      Reflects downloads up to 30 Nov 2024

      Other Metrics

      Citations

      View Options

      Login options

      Full Access

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Full Text

      View this article in Full Text.

      Full Text

      Media

      Figures

      Other

      Tables

      Share

      Share

      Share this Publication link

      Share on social media