ACM Transactions on Design Automation of Electronic Systems

Cyber-physical systems (CPSs) need to respond to each change of each monitored object in time. The entire response process can be divided into two stages: the update stage and the control stage. Tasks in CPSs can thus be divided into two kinds: update ...

Wearable devices that have low-power sensors, processors, and communication capabilities are gaining wide adoption in several health applications. The machine learning algorithms on these devices assume that data from all sensors are available during ...

Today’s performance analysis frameworks for deep learning accelerators suffer from two significant limitations. First, although modern convolutional neural networks (CNNs) consist of many types of layers other than convolution, especially during training, ...

To accelerate the back-end design flow of integrated circuit (IC), numerous studies have made exploratory advancements in machine learning (ML) for electronic design automation (EDA). However, most research works are limited to deep learning (DL) models ...

Bi-decomposition rewrites logic functions as the composition of simpler components. It is related to Boolean division, where a given function is rewritten as the product of a divisor and a quotient, but bi-decomposition can be defined for any Boolean ...

High reliability requirements in certain systems are combined with constraints on test overheads, including test data volume, test application time and design-for-testability (DFT) logic. The overheads can be reduced if they are shared among different ...

Due to the supply chain globalization of the semiconductor industry, securing heterogeneous System-on-Chip (SoC) is becoming necessary. A malicious alteration, inserting Hardware Trojan, infringement, or counterfeiting of design via Reverse Engineering (...

Network sparsification serves as an effective technique to accelerate Deep Neural Network (DNN) inference. However, existing sparsification techniques often rely on structured sparsity, which yields limited benefits. This is primarily due to the ...

Oftentimes fault candidates produced by logic diagnosis are too many to effectively guide the follow-on failure analysis. In this work, we propose a novel two-stage fast screening method to sift through a large of candidates in the fault callout outputted ...

Emerging resistive random-access memory (ReRAM) based processing-in-memory (PIM) accelerators have been increasingly explored in recent years because they can efficiently perform in-situ matrix-vector multiplication (MVM) operations involved in a wide ...

This paper presents the hardware realization of a real-time blood pressure (BP) prediction model for wearable devices, utilizing long short-term memory (LSTM) deep neural networks (DNNs). The proposed system uses both electrocardiogram (ECG) and ...

Logic synthesis tools are the core components of digital circuit design, which convert programs written in hardware description languages into gate-level netlists and optimize the netlists. However, the netlist optimization is complex, with numerous ...

As FPGAs are being deployed in the cloud infrastructure for acceleration, the technology of multi-tenant FPGA has emerged as a topic of interest. This development has drawn considerable attention to its security issues. While previous research primarily ...

Recent work has shown that graph neural networks (GNNs) can be used to recover high-level word operators and their boundaries in gate-level netlists. Unlike formal methods, however, the GNN does not prove functional equivalence. As such, there is a ...

Functional and timing validation of high performing safety-related platforms requires testing specific traffic patterns in the network-on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control on the ...