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High-speed concurrent fault simulation with vectors and scalars

Authors:

D. Lacy,

R. BeavenAuthors Info & Claims

DAC '80: Proceedings of the 17th Design Automation Conference

Pages 374 - 380

https://doi.org/10.1145/800139.804558

Published: 23 June 1980 Publication History

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Abstract

Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.

It should be observed that some of the above goals are in mutual conflict. For example, modeling ease and high execution speed are normally only achievable by a sacrifice in accuracy, and high accuracy is only possible by more elaborate modeling efforts or slower execution speeds, or both. As a consequence it becomes important to achieve a balance between these goals. The balance achieved here, in part dictated by the demands of fault simulation, emphasizes execution speed, adequate accuracy, and a simple modeling method.

A new logic and fault simulator, VOTE (Verification of Test Effectiveness) is described. The specifics to be described here fall into two categories: those which are of general interest, and those which are strictly implementation items.

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Cited By

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Rogers WGuzolek JAbraham J(2006)Concurrent Hierarchical Fault SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1987.12703286:5(848-862)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.1987.1270328
Ulrich EAgrawal VArabian JUlrich EAgrawal VArabian J(1994)Simulation on MultiprocessorsConcurrent and Comparative Discrete Event Simulation10.1007/978-1-4615-2738-1_12(151-177)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2738-1_12
Ulrich EAgrawal VArabian JUlrich EAgrawal VArabian J(1994)Introduction and OverviewConcurrent and Comparative Discrete Event Simulation10.1007/978-1-4615-2738-1_1(1-22)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2738-1_1
Show More Cited By

Index Terms

High-speed concurrent fault simulation with vectors and scalars
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware

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Published In

DAC '80: Proceedings of the 17th Design Automation Conference

June 1980

642 pages

ISBN:0897910206

DOI:10.1145/800139

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 1980

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Cited By

View all

Rogers WGuzolek JAbraham J(2006)Concurrent Hierarchical Fault SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.1987.12703286:5(848-862)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.1987.1270328
Ulrich EAgrawal VArabian JUlrich EAgrawal VArabian J(1994)Simulation on MultiprocessorsConcurrent and Comparative Discrete Event Simulation10.1007/978-1-4615-2738-1_12(151-177)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2738-1_12
Ulrich EAgrawal VArabian JUlrich EAgrawal VArabian J(1994)Introduction and OverviewConcurrent and Comparative Discrete Event Simulation10.1007/978-1-4615-2738-1_1(1-22)Online publication date: 1994
https://doi.org/10.1007/978-1-4615-2738-1_1
Bose SAgrawal PSchweikert D(1992)Concurrent fault simulation of logic gates and memory blocks on message passing multicomputersProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.149479(332-335)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.149479
Bose SAgrawal P(1992)Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers[1992] Proceedings 29th ACM/IEEE Design Automation Conference10.1109/DAC.1992.227783(332-335)Online publication date: 1992
https://doi.org/10.1109/DAC.1992.227783
Ulrich ELentz KArabian JGustin MAgrawal VMontessoro P(1992)The comparative and concurrent simulation of discrete-event experimentsJournal of Electronic Testing: Theory and Applications10.1007/BF001372483:2(107-118)Online publication date: 1-May-1992
https://dl.acm.org/doi/10.1007/BF00137248
Hill FAbuelyaman E(1990)Evaluation of a fan out stem based fault simulation in sequential circuitsMathematical and Computer Modelling: An International Journal10.5555/2259362.225964414(365-371)Online publication date: 1-Jan-1990
https://dl.acm.org/doi/10.5555/2259362.2259644
Ishiura NIto MYajima S(1990)Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.577859:8(868-875)Online publication date: Jan-1990
https://doi.org/10.1109/43.57785
Razdan RAnwaruddin MKovijanic PGanesh RShih H(1989)An interactive sequential test pattern generation systemProceedings. 'Meeting the Tests of Time'., International Test Conference10.1109/TEST.1989.82275(38-46)Online publication date: 1989
https://doi.org/10.1109/TEST.1989.82275
Heydemann MPlaignaud ADure DShaklee DNewton A(1988)The architecture of a highly integrated simulation systemProceedings of the 25th ACM/IEEE Design Automation Conference10.5555/285730.285833(617-621)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.5555/285730.285833
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