research-article

Software-directed combined cpu/link voltage scaling fornoc-based cmps

Authors:

Mahmut Kandemir,

Ozcan OzturkAuthors Info & Claims

SIGMETRICS '08: Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

Pages 359 - 370

https://doi.org/10.1145/1375457.1375498

Published: 02 June 2008 Publication History

Abstract

Network-on-Chip (NoC) based chip multiprocessors (CMPs) are expected to become more widespread in future, in both high performance scientific computing and low-end embedded computing. For many execution environments that employ these systems, reducing power consumption is an important goal. This paper presents a software approach for reducing power consumption in such systems through compiler-directed voltage/frequency scaling. The unique characteristic of this approach is that it scales the voltages and frequencies of select CPUs and communication links in a coordinated manner to maximize energy savings without degrading performance. Our approach has three important components. The first component is the identification of phases in the application. The next step is to determine the critical execution paths and slacks in each phase. For implementing these two components, our approach employs a novel parallel program representation. The last component of our approach is the assignment of voltages and frequencies to CPUs and communication links to maximize energy savings. We use integer linear programming (ILP) for this voltage/frequency assignment problem. To test our approach, we implemented it within a compilation framework and conducted experiments with applications from the SPEComp suite and SPECjbb. Our results show that the proposed combined CPU/link scaling is much more effective than scaling voltages of CPUs or communication links in isolation. In addition, we observed that the energy savings obtained are consistent across a wide range of values of our major simulation parameters such as the number of CPUs, the number of voltage/frequency levels, and the thread-to-CPU mapping.

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Cited By

Booth JKotra JZhao HKandemir MRaghavan P(2015)Phase Detection with Hidden Markov Models for DVFS on Many-Core Processors2015 IEEE 35th International Conference on Distributed Computing Systems10.1109/ICDCS.2015.27(185-195)Online publication date: Jun-2015
https://doi.org/10.1109/ICDCS.2015.27
Shin DKim WKwon SHan T(2011)Communication-aware VFI partitioning for GALS-based networks-on-chipDesign Automation for Embedded Systems10.1007/s10617-011-9070-x15:2(89-109)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1007/s10617-011-9070-x
Ozturk OKandemir MIrwin MNarayanan S(2010)Compiler directed network-on-chip reliability enhancement for chip multiprocessorsACM SIGPLAN Notices10.1145/1755951.175590245:4(85-94)Online publication date: 13-Apr-2010
https://dl.acm.org/doi/10.1145/1755951.1755902
Show More Cited By

Index Terms

Software-directed combined cpu/link voltage scaling fornoc-based cmps
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Memory management
        Garbage collection

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cover image ACM Conferences

SIGMETRICS '08: Proceedings of the 2008 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

June 2008

486 pages

ISBN:9781605580050

DOI:10.1145/1375457

General Chair:
Zhen Liu
IBM T. J. Watson Research Center, USA
,
Program Chairs:
Vishal Misra
Columbia University, USA
,
Prashant Shenoy
University of Massachusetts, USA

ACM SIGMETRICS Performance Evaluation Review Volume 36, Issue 1
SIGMETRICS '08
June 2008
469 pages
ISSN:0163-5999
DOI:10.1145/1384529
Issue’s Table of Contents

Copyright © 2008 ACM.

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Published: 02 June 2008

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Cited By

Booth JKotra JZhao HKandemir MRaghavan P(2015)Phase Detection with Hidden Markov Models for DVFS on Many-Core Processors2015 IEEE 35th International Conference on Distributed Computing Systems10.1109/ICDCS.2015.27(185-195)Online publication date: Jun-2015
https://doi.org/10.1109/ICDCS.2015.27
Shin DKim WKwon SHan T(2011)Communication-aware VFI partitioning for GALS-based networks-on-chipDesign Automation for Embedded Systems10.1007/s10617-011-9070-x15:2(89-109)Online publication date: 1-Jun-2011
https://dl.acm.org/doi/10.1007/s10617-011-9070-x
Ozturk OKandemir MIrwin MNarayanan S(2010)Compiler directed network-on-chip reliability enhancement for chip multiprocessorsACM SIGPLAN Notices10.1145/1755951.175590245:4(85-94)Online publication date: 13-Apr-2010
https://dl.acm.org/doi/10.1145/1755951.1755902
Ozturk OKandemir MIrwin MNarayanan SLee JChilders B(2010)Compiler directed network-on-chip reliability enhancement for chip multiprocessorsProceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems10.1145/1755888.1755902(85-94)Online publication date: 13-Apr-2010
https://dl.acm.org/doi/10.1145/1755888.1755902

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