research-article

MemScale: active low-power modes for main memory

Authors:

Thomas F. Wenisch,

Ricardo BianchiniAuthors Info & Claims

ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

Pages 225 - 238

https://doi.org/10.1145/1950365.1950392

Published: 05 March 2011 Publication History

Abstract

Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. However, these states require entire DRAM ranks to be idled, which is difficult to achieve even in lightly loaded servers. In this paper, we propose to conserve memory energy while improving its energy-proportionality by creating active low-power modes for it. Specifically, we propose MemScale, a scheme wherein we apply dynamic voltage and frequency scaling (DVFS) to the memory controller and dynamic frequency scaling (DFS) to the memory channels and DRAM devices. MemScale is guided by an operating system policy that determines the DVFS/DFS mode of the memory subsystem based on the current need for memory bandwidth, the potential energy savings, and the performance degradation that applications are willing to withstand. Our results demonstrate that MemScale reduces energy consumption significantly compared to modern memory energy management approaches. We conclude that the potential benefits of the MemScale mechanisms and policy more than compensate for their small hardware cost.

References

[1]

J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memory interfaces. SC '09 - Super Computing, 2009.

Digital Library

[2]

I. Akyildiz. On the exact and approximate throughput analysis of closed queuing networks with blocking. IEEE Transactions on Software Engineering, 14(1):62--70, 1988.

Digital Library

[3]

AMD. ACP -- The Truth About Power Consumption Starts Here, 2009. http://www.amd.com/us/Documents/43761C_ACP_WP_EE.pdf.

[4]

S. Balsamo, V. D. N. Persone, and R. Onvural. Analysis of Queuing Networks with Blocking. 2001.

Digital Library

[5]

L. A. Barroso and U. Hölzle. The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines. Synthesis Lectures on Computer Architecture, Jan. 2009.

Digital Library

[6]

L. A. Barroso and U. Hölzle. The Case for Energy-Proportional Computing. IEEE Computer, 40(12):33--37, December 2007.

Digital Library

[7]

N. Binkert, R. Dreslinski, L. Hsu, K. Lim, a.G. Saidi, and S. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52--60, July 2006.

Digital Library

[8]

R. Crisp. Direct Rambus Technology: The New Main Memory Standard. IEEE Micro, 1997.

Digital Library

[9]

R. Das, O. Mutlu, T. Moscibroda, and C. R. Das. Aérgia : Exploiting Packet Latency Slack in On-Chip Networks. ISCA '10: International Symposium on Computer Architecture, 2010.

Digital Library

[10]

V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, 50(11), 2001.

Digital Library

[11]

B. Diniz, D. Guedes, W. M. Jr, and R. Bianchini. Limiting the Power Consumption of Main Memory. ISCA '07: International Symposium on Computer Architecture, 2007.

Digital Library

[12]

EPA. Report to Congress on Server and Data Center Energy Efficiency Public Law 109--431, 2007.

[13]

X. Fan, C. Ellis, and A. Lebeck. Memory Controller Policies for DRAM Power Management. In Proceedings of the International Symposium on Low-Power Electronics and Design, August 2001.

Digital Library

[14]

W. Felter, K. Rajamani, T. Keller, and C. Rusu. A Performance-Conserving Approach for Reducing Peak Power Consumption in Server Systems. ICS '05: International Conference on Supercomputing, 2005.

Digital Library

[15]

Google. Going Green at Google, 2010.

[16]

E. Gorbatov, 2010. Personal communication.

[17]

M. S. Gupta, G.-Y. Wei, and D. Brooks. System level analysis of fast, per-core DVFS using on-chip switching regulators. HPCA '08: High Performance Computer Architecture, 2008.

[18]

H. Hanson and K. Rajamani. What Computer Architects Need to Know About Memory Throttling. WEED '10: Workshop on Energy-Efficient Design, 2010.

Digital Library

[19]

S. Herbert and D. Marculescu. Analysis of Dynamic Voltage/Frequency Scaling in Chip-Multiprocessors. ISLPED '07: International Symposium on Low Power Electronics and Design, 2007.

Digital Library

[20]

H. Huang, P. Pillai, and K. G. Shin. Design and Implementation of Power-Aware Virtual Memory. In Proceedings of the USENIX Annual Technical Conference, June 2003.

Digital Library

[21]

Intel. Intel Xeon Processor 5600 Series, 2010.

[22]

B. Jacob, S. W. Ng, and D. T. Wang. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers, 2007.

Digital Library

[23]

JEDEC. DDR3 SDRAM Standard, 2009.

[24]

A. R. Lebeck, X. Fan, H. Zeng, and C. Ellis. Power Aware Page Allocation. ASPLOS '00: Architectural Support for Programming Languages and Operating Systems, 2000.

Digital Library

[25]

C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller. Energy Management for Commercial Servers. IEEE Computer, 36(12), December 2003.

Digital Library

[26]

D. Levinthal. Performance Analysis Guide for Intel Core i7 Processor and Intel Xeon 5500 processors, 2009.

[27]

X. Li, Z. Li, F. M. David, P. Zhou, Y. Zhou, S. V. Adve, and S. Kumar. Performance-directed energy management for main memory and disks. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, October 2004.

Digital Library

[28]

K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. K. Reinhardt, and T. F. Wenisch. Disaggregated Memory for Expansion and Sharing in Blade Servers. ISCA '09: International Symposium on Computer Architecture, 2009.

Digital Library

[29]

J. Lin, H. Zheng, Z. Zhu, H. David, and Z. Zhang. Thermal Modeling and Management of DRAM Memory Systems. ISCA '07: International Symposium on Computer Architecture, 2007.

Digital Library

[30]

J. Lin, H. Zheng, Z. Zhu, E. Gorbatov, H. David, and Z. Zhang. Software Thermal Management of DRAM Memory for Multicore Systems. SIGMETRICS, pages 337--348, 2008.

Digital Library

[31]

D. Meisner, B. T. Gold, and T. F. Wenisch. PowerNap: Eliminating Server Idle Power. ASPLOS '09: Architectural Support for Programming Languages and Operating Systems, Feb. 2009.

Digital Library

[32]

Micron. 1Gb: x4, x8, x16 DDR3 SDRAM, 2006.

[33]

Micron. Calculating Memory System Power for DDR3, July 2007.

[34]

A. Miyoshi, C. Lefurgy, E. V. Hensbergen, R. Rajamony, and R. Rajkumar. Critical Power Slope : Understanding the Runtime Effects of Frequency Scaling. ICS '02: International Conference on Supercomputing, 2002.

Digital Library

[35]

J. Moore, J. S. Chase, and P. Ranganathan. Weatherman: Automated, Online and Predictive Thermal Mapping and Management for Data Centers. ICAC '06: International Conference on Autonomic Computing, 2006.

Digital Library

[36]

V. Pandey, W. Jiang, Y. Zhou, and R. Bianchini. DMA-Aware Memory Energy Management. HPCA '06: High-Performance Computer Architecture, 2006.

[37]

S. Pelley, D. Meisner, P. Zandevakili, T. F. Wenisch, and J. Underwood. Power Routing : Dynamic Power Provisioning in the Data Center. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.

Digital Library

[38]

E. Perelman, G. Hamerly, M. V. Biesbrouck, T. Sherwood, and B. Calder. Using SimPoint for Accurate and Efficient Simulation Erez Perelman. SIGMETRICS, 2003.

Digital Library

[39]

L. Ramos and R. Bianchini. C-Oracle: Predictive thermal management for data centers. HPCA '08: High Performance Computer Architecture, Feb. 2008.

[40]

K. Sudan, N. Chatterjee, D. Nellans, M. Awasthi, Rajeev Balasubramonian, and A. Davis. Micro-Pages : Increasing DRAM Efficiency with Locality-Aware Data Placement. ASPLOS '10: Architectural Support for Programming Languages and Operating Systems, 2010.

Digital Library

[41]

N. Tolia, Z. Wang, M. Marwah, C. Bash, P. Ranganathan, and X. Zhu. Delivering Energy Proportionality with Non Energy-Proportional Systems â Optimizing the Ensemble. HotPower, 2008.

Digital Library

[42]

D. Tsirogiannis, S. Harizopoulos, and M. A. Shah. Analyzing the energy efficiency of a database server. SIGMOD, 2010.

Digital Library

[43]

A. N. Udipi, N. Muralimanohar, N. Chatterjee, Rajeev Balasubramonian, A. Davis, and N. P. Jouppi. Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores. ISCA '10: International Symposium on Computer Architecture, 2010.

Digital Library

[44]

H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. MICRO '08: Symposium on Microarchitecture, Nov. 2008.

Digital Library

[45]

H. Zheng, J. Lin, Z. Zhang, and Z. Zhu. Decoupled DIMM : Building High-Bandwidth Memory System Using Low-Speed DRAM Devices. ISCA '09: International Symposium on Computer Architecture, 2009.

Digital Library

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Index Terms

MemScale: active low-power modes for main memory
1. Computer systems organization

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MemScale: active low-power modes for main memory
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Main memory accounts for a growing fraction of server energy usage. Investigating active low-power modes for managing main memory, with a system called MemScale, the authors offer a solution for performance-aware energy management. By creating a set of ...

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cover image ACM Conferences

ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems

March 2011

432 pages

ISBN:9781450302661

DOI:10.1145/1950365

General Chair:
Rajiv Gupta
University of California, Riverside
,
Program Chair:
Todd C. Mowry
Carnegie Mellon University

ACM SIGARCH Computer Architecture News Volume 39, Issue 1
ASPLOS '11
March 2011
407 pages
ISSN:0163-5964
DOI:10.1145/1961295
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 46, Issue 3
ASPLOS '11
March 2011
407 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1961296
Issue’s Table of Contents

Copyright © 2011 ACM.

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Published: 05 March 2011

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https://doi.org/10.1109/IPDPS57955.2024.00036
Chen JManivannan MGoel BPericàs M(2023)JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy EfficiencyProceedings of the 52nd International Conference on Parallel Processing10.1145/3605573.3605586(828-838)Online publication date: 7-Aug-2023
https://dl.acm.org/doi/10.1145/3605573.3605586
Oliveira GGhose SGómez-Luna JBoroumand ASavery ARao SQazi SGrignou GThakur RShiu EMutlu O(2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3317884
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