Cited By
View all- Reis DNiemier MHu X(2018)Computing in memory with FeFETsProceedings of the International Symposium on Low Power Electronics and Design10.1145/3218603.3218640(1-6)Online publication date: 23-Jul-2018
Endurance management for resistive logic-in-memory computing architectures
Abstract
Resistive Random Access Memory (RRAM) is a promising non-volatile memory technology which enables modern in-memory computing architectures. Although RRAMs are known to be superior to conventional memories in many aspects, they suffer from a low write endurance. In this paper, we focus on balancing memory write traffic as a solution to extend the lifetime of resistive crossbar architectures. As a case study, we monitor the write traffic in a Programmable Logic-in-Memory (PLiM) architecture, and propose an endurance management scheme for it. The proposed endurance-aware compilation is capable of handling different trade-offs between write balance, latency, and area of the resulting PLiM implementations. Experimental evaluations on a set of benchmarks including large arithmetic and control functions show that the standard deviation of writes can be reduced by 86.65% on average compared to a naive compiler, while the average number of instructions and RRAM devices also decreases by 36.45% and 13.67%, respectively.
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March 2017
1814 pages
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European Design and Automation Association
Leuven, Belgium
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Published: 27 March 2017
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View all- Reis DNiemier MHu X(2018)Computing in memory with FeFETsProceedings of the International Symposium on Low Power Electronics and Design10.1145/3218603.3218640(1-6)Online publication date: 23-Jul-2018
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